From 2260a4bbbaedc3528e5b1ebbf2ebd16ee6e40769 Mon Sep 17 00:00:00 2001 From: Job Noorman Date: Mon, 12 Aug 2024 12:01:09 +0200 Subject: [PATCH] ir3: fix spill/reload split src/dst regs When splitting spills/reloads into to multiple separate spills/reloads, the src/dst registers where not adjusted. This caused the separate instructions too all refer to the same register. Signed-off-by: Job Noorman Part-of: --- src/freedreno/ir3/ir3_lower_spill.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/freedreno/ir3/ir3_lower_spill.c b/src/freedreno/ir3/ir3_lower_spill.c index f5782786af4..4b3ce660957 100644 --- a/src/freedreno/ir3/ir3_lower_spill.c +++ b/src/freedreno/ir3/ir3_lower_spill.c @@ -139,6 +139,8 @@ split_spill(struct ir3_instruction *spill) if (clone->srcs[1]->flags & IR3_REG_ARRAY) { clone->srcs[1]->num = clone->srcs[1]->array.base + comp; clone->srcs[1]->flags &= ~IR3_REG_ARRAY; + } else { + clone->srcs[1]->num += comp; } clone->srcs[2]->uim_val = components; @@ -173,6 +175,8 @@ split_reload(struct ir3_instruction *reload) if (clone->dsts[0]->flags & IR3_REG_ARRAY) { clone->dsts[0]->num = clone->dsts[0]->array.base + comp; clone->dsts[0]->flags &= ~IR3_REG_ARRAY; + } else { + clone->dsts[0]->num += comp; } clone->srcs[2]->uim_val = components;