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gallivm/nir: handle bool registers.

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lowering to 32-bit bools doesn't get rid of register stores,
so handle those.

Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>
This commit is contained in:
Dave Airlie 2020-12-22 15:38:06 +10:00
parent 2a9e98130b
commit 224069cefd
1 changed files with 2 additions and 1 deletions
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3
src/gallium/auxiliary/gallivm/lp_bld_nir.c
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@ -78,6 +78,7 @@ static LLVMValueRef cast_type(struct lp_build_nir_context *bld_base, LLVMValueRe
return LLVMBuildBitCast(builder, val, bld_base->uint8_bld.vec_type, "");
case 16:
return LLVMBuildBitCast(builder, val, bld_base->uint16_bld.vec_type, "");
case 1:
case 32:
return LLVMBuildBitCast(builder, val, bld_base->uint_bld.vec_type, "");
case 64:
@ -2211,7 +2212,7 @@ handle_shader_output_decl(struct lp_build_nir_context *bld_base,
static LLVMTypeRef get_register_type(struct lp_build_nir_context *bld_base,
nir_register *reg)
{
struct lp_build_context *int_bld = get_int_bld(bld_base, true, reg->bit_size);
struct lp_build_context *int_bld = get_int_bld(bld_base, true, reg->bit_size == 1 ? 32 : reg->bit_size);
LLVMTypeRef type = int_bld->vec_type;
if (reg->num_array_elems)