From 224069cefdd162efae87f0f515d6203f56e9cd53 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 22 Dec 2020 15:38:06 +1000 Subject: [PATCH] gallivm/nir: handle bool registers. lowering to 32-bit bools doesn't get rid of register stores, so handle those. Acked-by: Adam Jackson Reviewed-by: Roland Scheidegger Part-of: --- src/gallium/auxiliary/gallivm/lp_bld_nir.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_nir.c b/src/gallium/auxiliary/gallivm/lp_bld_nir.c index f637f11eaf1..a98ea75abe5 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_nir.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_nir.c @@ -78,6 +78,7 @@ static LLVMValueRef cast_type(struct lp_build_nir_context *bld_base, LLVMValueRe return LLVMBuildBitCast(builder, val, bld_base->uint8_bld.vec_type, ""); case 16: return LLVMBuildBitCast(builder, val, bld_base->uint16_bld.vec_type, ""); + case 1: case 32: return LLVMBuildBitCast(builder, val, bld_base->uint_bld.vec_type, ""); case 64: @@ -2211,7 +2212,7 @@ handle_shader_output_decl(struct lp_build_nir_context *bld_base, static LLVMTypeRef get_register_type(struct lp_build_nir_context *bld_base, nir_register *reg) { - struct lp_build_context *int_bld = get_int_bld(bld_base, true, reg->bit_size); + struct lp_build_context *int_bld = get_int_bld(bld_base, true, reg->bit_size == 1 ? 32 : reg->bit_size); LLVMTypeRef type = int_bld->vec_type; if (reg->num_array_elems)