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radv: add RADV_CMD_DIRTY_COMPUTE_PIPELINE

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This seems cleaner than storing the last emitted compute pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41136>
This commit is contained in:
Samuel Pitoiset 2026-04-23 12:29:23 +02:00 • committed by Marge Bot
parent c7c2ce13ae
commit 20f7fba442
2 changed files with 50 additions and 52 deletions
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24
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -8545,15 +8545,10 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_compu
const struct radv_physical_device *pdev = radv_device_physical(device);
struct radv_cmd_stream *cs = radv_get_pm4_cs(cmd_buffer);
if (pipeline == cmd_buffer->state.emitted_compute_pipeline)
return;
radeon_check_space(device->ws, cs->b, pdev->info.gfx_level >= GFX10 ? 25 : 22);
radv_emit_compute_shader(pdev, cs, cmd_buffer->state.shaders[MESA_SHADER_COMPUTE]);
cmd_buffer->state.emitted_compute_pipeline = pipeline;
if (radv_device_fault_detection_enabled(device))
radv_save_pipeline(cmd_buffer, &pipeline->base);
}
@ -9086,6 +9081,7 @@ radv_bind_compute_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_compu
radv_bind_shader(cmd_buffer, compute_pipeline->base.shaders[MESA_SHADER_COMPUTE], MESA_SHADER_COMPUTE);
cmd_buffer->state.compute_pipeline = compute_pipeline;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_COMPUTE_PIPELINE;
cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_CS;
}
@ -10042,7 +10038,6 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
device->ws->cs_execute_secondary(primary_cs->b, secondary_cs->b, allow_ib2);
primary->state.emitted_compute_pipeline = secondary->state.emitted_compute_pipeline;
primary->state.emitted_rt_pipeline = secondary->state.emitted_rt_pipeline;
primary->state.emitted_vs_prolog = secondary->state.emitted_vs_prolog;
@ -10098,9 +10093,10 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
* some states.
*/
primary->state.dirty_dynamic |= RADV_DYNAMIC_ALL;
primary->state.dirty |= RADV_CMD_DIRTY_GRAPHICS_PIPELINE | RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_GUARDBAND |
RADV_CMD_DIRTY_SHADER_QUERY | RADV_CMD_DIRTY_OCCLUSION_QUERY |
RADV_CMD_DIRTY_DB_SHADER_CONTROL | RADV_CMD_DIRTY_FRAGMENT_OUTPUT;
primary->state.dirty |= RADV_CMD_DIRTY_GRAPHICS_PIPELINE | RADV_CMD_DIRTY_COMPUTE_PIPELINE |
RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_GUARDBAND | RADV_CMD_DIRTY_SHADER_QUERY |
RADV_CMD_DIRTY_OCCLUSION_QUERY | RADV_CMD_DIRTY_DB_SHADER_CONTROL |
RADV_CMD_DIRTY_FRAGMENT_OUTPUT;
radv_mark_descriptors_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
radv_mark_descriptors_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
@ -14270,11 +14266,13 @@ radv_before_dispatch(struct radv_cmd_buffer *cmd_buffer, struct radv_compute_pip
const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
struct radv_cmd_stream *cs = radv_get_pm4_cs(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
const bool pipeline_is_dirty = pipeline != cmd_buffer->state.emitted_compute_pipeline;
const bool pipeline_is_dirty = !!(cmd_buffer->state.dirty & RADV_CMD_DIRTY_COMPUTE_PIPELINE);
/* Use the optimal packet order similar to draws. */
if (pipeline)
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_COMPUTE_PIPELINE) {
radv_emit_compute_pipeline(cmd_buffer, pipeline);
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_COMPUTE_PIPELINE;
}
radv_upload_compute_shader_descriptors(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE);
@ -14360,7 +14358,7 @@ radv_before_trace_rays(struct radv_cmd_buffer *cmd_buffer, struct radv_ray_traci
*/
radv_mark_descriptors_dirty(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE);
cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
cmd_buffer->state.emitted_compute_pipeline = NULL;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_COMPUTE_PIPELINE;
}
}
@ -16226,7 +16224,7 @@ radv_reset_pipeline_state(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoin
radv_bind_shader(cmd_buffer, NULL, MESA_SHADER_COMPUTE);
cmd_buffer->state.compute_pipeline = NULL;
}
cmd_buffer->state.emitted_compute_pipeline = NULL;
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_COMPUTE_PIPELINE;
break;
case VK_PIPELINE_BIND_POINT_GRAPHICS:
if (cmd_buffer->state.graphics_pipeline) {

78
src/amd/vulkan/radv_cmd_buffer.h
View file

@ -86,44 +86,45 @@ enum radv_dynamic_state_bits {
enum radv_cmd_dirty_bits {
RADV_CMD_DIRTY_GRAPHICS_PIPELINE = 1ull << 0,
RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 1,
RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 2,
RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 3,
RADV_CMD_DIRTY_GUARDBAND = 1ull << 4,
RADV_CMD_DIRTY_RBPLUS = 1ull << 5,
RADV_CMD_DIRTY_OCCLUSION_QUERY = 1ull << 6,
RADV_CMD_DIRTY_DB_SHADER_CONTROL = 1ull << 7,
RADV_CMD_DIRTY_STREAMOUT_ENABLE = 1ull << 8,
RADV_CMD_DIRTY_GRAPHICS_SHADERS = 1ull << 9,
RADV_CMD_DIRTY_FRAGMENT_OUTPUT = 1ull << 10,
RADV_CMD_DIRTY_PS_STATE = 1ull << 11,
RADV_CMD_DIRTY_NGG_STATE = 1ull << 12,
RADV_CMD_DIRTY_TASK_STATE = 1ull << 13,
RADV_CMD_DIRTY_DEPTH_STENCIL_STATE = 1ull << 14,
RADV_CMD_DIRTY_RASTER_STATE = 1ull << 15,
RADV_CMD_DIRTY_MSAA_STATE = 1ull << 16,
RADV_CMD_DIRTY_CLIP_RECTS_STATE = 1ull << 17,
RADV_CMD_DIRTY_TCS_TES_STATE = 1ull << 18,
RADV_CMD_DIRTY_CB_RENDER_STATE = 1ull << 19,
RADV_CMD_DIRTY_VIEWPORT_STATE = 1ull << 20,
RADV_CMD_DIRTY_BINNING_STATE = 1ull << 21,
RADV_CMD_DIRTY_FSR_STATE = 1ull << 22,
RADV_CMD_DIRTY_RAST_SAMPLES_STATE = 1ull << 23,
RADV_CMD_DIRTY_DEPTH_BIAS_STATE = 1ull << 24,
RADV_CMD_DIRTY_VS_PROLOG_STATE = 1ull << 25,
RADV_CMD_DIRTY_BLEND_CONSTANTS_STATE = 1ull << 26,
RADV_CMD_DIRTY_SAMPLE_LOCATIONS_STATE = 1ull << 27,
RADV_CMD_DIRTY_SCISSOR_STATE = 1ull << 28,
RADV_CMD_DIRTY_TESS_DOMAIN_ORIGIN_STATE = 1ull << 29,
RADV_CMD_DIRTY_LS_HS_CONFIG = 1ull << 30,
RADV_CMD_DIRTY_VGT_PRIM_STATE = 1ull << 31,
RADV_CMD_DIRTY_FORCE_VRS_STATE = 1ull << 32,
RADV_CMD_DIRTY_NGGC_VIEWPORT = 1ull << 33,
RADV_CMD_DIRTY_NGGC_SETTINGS = 1ull << 34,
RADV_CMD_DIRTY_PS_EPILOG_SHADER = 1ull << 35,
RADV_CMD_DIRTY_PS_EPILOG_STATE = 1ull << 36,
RADV_CMD_DIRTY_GFX12_HIZ_WA_STATE = 1ull << 37,
RADV_CMD_DIRTY_ALL = (1ull << 38) - 1,
RADV_CMD_DIRTY_COMPUTE_PIPELINE = 1ull << 1,
RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 2,
RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 3,
RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 4,
RADV_CMD_DIRTY_GUARDBAND = 1ull << 5,
RADV_CMD_DIRTY_RBPLUS = 1ull << 6,
RADV_CMD_DIRTY_OCCLUSION_QUERY = 1ull << 7,
RADV_CMD_DIRTY_DB_SHADER_CONTROL = 1ull << 8,
RADV_CMD_DIRTY_STREAMOUT_ENABLE = 1ull << 9,
RADV_CMD_DIRTY_GRAPHICS_SHADERS = 1ull << 10,
RADV_CMD_DIRTY_FRAGMENT_OUTPUT = 1ull << 11,
RADV_CMD_DIRTY_PS_STATE = 1ull << 12,
RADV_CMD_DIRTY_NGG_STATE = 1ull << 13,
RADV_CMD_DIRTY_TASK_STATE = 1ull << 14,
RADV_CMD_DIRTY_DEPTH_STENCIL_STATE = 1ull << 15,
RADV_CMD_DIRTY_RASTER_STATE = 1ull << 16,
RADV_CMD_DIRTY_MSAA_STATE = 1ull << 17,
RADV_CMD_DIRTY_CLIP_RECTS_STATE = 1ull << 18,
RADV_CMD_DIRTY_TCS_TES_STATE = 1ull << 19,
RADV_CMD_DIRTY_CB_RENDER_STATE = 1ull << 20,
RADV_CMD_DIRTY_VIEWPORT_STATE = 1ull << 21,
RADV_CMD_DIRTY_BINNING_STATE = 1ull << 22,
RADV_CMD_DIRTY_FSR_STATE = 1ull << 23,
RADV_CMD_DIRTY_RAST_SAMPLES_STATE = 1ull << 24,
RADV_CMD_DIRTY_DEPTH_BIAS_STATE = 1ull << 25,
RADV_CMD_DIRTY_VS_PROLOG_STATE = 1ull << 26,
RADV_CMD_DIRTY_BLEND_CONSTANTS_STATE = 1ull << 27,
RADV_CMD_DIRTY_SAMPLE_LOCATIONS_STATE = 1ull << 28,
RADV_CMD_DIRTY_SCISSOR_STATE = 1ull << 29,
RADV_CMD_DIRTY_TESS_DOMAIN_ORIGIN_STATE = 1ull << 30,
RADV_CMD_DIRTY_LS_HS_CONFIG = 1ull << 31,
RADV_CMD_DIRTY_VGT_PRIM_STATE = 1ull << 32,
RADV_CMD_DIRTY_FORCE_VRS_STATE = 1ull << 33,
RADV_CMD_DIRTY_NGGC_VIEWPORT = 1ull << 34,
RADV_CMD_DIRTY_NGGC_SETTINGS = 1ull << 35,
RADV_CMD_DIRTY_PS_EPILOG_SHADER = 1ull << 36,
RADV_CMD_DIRTY_PS_EPILOG_STATE = 1ull << 37,
RADV_CMD_DIRTY_GFX12_HIZ_WA_STATE = 1ull << 38,
RADV_CMD_DIRTY_ALL = (1ull << 39) - 1,
RADV_CMD_DIRTY_SHADER_QUERY = RADV_CMD_DIRTY_NGG_STATE | RADV_CMD_DIRTY_TASK_STATE,
};
@ -341,7 +342,6 @@ struct radv_cmd_state {
struct radv_graphics_pipeline *graphics_pipeline;
struct radv_compute_pipeline *compute_pipeline;
struct radv_compute_pipeline *emitted_compute_pipeline;
struct radv_ray_tracing_pipeline *rt_pipeline;
struct radv_ray_tracing_pipeline *emitted_rt_pipeline;
struct radv_dynamic_state dynamic;