fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-07 07:08:04 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

radv: stop tracking the last emitted graphics pipeline

Browse source 
This shouldn't have any effects because there is a dirty bit and
binding the same graphics pipeline doesn't trigger it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41136>
This commit is contained in:
Samuel Pitoiset 2026-04-23 13:07:31 +02:00 • committed by Marge Bot
parent 6af89db05c
commit c7c2ce13ae
2 changed files with 0 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -3998,9 +3998,6 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
struct radv_cmd_stream *cs = cmd_buffer->cs;
if (cmd_buffer->state.emitted_graphics_pipeline == pipeline)
return;
radv_emit_graphics_shaders(cmd_buffer);
if (pipeline->sqtt_shaders_reloc) {
@ -4012,8 +4009,6 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
if (radv_device_fault_detection_enabled(device))
radv_save_pipeline(cmd_buffer, &pipeline->base);
cmd_buffer->state.emitted_graphics_pipeline = pipeline;
}
static bool
@ -6061,8 +6056,6 @@ emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v
enum amd_gfx_level chip = pdev->info.gfx_level;
assert(cmd_buffer->state.emitted_graphics_pipeline == cmd_buffer->state.graphics_pipeline);
if (vs_shader->info.merged_shader_compiled_separately) {
if (vs_shader->info.next_stage == MESA_SHADER_GEOMETRY) {
radv_shader_combine_cfg_vs_gs(device, vs_shader, cmd_buffer->state.shaders[MESA_SHADER_GEOMETRY], &rsrc1,
@ -10049,7 +10042,6 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
device->ws->cs_execute_secondary(primary_cs->b, secondary_cs->b, allow_ib2);
primary->state.emitted_graphics_pipeline = secondary->state.emitted_graphics_pipeline;
primary->state.emitted_compute_pipeline = secondary->state.emitted_compute_pipeline;
primary->state.emitted_rt_pipeline = secondary->state.emitted_rt_pipeline;
@ -16263,7 +16255,6 @@ radv_reset_pipeline_state(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoin
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAGMENT_OUTPUT;
}
}
cmd_buffer->state.emitted_graphics_pipeline = NULL;
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_GRAPHICS_PIPELINE;
break;
default:

1
src/amd/vulkan/radv_cmd_buffer.h
View file

@ -340,7 +340,6 @@ struct radv_cmd_state {
uint32_t prefetch_L2_mask;
struct radv_graphics_pipeline *graphics_pipeline;
struct radv_graphics_pipeline *emitted_graphics_pipeline;
struct radv_compute_pipeline *compute_pipeline;
struct radv_compute_pipeline *emitted_compute_pipeline;
struct radv_ray_tracing_pipeline *rt_pipeline;