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freedreno/ir3: output ir3 and nir asm for frameretrace
See: 298dc8195b
Signed-off-by: Rob Clark <robdclark@gmail.com>
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4 changed files with 69 additions and 0 deletions
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@ -25,6 +25,17 @@
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#define DISASM_H_
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#include <stdio.h>
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#include <stdbool.h>
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#include "util/u_debug.h"
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enum fd_shader_debug {
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FD_DBG_SHADER_VS = 0x01,
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FD_DBG_SHADER_FS = 0x02,
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FD_DBG_SHADER_CS = 0x04,
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};
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extern enum fd_shader_debug fd_shader_debug;
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enum shader_t {
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SHADER_VERTEX,
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@ -36,6 +47,38 @@ enum shader_t {
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SHADER_MAX,
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};
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static inline bool
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shader_debug_enabled(enum shader_t type)
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{
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switch (type) {
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case SHADER_VERTEX: return !!(fd_shader_debug & FD_DBG_SHADER_VS);
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case SHADER_FRAGMENT: return !!(fd_shader_debug & FD_DBG_SHADER_FS);
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case SHADER_COMPUTE: return !!(fd_shader_debug & FD_DBG_SHADER_CS);
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default:
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debug_assert(0);
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return false;
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}
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}
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static inline const char *
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shader_stage_name(enum shader_t type)
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{
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/* NOTE these names are chosen to match the INTEL_DEBUG output
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* which frameretrace parses. Hurray accidental ABI!
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*/
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switch (type) {
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case SHADER_VERTEX: return "vertex";
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case SHADER_TCS: return "tessellation control";
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case SHADER_TES: return "tessellation evaluation";
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case SHADER_GEOM: return "geometry";
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case SHADER_FRAGMENT: return "fragment";
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case SHADER_COMPUTE: return "compute";
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default:
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debug_assert(0);
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return NULL;
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}
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}
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/* bitmask of debug flags */
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enum debug_t {
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PRINT_RAW = 0x1, /* dump raw hexdump */
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@ -93,6 +93,17 @@ int fd_mesa_debug = 0;
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bool fd_binning_enabled = true;
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static bool glsl120 = false;
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static const struct debug_named_value shader_debug_options[] = {
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{"vs", FD_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
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{"fs", FD_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
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{"cs", FD_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
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DEBUG_NAMED_VALUE_END
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};
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DEBUG_GET_ONCE_FLAGS_OPTION(fd_shader_debug, "FD_SHADER_DEBUG", shader_debug_options, 0)
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enum fd_shader_debug fd_shader_debug = 0;
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static const char *
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fd_screen_get_name(struct pipe_screen *pscreen)
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{
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@ -783,6 +794,7 @@ fd_screen_create(struct fd_device *dev)
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uint64_t val;
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fd_mesa_debug = debug_get_option_fd_mesa_debug();
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fd_shader_debug = debug_get_option_fd_shader_debug();
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if (fd_mesa_debug & FD_DBG_NOBIN)
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fd_binning_enabled = false;
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@ -220,6 +220,12 @@ compile_init(struct ir3_compiler *compiler,
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nir_print_shader(ctx->s, stdout);
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}
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if (shader_debug_enabled(so->type)) {
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fprintf(stderr, "NIR (final form) for %s shader:\n",
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shader_stage_name(so->type));
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nir_print_shader(ctx->s, stderr);
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}
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ir3_nir_scan_driver_consts(ctx->s, &so->const_layout);
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so->num_uniforms = ctx->s->num_uniforms;
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@ -162,6 +162,14 @@ assemble_variant(struct ir3_shader_variant *v)
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ir3_shader_disasm(v, bin, stdout);
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}
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if (shader_debug_enabled(v->shader->type)) {
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fprintf(stderr, "Native code for unnamed %s shader %s:\n",
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shader_stage_name(v->shader->type), v->shader->nir->info.name);
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if (v->shader->type == SHADER_FRAGMENT)
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fprintf(stderr, "SIMD0\n");
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ir3_shader_disasm(v, bin, stderr);
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}
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free(bin);
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/* no need to keep the ir around beyond this point: */
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