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freedreno/ir3: redirectable ir3 disasm output
For now it still goes to stdout, this will make it easier to support output on stderr like what frameretrace expects. (If we eventually have a proper GL extension for this, implementation probably looks like dumping shader disasm to a tmp file and then dumping that out over whatever mechanism is used.) Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
4c58db8064
commit
e4c225ab6f
3 changed files with 48 additions and 50 deletions
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@ -56,7 +56,7 @@ static void dump_info(struct ir3_shader_variant *so, const char *str)
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const char *type = ir3_shader_stage(so->shader);
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bin = ir3_shader_assemble(so, so->shader->compiler->gpu_id);
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debug_printf("; %s: %s\n", type, str);
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ir3_shader_disasm(so, bin);
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ir3_shader_disasm(so, bin, stdout);
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free(bin);
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}
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@ -157,9 +157,9 @@ assemble_variant(struct ir3_shader_variant *v)
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if (fd_mesa_debug & FD_DBG_DISASM) {
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struct ir3_shader_key key = v->key;
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DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
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printf("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
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key.binning_pass, key.color_two_side, key.half_precision);
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ir3_shader_disasm(v, bin);
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ir3_shader_disasm(v, bin, stdout);
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}
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free(bin);
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@ -375,29 +375,29 @@ ir3_shader_create_compute(struct ir3_compiler *compiler,
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/* do first pass optimization, ignoring the key: */
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shader->nir = ir3_optimize_nir(shader, nir, NULL);
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if (fd_mesa_debug & FD_DBG_DISASM) {
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DBG("dump nir%d: type=%d", shader->id, shader->type);
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printf("dump nir%d: type=%d\n", shader->id, shader->type);
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nir_print_shader(shader->nir, stdout);
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}
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return shader;
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}
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static void dump_reg(const char *name, uint32_t r)
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static void dump_reg(FILE *out, const char *name, uint32_t r)
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{
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if (r != regid(63,0))
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debug_printf("; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
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fprintf(out, "; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
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}
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static void dump_output(struct ir3_shader_variant *so,
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static void dump_output(FILE *out, struct ir3_shader_variant *so,
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unsigned slot, const char *name)
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{
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uint32_t regid;
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regid = ir3_find_output_regid(so, slot);
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dump_reg(name, regid);
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dump_reg(out, name, regid);
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}
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void
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ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
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ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
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{
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struct ir3 *ir = so->ir;
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struct ir3_register *reg;
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@ -407,19 +407,19 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
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for (i = 0; i < ir->ninputs; i++) {
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if (!ir->inputs[i]) {
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debug_printf("; in%d unused\n", i);
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fprintf(out, "; in%d unused\n", i);
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continue;
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}
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reg = ir->inputs[i]->regs[0];
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regid = reg->num;
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debug_printf("@in(%sr%d.%c)\tin%d\n",
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fprintf(out, "@in(%sr%d.%c)\tin%d\n",
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(reg->flags & IR3_REG_HALF) ? "h" : "",
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(regid >> 2), "xyzw"[regid & 0x3], i);
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}
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for (i = 0; i < ir->noutputs; i++) {
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if (!ir->outputs[i]) {
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debug_printf("; out%d unused\n", i);
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fprintf(out, "; out%d unused\n", i);
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continue;
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}
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/* kill shows up as a virtual output.. skip it! */
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@ -427,65 +427,63 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
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continue;
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reg = ir->outputs[i]->regs[0];
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regid = reg->num;
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debug_printf("@out(%sr%d.%c)\tout%d\n",
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fprintf(out, "@out(%sr%d.%c)\tout%d\n",
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(reg->flags & IR3_REG_HALF) ? "h" : "",
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(regid >> 2), "xyzw"[regid & 0x3], i);
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}
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for (i = 0; i < so->immediates_count; i++) {
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debug_printf("@const(c%d.x)\t", so->constbase.immediate + i);
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debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
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fprintf(out, "@const(c%d.x)\t", so->constbase.immediate + i);
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fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
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so->immediates[i].val[0],
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so->immediates[i].val[1],
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so->immediates[i].val[2],
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so->immediates[i].val[3]);
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}
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#ifdef DEBUG
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disasm_a3xx(bin, so->info.sizedwords, 0, stdout);
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#endif
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disasm_a3xx(bin, so->info.sizedwords, 0, out);
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switch (so->type) {
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case SHADER_VERTEX:
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debug_printf("; %s: outputs:", type);
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fprintf(out, "; %s: outputs:", type);
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for (i = 0; i < so->outputs_count; i++) {
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uint8_t regid = so->outputs[i].regid;
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debug_printf(" r%d.%c (%s)",
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fprintf(out, " r%d.%c (%s)",
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(regid >> 2), "xyzw"[regid & 0x3],
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gl_varying_slot_name(so->outputs[i].slot));
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}
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debug_printf("\n");
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debug_printf("; %s: inputs:", type);
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fprintf(out, "\n");
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fprintf(out, "; %s: inputs:", type);
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for (i = 0; i < so->inputs_count; i++) {
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uint8_t regid = so->inputs[i].regid;
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debug_printf(" r%d.%c (cm=%x,il=%u,b=%u)",
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fprintf(out, " r%d.%c (cm=%x,il=%u,b=%u)",
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(regid >> 2), "xyzw"[regid & 0x3],
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so->inputs[i].compmask,
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so->inputs[i].inloc,
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so->inputs[i].bary);
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}
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debug_printf("\n");
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fprintf(out, "\n");
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break;
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case SHADER_FRAGMENT:
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debug_printf("; %s: outputs:", type);
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fprintf(out, "; %s: outputs:", type);
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for (i = 0; i < so->outputs_count; i++) {
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uint8_t regid = so->outputs[i].regid;
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debug_printf(" r%d.%c (%s)",
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fprintf(out, " r%d.%c (%s)",
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(regid >> 2), "xyzw"[regid & 0x3],
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gl_frag_result_name(so->outputs[i].slot));
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}
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debug_printf("\n");
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debug_printf("; %s: inputs:", type);
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fprintf(out, "\n");
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fprintf(out, "; %s: inputs:", type);
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for (i = 0; i < so->inputs_count; i++) {
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uint8_t regid = so->inputs[i].regid;
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debug_printf(" r%d.%c (%s,cm=%x,il=%u,b=%u)",
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fprintf(out, " r%d.%c (%s,cm=%x,il=%u,b=%u)",
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(regid >> 2), "xyzw"[regid & 0x3],
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gl_varying_slot_name(so->inputs[i].slot),
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so->inputs[i].compmask,
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so->inputs[i].inloc,
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so->inputs[i].bary);
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}
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debug_printf("\n");
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fprintf(out, "\n");
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break;
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default:
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/* TODO */
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@ -493,53 +491,53 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
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}
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/* print generic shader info: */
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debug_printf("; %s prog %d/%d: %u instructions, %d half, %d full\n",
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fprintf(out, "; %s prog %d/%d: %u instructions, %d half, %d full\n",
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type, so->shader->id, so->id,
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so->info.instrs_count,
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so->info.max_half_reg + 1,
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so->info.max_reg + 1);
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debug_printf("; %d const, %u constlen\n",
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fprintf(out, "; %d const, %u constlen\n",
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so->info.max_const + 1,
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so->constlen);
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debug_printf("; %u (ss), %u (sy)\n", so->info.ss, so->info.sy);
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fprintf(out, "; %u (ss), %u (sy)\n", so->info.ss, so->info.sy);
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/* print shader type specific info: */
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switch (so->type) {
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case SHADER_VERTEX:
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dump_output(so, VARYING_SLOT_POS, "pos");
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dump_output(so, VARYING_SLOT_PSIZ, "psize");
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dump_output(out, so, VARYING_SLOT_POS, "pos");
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dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
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break;
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case SHADER_FRAGMENT:
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dump_reg("pos (bary)", so->pos_regid);
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dump_output(so, FRAG_RESULT_DEPTH, "posz");
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dump_reg(out, "pos (bary)", so->pos_regid);
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dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
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if (so->color0_mrt) {
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dump_output(so, FRAG_RESULT_COLOR, "color");
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dump_output(out, so, FRAG_RESULT_COLOR, "color");
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} else {
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dump_output(so, FRAG_RESULT_DATA0, "data0");
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dump_output(so, FRAG_RESULT_DATA1, "data1");
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dump_output(so, FRAG_RESULT_DATA2, "data2");
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dump_output(so, FRAG_RESULT_DATA3, "data3");
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dump_output(so, FRAG_RESULT_DATA4, "data4");
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dump_output(so, FRAG_RESULT_DATA5, "data5");
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dump_output(so, FRAG_RESULT_DATA6, "data6");
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dump_output(so, FRAG_RESULT_DATA7, "data7");
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dump_output(out, so, FRAG_RESULT_DATA0, "data0");
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dump_output(out, so, FRAG_RESULT_DATA1, "data1");
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dump_output(out, so, FRAG_RESULT_DATA2, "data2");
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dump_output(out, so, FRAG_RESULT_DATA3, "data3");
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dump_output(out, so, FRAG_RESULT_DATA4, "data4");
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dump_output(out, so, FRAG_RESULT_DATA5, "data5");
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dump_output(out, so, FRAG_RESULT_DATA6, "data6");
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dump_output(out, so, FRAG_RESULT_DATA7, "data7");
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}
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/* these two are hard-coded since we don't know how to
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* program them to anything but all 0's...
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*/
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if (so->frag_coord)
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debug_printf("; fragcoord: r0.x\n");
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fprintf(out, "; fragcoord: r0.x\n");
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if (so->frag_face)
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debug_printf("; fragface: hr0.x\n");
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fprintf(out, "; fragface: hr0.x\n");
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break;
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default:
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/* TODO */
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break;
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}
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debug_printf("\n");
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fprintf(out, "\n");
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}
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uint64_t
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@ -381,7 +381,7 @@ ir3_shader_create_compute(struct ir3_compiler *compiler,
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void ir3_shader_destroy(struct ir3_shader *shader);
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struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
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struct ir3_shader_key key, struct pipe_debug_callback *debug);
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void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin);
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void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out);
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uint64_t ir3_shader_outputs(const struct ir3_shader *so);
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struct fd_ringbuffer;
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