From 1d8382b88e2a3eeb32a513d279e2a2296be80163 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Tue, 3 Jun 2025 18:11:43 +0300 Subject: [PATCH] brw: enable more lowering for bitfield manipulation at non 32bit sizes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Lionel Landwerlin Reviewed-by: José Roberto de Souza Part-of: --- src/intel/compiler/brw_compiler.c | 6 +++++- src/intel/compiler/brw_nir.c | 2 ++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 3ab2346cb3a..de5a9863b55 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -46,6 +46,8 @@ const struct nir_shader_compiler_options brw_scalar_nir_options = { .has_uclz = true, .lower_base_vertex = true, .lower_bitfield_extract = true, + .lower_bitfield_extract8 = true, + .lower_bitfield_extract16 = true, .lower_bitfield_insert = true, .lower_device_index_to_zero = true, .lower_fdiv = true, @@ -115,7 +117,9 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo) nir_lower_find_lsb64 | nir_lower_ufind_msb64 | nir_lower_bit_count64 | - nir_lower_iadd3_64; + nir_lower_iadd3_64 | + nir_lower_bitfield_extract64 | + nir_lower_bitfield_reverse64; nir_lower_doubles_options fp64_options = nir_lower_drcp | nir_lower_dsqrt | diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 760a4b9a549..71f325b1006 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -1072,6 +1072,8 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *data) * fewer MOV instructions. */ switch (alu->op) { + case nir_op_bitfield_reverse: + return alu->def.bit_size != 32 ? 32 : 0; case nir_op_idiv: case nir_op_imod: case nir_op_irem: