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intel/mi_builder: fix self modifying batches

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So far we only write a maximum of 4 dwords further into the batch and
it seems just going over the CS prefetch was enough.

Turns out writing more dwords can delay the writes and we start
prefetching stuff that hasn't landed in memory yet.

This fixes the issue by stalling the CS to ensure the writes have
landed before we go over the prefetch.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 796fccce63 ("intel/mi-builder: add framework for self modifying batches")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8525>
(cherry picked from commit d8154c4006)
This commit is contained in:
Lionel Landwerlin 2020-08-31 16:42:32 +03:00 • committed by Dylan Baker
parent d4a0136e26
commit 1d0a7bb520
2 changed files with 8 additions and 1 deletions
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2
.pick_status.json
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@ -112,7 +112,7 @@
"description": "intel/mi_builder: fix self modifying batches",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "796fccce631bf8ecb6ce2fd1a68f219788693a6e"
},

7
src/intel/common/gen_mi_builder.h
View file

@ -932,6 +932,13 @@ gen_mi_store_address(struct gen_mi_builder *b,
static inline void
gen_mi_self_mod_barrier(struct gen_mi_builder *b)
{
/* First make sure all the memory writes from previous modifying commands
* have landed. We want to do this before going through the CS cache,
* otherwise we could be fetching memory that hasn't been written to yet.
*/
gen_mi_builder_emit(b, GENX(PIPE_CONTROL), pc) {
pc.CommandStreamerStallEnable = true;
}
/* Documentation says Gen11+ should be able to invalidate the command cache
* but experiment show it doesn't work properly, so for now just get over
* the CS prefetch.