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tu: Reset BIN_FOVEAT regs for tiling with and without HW binning

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We didn't reset the regs when HW binning was disabled.

Fixes: b34b089ca1 ("tu: Use GRAS bin offset registers")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37373>
This commit is contained in:
Danylo Piliaiev 2025-08-29 15:54:02 +02:00 • committed by Marge Bot
parent 0bc0ead674
commit 1c57f88908
1 changed files with 6 additions and 6 deletions
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12
src/freedreno/vulkan/tu_cmd_buffer.cc
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@ -2099,12 +2099,6 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
const struct tu_framebuffer *fb = cmd->state.framebuffer;
const struct tu_tiling_config *tiling = cmd->state.tiling;
/* Reset bin scaling. */
if (phys_dev->info->a7xx.has_hw_bin_scaling) {
tu_cs_emit_regs(cs, A7XX_GRAS_BIN_FOVEAT());
tu_cs_emit_regs(cs, A7XX_RB_BIN_FOVEAT());
}
/* If this command buffer may be executed multiple times, then
* viewports/scissor states may have been changed by previous executions
* and we need to reset them before executing the binning IB. With FDM
@ -2634,6 +2628,12 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
tu7_emit_tile_render_begin_regs(cs);
}
/* Reset bin scaling. */
if (phys_dev->info->a7xx.has_hw_bin_scaling) {
tu_cs_emit_regs(cs, A7XX_GRAS_BIN_FOVEAT());
tu_cs_emit_regs(cs, A7XX_RB_BIN_FOVEAT());
}
tu_emit_cache_flush_ccu<CHIP>(cmd, cs, TU_CMD_CCU_GMEM);
if (use_hw_binning(cmd)) {