From 1c57f889082653071f944f51bc3a2f804807f9ee Mon Sep 17 00:00:00 2001 From: Danylo Piliaiev Date: Fri, 29 Aug 2025 15:54:02 +0200 Subject: [PATCH] tu: Reset BIN_FOVEAT regs for tiling with and without HW binning We didn't reset the regs when HW binning was disabled. Fixes: b34b089ca13 ("tu: Use GRAS bin offset registers") Signed-off-by: Danylo Piliaiev Part-of: --- src/freedreno/vulkan/tu_cmd_buffer.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index 3436f886d58..da1e0473f56 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -2099,12 +2099,6 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const struct tu_framebuffer *fb = cmd->state.framebuffer; const struct tu_tiling_config *tiling = cmd->state.tiling; - /* Reset bin scaling. */ - if (phys_dev->info->a7xx.has_hw_bin_scaling) { - tu_cs_emit_regs(cs, A7XX_GRAS_BIN_FOVEAT()); - tu_cs_emit_regs(cs, A7XX_RB_BIN_FOVEAT()); - } - /* If this command buffer may be executed multiple times, then * viewports/scissor states may have been changed by previous executions * and we need to reset them before executing the binning IB. With FDM @@ -2634,6 +2628,12 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs, tu7_emit_tile_render_begin_regs(cs); } + /* Reset bin scaling. */ + if (phys_dev->info->a7xx.has_hw_bin_scaling) { + tu_cs_emit_regs(cs, A7XX_GRAS_BIN_FOVEAT()); + tu_cs_emit_regs(cs, A7XX_RB_BIN_FOVEAT()); + } + tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_GMEM); if (use_hw_binning(cmd)) {