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intel/brw: Use brw prefix instead of namespace for analysis implementations

Browse source 
Also drop the 'fs' prefix when applicable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33048>
This commit is contained in:
Caio Oliveira 2024-12-06 21:20:58 -08:00 • committed by Marge Bot
parent 2b92eb0b2c
commit 1ade9a05d8
24 changed files with 326 additions and 334 deletions
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14
src/intel/compiler/brw_analysis.cpp
View file

@ -17,7 +17,7 @@ using namespace brw;
* (less than 1000 nodes) that this algorithm is significantly faster than
* others like Lengauer-Tarjan.
*/
idom_tree::idom_tree(const fs_visitor *s) :
brw_idom_tree::brw_idom_tree(const fs_visitor *s) :
num_parents(s->cfg->num_blocks),
parents(new bblock_t *[num_parents]())
{
@ -48,13 +48,13 @@ idom_tree::idom_tree(const fs_visitor *s) :
} while (changed);
}
idom_tree::~idom_tree()
brw_idom_tree::~brw_idom_tree()
{
delete[] parents;
}
bblock_t *
idom_tree::intersect(bblock_t *b1, bblock_t *b2) const
brw_idom_tree::intersect(bblock_t *b1, bblock_t *b2) const
{
/* Note, the comparisons here are the opposite of what the paper says
* because we index blocks from beginning -> end (i.e. reverse post-order)
@ -71,7 +71,7 @@ idom_tree::intersect(bblock_t *b1, bblock_t *b2) const
}
void
idom_tree::dump(FILE *file) const
brw_idom_tree::dump(FILE *file) const
{
fprintf(file, "digraph DominanceTree {\n");
for (unsigned i = 0; i < num_parents; i++)
@ -79,9 +79,9 @@ idom_tree::dump(FILE *file) const
fprintf(file, "}\n");
}
register_pressure::register_pressure(const fs_visitor *v)
brw_register_pressure::brw_register_pressure(const fs_visitor *v)
{
const fs_live_variables &live = v->live_analysis.require();
const brw_live_variables &live = v->live_analysis.require();
const unsigned num_instructions = v->cfg->num_blocks ?
v->cfg->blocks[v->cfg->num_blocks - 1]->end_ip + 1 : 0;
@ -105,7 +105,7 @@ register_pressure::register_pressure(const fs_visitor *v)
delete[] payload_last_use_ip;
}
register_pressure::~register_pressure()
brw_register_pressure::~brw_register_pressure()
{
delete[] regs_live_at_ip;
}

500
src/intel/compiler/brw_analysis.h
View file

@ -173,300 +173,298 @@ private:
T *p;
};
namespace brw {
/**
* Immediate dominator tree analysis of a shader.
*/
struct idom_tree {
idom_tree(const fs_visitor *s);
~idom_tree();
/**
* Immediate dominator tree analysis of a shader.
*/
struct brw_idom_tree {
brw_idom_tree(const fs_visitor *s);
~brw_idom_tree();
bool
validate(const fs_visitor *) const
{
/* FINISHME */
return true;
}
bool
validate(const fs_visitor *) const
{
/* FINISHME */
return true;
}
brw_analysis_dependency_class
dependency_class() const
{
return BRW_DEPENDENCY_BLOCKS;
}
brw_analysis_dependency_class
dependency_class() const
{
return BRW_DEPENDENCY_BLOCKS;
}
const bblock_t *
parent(const bblock_t *b) const
{
assert(unsigned(b->num) < num_parents);
return parents[b->num];
}
const bblock_t *
parent(const bblock_t *b) const
{
assert(unsigned(b->num) < num_parents);
return parents[b->num];
}
bblock_t *
parent(bblock_t *b) const
{
assert(unsigned(b->num) < num_parents);
return parents[b->num];
}
bblock_t *
parent(bblock_t *b) const
{
assert(unsigned(b->num) < num_parents);
return parents[b->num];
}
bblock_t *
intersect(bblock_t *b1, bblock_t *b2) const;
/**
* Returns true if block `a` dominates block `b`.
*/
bool
dominates(const bblock_t *a, const bblock_t *b) const
{
while (a != b) {
if (b->num == 0)
return false;
b = parent(b);
}
return true;
}
void dump(FILE *file = stderr) const;
private:
unsigned num_parents;
bblock_t **parents;
};
bblock_t *
intersect(bblock_t *b1, bblock_t *b2) const;
/**
* Register pressure analysis of a shader. Estimates how many registers
* are live at any point of the program in GRF units.
* Returns true if block `a` dominates block `b`.
*/
struct register_pressure {
register_pressure(const fs_visitor *v);
~register_pressure();
bool
dominates(const bblock_t *a, const bblock_t *b) const
{
while (a != b) {
if (b->num == 0)
return false;
brw_analysis_dependency_class
dependency_class() const
{
return (BRW_DEPENDENCY_INSTRUCTION_IDENTITY |
BRW_DEPENDENCY_INSTRUCTION_DATA_FLOW |
BRW_DEPENDENCY_VARIABLES);
b = parent(b);
}
return true;
}
bool
validate(const fs_visitor *) const
{
/* FINISHME */
return true;
}
void dump(FILE *file = stderr) const;
unsigned *regs_live_at_ip;
};
private:
unsigned num_parents;
bblock_t **parents;
};
class def_analysis {
public:
def_analysis(const fs_visitor *v);
~def_analysis();
/**
* Register pressure analysis of a shader. Estimates how many registers
* are live at any point of the program in GRF units.
*/
struct brw_register_pressure {
brw_register_pressure(const fs_visitor *v);
~brw_register_pressure();
brw_inst *
get(const brw_reg &reg) const
{
return reg.file == VGRF && reg.nr < def_count ?
def_insts[reg.nr] : NULL;
}
brw_analysis_dependency_class
dependency_class() const
{
return (BRW_DEPENDENCY_INSTRUCTION_IDENTITY |
BRW_DEPENDENCY_INSTRUCTION_DATA_FLOW |
BRW_DEPENDENCY_VARIABLES);
}
bblock_t *
get_block(const brw_reg &reg) const
{
return reg.file == VGRF && reg.nr < def_count ?
def_blocks[reg.nr] : NULL;
}
bool
validate(const fs_visitor *) const
{
/* FINISHME */
return true;
}
uint32_t
get_use_count(const brw_reg &reg) const
{
return reg.file == VGRF && reg.nr < def_count ?
def_use_counts[reg.nr] : 0;
}
unsigned *regs_live_at_ip;
};
unsigned count() const { return def_count; }
unsigned ssa_count() const;
class brw_def_analysis {
public:
brw_def_analysis(const fs_visitor *v);
~brw_def_analysis();
void print_stats(const fs_visitor *) const;
brw_inst *
get(const brw_reg &reg) const
{
return reg.file == VGRF && reg.nr < def_count ?
def_insts[reg.nr] : NULL;
}
brw_analysis_dependency_class
dependency_class() const
{
return BRW_DEPENDENCY_INSTRUCTION_IDENTITY |
BRW_DEPENDENCY_INSTRUCTION_DATA_FLOW |
BRW_DEPENDENCY_VARIABLES |
BRW_DEPENDENCY_BLOCKS;
}
bblock_t *
get_block(const brw_reg &reg) const
{
return reg.file == VGRF && reg.nr < def_count ?
def_blocks[reg.nr] : NULL;
}
bool validate(const fs_visitor *) const;
uint32_t
get_use_count(const brw_reg &reg) const
{
return reg.file == VGRF && reg.nr < def_count ?
def_use_counts[reg.nr] : 0;
}
private:
void mark_invalid(int);
bool fully_defines(const fs_visitor *v, brw_inst *);
void update_for_reads(const idom_tree &idom, bblock_t *block, brw_inst *);
void update_for_write(const fs_visitor *v, bblock_t *block, brw_inst *);
unsigned count() const { return def_count; }
unsigned ssa_count() const;
brw_inst **def_insts;
bblock_t **def_blocks;
uint32_t *def_use_counts;
unsigned def_count;
};
void print_stats(const fs_visitor *) const;
class fs_live_variables {
public:
struct block_data {
/**
* Which variables are defined before being used in the block.
*
* Note that for our purposes, "defined" means unconditionally, completely
* defined.
*/
BITSET_WORD *def;
brw_analysis_dependency_class
dependency_class() const
{
return BRW_DEPENDENCY_INSTRUCTION_IDENTITY |
BRW_DEPENDENCY_INSTRUCTION_DATA_FLOW |
BRW_DEPENDENCY_VARIABLES |
BRW_DEPENDENCY_BLOCKS;
}
/**
* Which variables are used before being defined in the block.
*/
BITSET_WORD *use;
bool validate(const fs_visitor *) const;
/** Which defs reach the entry point of the block. */
BITSET_WORD *livein;
private:
void mark_invalid(int);
bool fully_defines(const fs_visitor *v, brw_inst *);
void update_for_reads(const brw_idom_tree &idom, bblock_t *block, brw_inst *);
void update_for_write(const fs_visitor *v, bblock_t *block, brw_inst *);
/** Which defs reach the exit point of the block. */
BITSET_WORD *liveout;
/**
* Variables such that the entry point of the block may be reached from any
* of their definitions.
*/
BITSET_WORD *defin;
/**
* Variables such that the exit point of the block may be reached from any
* of their definitions.
*/
BITSET_WORD *defout;
BITSET_WORD flag_def[1];
BITSET_WORD flag_use[1];
BITSET_WORD flag_livein[1];
BITSET_WORD flag_liveout[1];
};
fs_live_variables(const fs_visitor *s);
~fs_live_variables();
bool validate(const fs_visitor *s) const;
brw_analysis_dependency_class
dependency_class() const
{
return (BRW_DEPENDENCY_INSTRUCTION_IDENTITY |
BRW_DEPENDENCY_INSTRUCTION_DATA_FLOW |
BRW_DEPENDENCY_VARIABLES);
}
bool vars_interfere(int a, int b) const;
bool vgrfs_interfere(int a, int b) const;
int var_from_reg(const brw_reg &reg) const
{
return var_from_vgrf[reg.nr] + reg.offset / REG_SIZE;
}
/** Map from virtual GRF number to index in block_data arrays. */
int *var_from_vgrf;
brw_inst **def_insts;
bblock_t **def_blocks;
uint32_t *def_use_counts;
unsigned def_count;
};
class brw_live_variables {
public:
struct block_data {
/**
* Map from any index in block_data to the virtual GRF containing it.
* Which variables are defined before being used in the block.
*
* For alloc.sizes of [1, 2, 3], vgrf_from_var would contain
* [0, 1, 1, 2, 2, 2].
* Note that for our purposes, "defined" means unconditionally, completely
* defined.
*/
int *vgrf_from_var;
BITSET_WORD *def;
int num_vars;
int num_vgrfs;
int bitset_words;
/** @{
* Final computed live ranges for each var (each component of each virtual
* GRF).
/**
* Which variables are used before being defined in the block.
*/
int *start;
int *end;
/** @} */
BITSET_WORD *use;
/** @{
* Final computed live ranges for each VGRF.
/** Which defs reach the entry point of the block. */
BITSET_WORD *livein;
/** Which defs reach the exit point of the block. */
BITSET_WORD *liveout;
/**
* Variables such that the entry point of the block may be reached from any
* of their definitions.
*/
int *vgrf_start;
int *vgrf_end;
/** @} */
BITSET_WORD *defin;
/** Per-basic-block information on live variables */
struct block_data *block_data;
/**
* Variables such that the exit point of the block may be reached from any
* of their definitions.
*/
BITSET_WORD *defout;
protected:
void setup_def_use();
void setup_one_read(struct block_data *bd, int ip, const brw_reg &reg);
void setup_one_write(struct block_data *bd, brw_inst *inst, int ip,
const brw_reg &reg);
void compute_live_variables();
void compute_start_end();
const struct intel_device_info *devinfo;
const cfg_t *cfg;
void *mem_ctx;
BITSET_WORD flag_def[1];
BITSET_WORD flag_use[1];
BITSET_WORD flag_livein[1];
BITSET_WORD flag_liveout[1];
};
brw_live_variables(const fs_visitor *s);
~brw_live_variables();
bool validate(const fs_visitor *s) const;
brw_analysis_dependency_class
dependency_class() const
{
return (BRW_DEPENDENCY_INSTRUCTION_IDENTITY |
BRW_DEPENDENCY_INSTRUCTION_DATA_FLOW |
BRW_DEPENDENCY_VARIABLES);
}
bool vars_interfere(int a, int b) const;
bool vgrfs_interfere(int a, int b) const;
int var_from_reg(const brw_reg &reg) const
{
return var_from_vgrf[reg.nr] + reg.offset / REG_SIZE;
}
/** Map from virtual GRF number to index in block_data arrays. */
int *var_from_vgrf;
/**
* Various estimates of the performance of a shader based on static
* analysis.
* Map from any index in block_data to the virtual GRF containing it.
*
* For alloc.sizes of [1, 2, 3], vgrf_from_var would contain
* [0, 1, 1, 2, 2, 2].
*/
struct performance {
performance(const fs_visitor *v);
~performance();
int *vgrf_from_var;
brw_analysis_dependency_class
dependency_class() const
{
return (BRW_DEPENDENCY_INSTRUCTIONS |
BRW_DEPENDENCY_BLOCKS);
}
int num_vars;
int num_vgrfs;
int bitset_words;
bool
validate(const fs_visitor *) const
{
return true;
}
/** @{
* Final computed live ranges for each var (each component of each virtual
* GRF).
*/
int *start;
int *end;
/** @} */
/**
* Array containing estimates of the runtime of each basic block of the
* program in cycle units.
*/
unsigned *block_latency;
/** @{
* Final computed live ranges for each VGRF.
*/
int *vgrf_start;
int *vgrf_end;
/** @} */
/**
* Estimate of the runtime of the whole program in cycle units assuming
* uncontended execution.
*/
unsigned latency;
/** Per-basic-block information on live variables */
struct block_data *block_data;
/**
* Estimate of the throughput of the whole program in
* invocations-per-cycle units.
*
* Note that this might be lower than the ratio between the dispatch
* width of the program and its latency estimate in cases where
* performance doesn't scale without limits as a function of its thread
* parallelism, e.g. due to the existence of a bottleneck in a shared
* function.
*/
float throughput;
protected:
void setup_def_use();
void setup_one_read(struct block_data *bd, int ip, const brw_reg &reg);
void setup_one_write(struct block_data *bd, brw_inst *inst, int ip,
const brw_reg &reg);
void compute_live_variables();
void compute_start_end();
private:
performance(const performance &perf);
performance &
operator=(performance u);
};
}
const struct intel_device_info *devinfo;
const cfg_t *cfg;
void *mem_ctx;
};
/**
* Various estimates of the performance of a shader based on static
* analysis.
*/
struct brw_performance {
brw_performance(const fs_visitor *v);
~brw_performance();
brw_analysis_dependency_class
dependency_class() const
{
return (BRW_DEPENDENCY_INSTRUCTIONS |
BRW_DEPENDENCY_BLOCKS);
}
bool
validate(const fs_visitor *) const
{
return true;
}
/**
* Array containing estimates of the runtime of each basic block of the
* program in cycle units.
*/
unsigned *block_latency;
/**
* Estimate of the runtime of the whole program in cycle units assuming
* uncontended execution.
*/
unsigned latency;
/**
* Estimate of the throughput of the whole program in
* invocations-per-cycle units.
*
* Note that this might be lower than the ratio between the dispatch
* width of the program and its latency estimate in cases where
* performance doesn't scale without limits as a function of its thread
* parallelism, e.g. due to the existence of a bottleneck in a shared
* function.
*/
float throughput;
private:
brw_performance(const brw_performance &perf);
brw_performance &
operator=(brw_performance u);
};

30
src/intel/compiler/brw_analysis_def.cpp
View file

@ -35,21 +35,19 @@
* Def analysis requires the dominator tree, but not liveness information.
*/
using namespace brw;
static brw_inst *const UNSEEN = (brw_inst *) (uintptr_t) 1;
void
def_analysis::mark_invalid(int nr)
brw_def_analysis::mark_invalid(int nr)
{
def_blocks[nr] = NULL;
def_insts[nr] = NULL;
}
void
def_analysis::update_for_reads(const idom_tree &idom,
bblock_t *block,
brw_inst *inst)
brw_def_analysis::update_for_reads(const brw_idom_tree &idom,
bblock_t *block,
brw_inst *inst)
{
/* We don't track accumulator use for def analysis, so if an instruction
* implicitly reads the accumulator, we don't consider it to produce a def.
@ -96,16 +94,16 @@ def_analysis::update_for_reads(const idom_tree &idom,
}
bool
def_analysis::fully_defines(const fs_visitor *v, brw_inst *inst)
brw_def_analysis::fully_defines(const fs_visitor *v, brw_inst *inst)
{
return v->alloc.sizes[inst->dst.nr] * REG_SIZE == inst->size_written &&
!inst->is_partial_write();
}
void
def_analysis::update_for_write(const fs_visitor *v,
bblock_t *block,
brw_inst *inst)
brw_def_analysis::update_for_write(const fs_visitor *v,
bblock_t *block,
brw_inst *inst)
{
const int nr = inst->dst.nr;
@ -126,9 +124,9 @@ def_analysis::update_for_write(const fs_visitor *v,
}
}
def_analysis::def_analysis(const fs_visitor *v)
brw_def_analysis::brw_def_analysis(const fs_visitor *v)
{
const idom_tree &idom = v->idom_analysis.require();
const brw_idom_tree &idom = v->idom_analysis.require();
def_count = v->alloc.count;
@ -176,7 +174,7 @@ def_analysis::def_analysis(const fs_visitor *v)
} while (iterate);
}
def_analysis::~def_analysis()
brw_def_analysis::~brw_def_analysis()
{
delete[] def_insts;
delete[] def_blocks;
@ -184,7 +182,7 @@ def_analysis::~def_analysis()
}
bool
def_analysis::validate(const fs_visitor *v) const
brw_def_analysis::validate(const fs_visitor *v) const
{
for (unsigned i = 0; i < def_count; i++) {
assert(!def_insts[i] == !def_blocks[i]);
@ -194,7 +192,7 @@ def_analysis::validate(const fs_visitor *v) const
}
unsigned
def_analysis::ssa_count() const
brw_def_analysis::ssa_count() const
{
unsigned defs = 0;
@ -207,7 +205,7 @@ def_analysis::ssa_count() const
}
void
def_analysis::print_stats(const fs_visitor *v) const
brw_def_analysis::print_stats(const fs_visitor *v) const
{
const unsigned defs = ssa_count();

28
src/intel/compiler/brw_analysis_liveness.cpp
View file

@ -28,8 +28,6 @@
#include "brw_fs.h"
#include "brw_analysis.h"
using namespace brw;
#define MAX_INSTRUCTION (1 << 30)
/** @file
@ -53,8 +51,8 @@ using namespace brw;
*/
void
fs_live_variables::setup_one_read(struct block_data *bd,
int ip, const brw_reg &reg)
brw_live_variables::setup_one_read(struct block_data *bd,
int ip, const brw_reg &reg)
{
int var = var_from_reg(reg);
assert(var < num_vars);
@ -71,8 +69,8 @@ fs_live_variables::setup_one_read(struct block_data *bd,
}
void
fs_live_variables::setup_one_write(struct block_data *bd, brw_inst *inst,
int ip, const brw_reg &reg)
brw_live_variables::setup_one_write(struct block_data *bd, brw_inst *inst,
int ip, const brw_reg &reg)
{
int var = var_from_reg(reg);
assert(var < num_vars);
@ -101,7 +99,7 @@ fs_live_variables::setup_one_write(struct block_data *bd, brw_inst *inst,
* These are tracked at the per-component level, rather than whole VGRFs.
*/
void
fs_live_variables::setup_def_use()
brw_live_variables::setup_def_use()
{
int ip = 0;
@ -152,7 +150,7 @@ fs_live_variables::setup_def_use()
* a pass.
*/
void
fs_live_variables::compute_live_variables()
brw_live_variables::compute_live_variables()
{
bool cont = true;
@ -228,7 +226,7 @@ fs_live_variables::compute_live_variables()
* new information calculated from control flow.
*/
void
fs_live_variables::compute_start_end()
brw_live_variables::compute_start_end()
{
foreach_block (block, cfg) {
struct block_data *bd = &block_data[block->num];
@ -246,7 +244,7 @@ fs_live_variables::compute_start_end()
}
}
fs_live_variables::fs_live_variables(const fs_visitor *s)
brw_live_variables::brw_live_variables(const fs_visitor *s)
: devinfo(s->devinfo), cfg(s->cfg)
{
mem_ctx = ralloc_context(NULL);
@ -310,13 +308,13 @@ fs_live_variables::fs_live_variables(const fs_visitor *s)
}
}
fs_live_variables::~fs_live_variables()
brw_live_variables::~brw_live_variables()
{
ralloc_free(mem_ctx);
}
static bool
check_register_live_range(const fs_live_variables *live, int ip,
check_register_live_range(const brw_live_variables *live, int ip,
const brw_reg &reg, unsigned n)
{
const unsigned var = live->var_from_reg(reg);
@ -334,7 +332,7 @@ check_register_live_range(const fs_live_variables *live, int ip,
}
bool
fs_live_variables::validate(const fs_visitor *s) const
brw_live_variables::validate(const fs_visitor *s) const
{
int ip = 0;
@ -357,14 +355,14 @@ fs_live_variables::validate(const fs_visitor *s) const
}
bool
fs_live_variables::vars_interfere(int a, int b) const
brw_live_variables::vars_interfere(int a, int b) const
{
return !(end[b] <= start[a] ||
end[a] <= start[b]);
}
bool
fs_live_variables::vgrfs_interfere(int a, int b) const
brw_live_variables::vgrfs_interfere(int a, int b) const
{
return !(vgrf_end[a] <= vgrf_start[b] ||
vgrf_end[b] <= vgrf_start[a]);

8
src/intel/compiler/brw_analysis_performance.cpp
View file

@ -25,8 +25,6 @@
#include "brw_fs.h"
#include "brw_cfg.h"
using namespace brw;
namespace {
/**
* Enumeration representing the various asynchronous units that can run
@ -998,7 +996,7 @@ namespace {
* Estimate the performance of the specified shader.
*/
void
calculate_performance(performance &p, const fs_visitor *s,
calculate_performance(brw_performance &p, const fs_visitor *s,
unsigned dispatch_width)
{
/* XXX - Note that the previous version of this code used worst-case
@ -1064,13 +1062,13 @@ namespace {
}
}
brw::performance::performance(const fs_visitor *v) :
brw_performance::brw_performance(const fs_visitor *v) :
block_latency(new unsigned[v->cfg->num_blocks])
{
calculate_performance(*this, v, v->dispatch_width);
}
brw::performance::~performance()
brw_performance::~brw_performance()
{
delete[] block_latency;
}

2
src/intel/compiler/brw_cfg.cpp
View file

@ -617,7 +617,7 @@ sort_links(util_dynarray *scratch, exec_list *list)
void
cfg_t::dump(FILE *file)
{
const idom_tree *idom = (s ? &s->idom_analysis.require() : NULL);
const brw_idom_tree *idom = (s ? &s->idom_analysis.require() : NULL);
/* Temporary storage to sort the lists of blocks. This normalizes the
* output, making it possible to use it for certain tests.

6
src/intel/compiler/brw_compile_fs.cpp
View file

@ -1609,7 +1609,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
prog_data->base.grf_used = MAX2(prog_data->base.grf_used,
v8->grf_used);
const performance &perf = v8->performance_analysis.require();
const brw_performance &perf = v8->performance_analysis.require();
throughput = MAX2(throughput, perf.throughput);
has_spilled = v8->spilled_any_registers;
allow_spilling = false;
@ -1765,7 +1765,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
prog_data->base.grf_used = MAX2(prog_data->base.grf_used,
v16->grf_used);
const performance &perf = v16->performance_analysis.require();
const brw_performance &perf = v16->performance_analysis.require();
throughput = MAX2(throughput, perf.throughput);
has_spilled = v16->spilled_any_registers;
allow_spilling = false;
@ -1795,7 +1795,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
"SIMD32 shader failed to compile: %s\n",
v32->fail_msg);
} else {
const performance &perf = v32->performance_analysis.require();
const brw_performance &perf = v32->performance_analysis.require();
if (!INTEL_DEBUG(DEBUG_DO32) && throughput >= perf.throughput) {
brw_shader_perf_log(compiler, params->base.log_data,

2
src/intel/compiler/brw_fs.cpp
View file

@ -557,7 +557,7 @@ fs_visitor::debug_optimizer(const nir_shader *nir,
static uint32_t
brw_compute_max_register_pressure(fs_visitor &s)
{
const register_pressure &rp = s.regpressure_analysis.require();
const brw_register_pressure &rp = s.regpressure_analysis.require();
uint32_t ip = 0, max_pressure = 0;
foreach_block_and_inst(block, brw_inst, inst, s.cfg) {
max_pressure = MAX2(max_pressure, rp.regs_live_at_ip[ip]);

12
src/intel/compiler/brw_fs.h
View file

@ -232,11 +232,11 @@ public:
struct brw_stage_prog_data *prog_data;
brw_analysis<brw::fs_live_variables, fs_visitor> live_analysis;
brw_analysis<brw::register_pressure, fs_visitor> regpressure_analysis;
brw_analysis<brw::performance, fs_visitor> performance_analysis;
brw_analysis<brw::idom_tree, fs_visitor> idom_analysis;
brw_analysis<brw::def_analysis, fs_visitor> def_analysis;
brw_analysis<brw_live_variables, fs_visitor> live_analysis;
brw_analysis<brw_register_pressure, fs_visitor> regpressure_analysis;
brw_analysis<brw_performance, fs_visitor> performance_analysis;
brw_analysis<brw_idom_tree, fs_visitor> idom_analysis;
brw_analysis<brw_def_analysis, fs_visitor> def_analysis;
/** Number of uniform variable components visited. */
unsigned uniforms;
@ -348,7 +348,7 @@ void brw_print_instructions(const fs_visitor &s, FILE *file = stderr);
void brw_print_instruction(const fs_visitor &s, const brw_inst *inst,
FILE *file = stderr,
const brw::def_analysis *defs = nullptr);
const brw_def_analysis *defs = nullptr);
void brw_print_swsb(FILE *f, const struct intel_device_info *devinfo, const tgl_swsb swsb);

2
src/intel/compiler/brw_generator.cpp
View file

@ -756,7 +756,7 @@ translate_systolic_depth(unsigned d)
int
brw_generator::generate_code(const cfg_t *cfg, int dispatch_width,
struct brw_shader_stats shader_stats,
const brw::performance &perf,
const brw_performance &perf,
struct brw_compile_stats *stats,
unsigned max_polygons)
{

2
src/intel/compiler/brw_generator.h
View file

@ -20,7 +20,7 @@ public:
void enable_debug(const char *shader_name);
int generate_code(const cfg_t *cfg, int dispatch_width,
struct brw_shader_stats shader_stats,
const brw::performance &perf,
const brw_performance &perf,
struct brw_compile_stats *stats,
unsigned max_polygons = 0);
void add_const_data(void *data, unsigned size);

2
src/intel/compiler/brw_opt.cpp
View file

@ -23,7 +23,7 @@ brw_optimize(fs_visitor &s)
/* Track how much non-SSA at this point. */
{
const brw::def_analysis &defs = s.def_analysis.require();
const brw_def_analysis &defs = s.def_analysis.require();
s.shader_stats.non_ssa_registers_after_nir =
defs.count() - defs.ssa_count();
}

4
src/intel/compiler/brw_opt_address_reg_load.cpp
View file

@ -23,7 +23,7 @@
using namespace brw;
static bool
opt_address_reg_load_local(fs_visitor &s, bblock_t *block, const brw::def_analysis &defs)
opt_address_reg_load_local(fs_visitor &s, bblock_t *block, const brw_def_analysis &defs)
{
bool progress = false;
@ -58,7 +58,7 @@ bool
brw_opt_address_reg_load(fs_visitor &s)
{
bool progress = false;
const brw::def_analysis &defs = s.def_analysis.require();
const brw_def_analysis &defs = s.def_analysis.require();
foreach_block(block, s.cfg) {
foreach_inst_in_block_safe(brw_inst, inst, block) {

2
src/intel/compiler/brw_opt_combine_constants.cpp
View file

@ -1310,7 +1310,7 @@ brw_opt_combine_constants(fs_visitor &s)
table.num_boxes = 0;
table.boxes = ralloc_array(const_ctx, brw_inst_box, table.size_boxes);
const brw::idom_tree &idom = s.idom_analysis.require();
const brw_idom_tree &idom = s.idom_analysis.require();
unsigned ip = -1;
/* Make a pass through all instructions and mark each constant is used in

10
src/intel/compiler/brw_opt_copy_propagation.cpp
View file

@ -268,7 +268,7 @@ class fs_copy_prop_dataflow
{
public:
fs_copy_prop_dataflow(linear_ctx *lin_ctx, cfg_t *cfg,
const fs_live_variables &live,
const brw_live_variables &live,
struct acp *out_acp);
void setup_initial_values();
@ -277,7 +277,7 @@ public:
void dump_block_data() const UNUSED;
cfg_t *cfg;
const fs_live_variables &live;
const brw_live_variables &live;
acp_entry **acp;
int num_acp;
@ -288,7 +288,7 @@ public:
} /* anonymous namespace */
fs_copy_prop_dataflow::fs_copy_prop_dataflow(linear_ctx *lin_ctx, cfg_t *cfg,
const fs_live_variables &live,
const brw_live_variables &live,
struct acp *out_acp)
: cfg(cfg), live(live)
{
@ -1424,7 +1424,7 @@ brw_opt_copy_propagation(fs_visitor &s)
linear_ctx *lin_ctx = linear_context(copy_prop_ctx);
struct acp *out_acp = new (lin_ctx) acp[s.cfg->num_blocks];
const fs_live_variables &live = s.live_analysis.require();
const brw_live_variables &live = s.live_analysis.require();
/* First, walk through each block doing local copy propagation and getting
* the set of copies available at the end of the block.
@ -1812,7 +1812,7 @@ find_value_for_offset(brw_inst *def, const brw_reg &src, unsigned src_size)
bool
brw_opt_copy_propagation_defs(fs_visitor &s)
{
const brw::def_analysis &defs = s.def_analysis.require();
const brw_def_analysis &defs = s.def_analysis.require();
unsigned *uses_deleted = new unsigned[defs.count()]();
bool progress = false;

6
src/intel/compiler/brw_opt_cse.cpp
View file

@ -363,7 +363,7 @@ cmp_func(const void *data1, const void *data2)
}
static bool
remap_sources(fs_visitor &s, const brw::def_analysis &defs,
remap_sources(fs_visitor &s, const brw_def_analysis &defs,
brw_inst *inst, struct remap_entry *remap_table)
{
bool progress = false;
@ -399,8 +399,8 @@ bool
brw_opt_cse_defs(fs_visitor &s)
{
const intel_device_info *devinfo = s.devinfo;
const idom_tree &idom = s.idom_analysis.require();
const brw::def_analysis &defs = s.def_analysis.require();
const brw_idom_tree &idom = s.idom_analysis.require();
const brw_def_analysis &defs = s.def_analysis.require();
bool progress = false;
bool need_remaps = false;

2
src/intel/compiler/brw_opt_dead_code_eliminate.cpp
View file

@ -103,7 +103,7 @@ brw_opt_dead_code_eliminate(fs_visitor &s)
bool progress = false;
const fs_live_variables &live_vars = s.live_analysis.require();
const brw_live_variables &live_vars = s.live_analysis.require();
int num_vars = live_vars.num_vars;
BITSET_WORD *live = rzalloc_array(NULL, BITSET_WORD, BITSET_WORDS(num_vars));
BITSET_WORD *flag_live = rzalloc_array(NULL, BITSET_WORD, 1);

4
src/intel/compiler/brw_opt_register_coalesce.cpp
View file

@ -98,7 +98,7 @@ is_coalesce_candidate(const fs_visitor *v, const brw_inst *inst)
static bool
can_coalesce_vars(const intel_device_info *devinfo,
const fs_live_variables &live, const cfg_t *cfg,
const brw_live_variables &live, const cfg_t *cfg,
const bblock_t *block, const brw_inst *inst,
int dst_var, int src_var)
{
@ -231,7 +231,7 @@ brw_opt_register_coalesce(fs_visitor &s)
const intel_device_info *devinfo = s.devinfo;
bool progress = false;
fs_live_variables &live = s.live_analysis.require();
brw_live_variables &live = s.live_analysis.require();
int src_size = 0;
int channels_remaining = 0;
unsigned src_reg = ~0u, dst_reg = ~0u;

4
src/intel/compiler/brw_opt_saturate_propagation.cpp
View file

@ -104,7 +104,7 @@ opt_saturate_propagation_local(fs_visitor &s, bblock_t *block)
inst->src[0].abs)
continue;
const brw::def_analysis &defs = s.def_analysis.require();
const brw_def_analysis &defs = s.def_analysis.require();
brw_inst *def = defs.get(inst->src[0]);
if (def != NULL) {
@ -135,7 +135,7 @@ opt_saturate_propagation_local(fs_visitor &s, bblock_t *block)
continue;
}
const fs_live_variables &live = s.live_analysis.require();
const brw_live_variables &live = s.live_analysis.require();
int src_var = live.var_from_reg(inst->src[0]);
int src_end_ip = live.end[src_var];

8
src/intel/compiler/brw_opt_txf_combiner.cpp
View file

@ -25,13 +25,13 @@ dest_comps_for_txf(const fs_visitor &s, const brw_inst *txf)
}
static bool
is_def(const def_analysis &defs, const brw_reg &r)
is_def(const brw_def_analysis &defs, const brw_reg &r)
{
return r.file == IMM || r.file == BAD_FILE || defs.get(r) != NULL;
}
static bool
is_uniform_def(const def_analysis &defs, const brw_reg &r)
is_uniform_def(const brw_def_analysis &defs, const brw_reg &r)
{
return is_def(defs, r) && is_uniform(r);
}
@ -42,7 +42,7 @@ is_uniform_def(const def_analysis &defs, const brw_reg &r)
* with matching source modifiers and regions).
*/
static bool
sources_match(ASSERTED const def_analysis &defs,
sources_match(ASSERTED const brw_def_analysis &defs,
const brw_inst *a, const brw_inst *b, enum tex_logical_srcs src)
{
assert(is_def(defs, a->src[src]));
@ -82,7 +82,7 @@ sources_match(ASSERTED const def_analysis &defs,
bool
brw_opt_combine_convergent_txf(fs_visitor &s)
{
const def_analysis &defs = s.def_analysis.require();
const brw_def_analysis &defs = s.def_analysis.require();
const unsigned min_simd = 8 * reg_unit(s.devinfo);
const unsigned max_simd = 16 * reg_unit(s.devinfo);

6
src/intel/compiler/brw_print.cpp
View file

@ -16,8 +16,8 @@ void
brw_print_instructions(const fs_visitor &s, FILE *file)
{
if (s.cfg && s.grf_used == 0) {
const brw::def_analysis &defs = s.def_analysis.require();
const register_pressure *rp =
const brw_def_analysis &defs = s.def_analysis.require();
const brw_register_pressure *rp =
INTEL_DEBUG(DEBUG_REG_PRESSURE) ? &s.regpressure_analysis.require() : NULL;
unsigned ip = 0, max_pressure = 0;
@ -374,7 +374,7 @@ print_memory_logical_source(FILE *file, const brw_inst *inst, unsigned i)
}
void
brw_print_instruction(const fs_visitor &s, const brw_inst *inst, FILE *file, const brw::def_analysis *defs)
brw_print_instruction(const fs_visitor &s, const brw_inst *inst, FILE *file, const brw_def_analysis *defs)
{
if (inst->predicate) {
fprintf(file, "(%cf%d.%d) ",

2
src/intel/compiler/brw_reg_allocate.cpp
View file

@ -313,7 +313,7 @@ private:
fs_visitor *fs;
const intel_device_info *devinfo;
const brw_compiler *compiler;
const fs_live_variables &live;
const brw_live_variables &live;
int live_instr_count;
set *spill_insts;

2
src/intel/compiler/brw_schedule_instructions.cpp
View file

@ -822,7 +822,7 @@ brw_instruction_scheduler::count_reads_remaining(const brw_inst *inst)
void
brw_instruction_scheduler::setup_liveness(cfg_t *cfg)
{
const fs_live_variables &live = s->live_analysis.require();
const brw_live_variables &live = s->live_analysis.require();
/* First, compute liveness on a per-GRF level using the in/out sets from
* liveness calculation.

2
src/intel/compiler/brw_workaround.cpp
View file

@ -169,7 +169,7 @@ brw_workaround_nomask_control_flow(fs_visitor &s)
unsigned depth = 0;
bool progress = false;
const fs_live_variables &live_vars = s.live_analysis.require();
const brw_live_variables &live_vars = s.live_analysis.require();
/* Scan the program backwards in order to be able to easily determine
* whether the flag register is live at any point.