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radv: remove radv_compiler_info::cache_key

Browse source 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41022>
This commit is contained in:
Rhys Perry 2026-04-23 16:33:08 +01:00 • committed by Marge Bot
parent c6c4f523af
commit 1ac306c11e
11 changed files with 42 additions and 45 deletions
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5
src/amd/vulkan/nir/radv_nir_lower_descriptors.c
View file

@ -685,10 +685,9 @@ radv_nir_lower_descriptors(nir_shader *shader, const struct radv_compiler_info *
.combined_image_sampler_desc_size = compiler_info->combined_image_sampler_desc_size,
.combined_image_sampler_offset = compiler_info->combined_image_sampler_offset,
.disable_aniso_single_level =
compiler_info->cache_key->disable_aniso_single_level && compiler_info->ac->gfx_level < GFX8,
compiler_info->key.disable_aniso_single_level && compiler_info->ac->gfx_level < GFX8,
.has_image_load_dcc_bug = compiler_info->ac->has_image_load_dcc_bug,
.disable_tg4_trunc_coord =
!compiler_info->ac->conformant_trunc_coord && !compiler_info->cache_key->disable_trunc_coord,
.disable_tg4_trunc_coord = !compiler_info->ac->conformant_trunc_coord && !compiler_info->key.disable_trunc_coord,
.args = &stage->args,
.info = &stage->info,
.layout = &stage->layout,

2
src/amd/vulkan/nir/radv_nir_lower_immediate_samplers.c
View file

@ -30,7 +30,7 @@ lower_immediate_samplers(nir_builder *b, nir_tex_instr *tex, void *cb_data)
b->cursor = nir_before_instr(&tex->instr);
const bool disable_tg4_trunc_coord =
!state->compiler_info->ac->conformant_trunc_coord && !state->compiler_info->cache_key->disable_trunc_coord;
!state->compiler_info->ac->conformant_trunc_coord && !state->compiler_info->key.disable_trunc_coord;
const uint32_t dword0_mask =
tex->op == nir_texop_tg4 && disable_tg4_trunc_coord ? C_008F30_TRUNC_COORD : 0xffffffffu;

4
src/amd/vulkan/nir/radv_nir_lower_ray_queries.c
View file

@ -339,7 +339,7 @@ lower_rq_initialize(nir_builder *b, nir_intrinsic_instr *instr, struct ray_query
rq_store(b, rq, trav_top_stack, nir_imm_int(b, -1));
rq_store(b, rq, incomplete, nir_iand_imm(b, accel_struct_non_null, !compiler_info->cache_key->no_rt));
rq_store(b, rq, incomplete, nir_iand_imm(b, accel_struct_non_null, !compiler_info->key.no_rt));
vars->initialize = instr;
}
@ -586,7 +586,7 @@ lower_rq_proceed(nir_builder *b, nir_intrinsic_instr *instr, struct ray_query_va
nir_push_if(b, rq_load(b, rq, incomplete));
{
nir_def *incomplete;
if (compiler_info->cache_key->bvh8)
if (compiler_info->key.bvh8)
incomplete = radv_build_ray_traversal_gfx12(compiler_info, b, &args);
else
incomplete = radv_build_ray_traversal(compiler_info, b, &args);

35
src/amd/vulkan/nir/radv_nir_rt_common.c
View file

@ -18,8 +18,8 @@ radv_use_bvh_stack_rtn(const struct radv_compiler_info *compiler_info)
{
/* gfx12 requires using the bvh4 ds_bvh_stack_rtn differently - enable hw stack instrs on gfx12 only with bvh8 */
return ((compiler_info->ac->gfx_level >= GFX11 && compiler_info->ac->gfx_level < GFX12) ||
compiler_info->cache_key->bvh8) &&
!compiler_info->cache_key->emulate_rt;
compiler_info->key.bvh8) &&
!compiler_info->key.emulate_rt;
}
nir_def *
@ -388,7 +388,7 @@ build_addr_to_node(const struct radv_compiler_info *compiler_info, nir_builder *
nir_def *node = nir_ushr_imm(b, addr, 3);
node = nir_iand_imm(b, node, (bvh_size - 1) << 3);
if (compiler_info->cache_key->bvh8) {
if (compiler_info->key.bvh8) {
/* The HW ray flags are the same bits as the API flags.
* - SpvRayFlagsTerminateOnFirstHitKHRMask, SpvRayFlagsSkipClosestHitShaderKHRMask are handled in shader code.
* - SpvRayFlagsSkipTrianglesKHRMask, SpvRayFlagsSkipAABBsKHRMask do not work.
@ -433,7 +433,7 @@ nir_build_vec3_mat_mult(nir_builder *b, nir_def *vec, nir_def *matrix[], bool tr
nir_def *
radv_load_vertex_position(const struct radv_compiler_info *compiler_info, nir_builder *b, nir_def *primitive_addr, uint32_t index)
{
if (compiler_info->cache_key->bvh8) {
if (compiler_info->key.bvh8) {
/* Assume that vertices are uncompressed. */
uint32_t offset = ROUND_DOWN_TO(RADV_GFX12_PRIMITIVE_NODE_HEADER_SIZE / 8, 4) + index * 3 * sizeof(float);
nir_def *data[4];
@ -462,7 +462,7 @@ void
radv_load_wto_matrix(const struct radv_compiler_info *compiler_info, nir_builder *b, nir_def *instance_addr, nir_def **out)
{
unsigned offset = offsetof(struct radv_bvh_instance_node, wto_matrix);
if (compiler_info->cache_key->bvh8)
if (compiler_info->key.bvh8)
offset = offsetof(struct radv_gfx12_instance_node, wto_matrix);
for (unsigned i = 0; i < 3; ++i) {
@ -475,7 +475,7 @@ void
radv_load_otw_matrix(const struct radv_compiler_info *compiler_info, nir_builder *b, nir_def *instance_addr, nir_def **out)
{
unsigned offset = offsetof(struct radv_bvh_instance_node, otw_matrix);
if (compiler_info->cache_key->bvh8)
if (compiler_info->key.bvh8)
offset =
sizeof(struct radv_gfx12_instance_node) + offsetof(struct radv_gfx12_instance_node_user_data, otw_matrix);
@ -488,7 +488,7 @@ radv_load_otw_matrix(const struct radv_compiler_info *compiler_info, nir_builder
nir_def *
radv_load_custom_instance(const struct radv_compiler_info *compiler_info, nir_builder *b, nir_def *instance_addr)
{
if (compiler_info->cache_key->bvh8) {
if (compiler_info->key.bvh8) {
return nir_load_global(b, 1, 32,
nir_iadd_imm(b, instance_addr,
sizeof(struct radv_gfx12_instance_node) +
@ -505,7 +505,7 @@ radv_load_custom_instance(const struct radv_compiler_info *compiler_info, nir_bu
nir_def *
radv_load_instance_id(const struct radv_compiler_info *compiler_info, nir_builder *b, nir_def *instance_addr)
{
if (compiler_info->cache_key->bvh8) {
if (compiler_info->key.bvh8) {
return nir_load_global(b, 1, 32,
nir_iadd_imm(b, instance_addr,
sizeof(struct radv_gfx12_instance_node) +
@ -537,7 +537,7 @@ create_bvh_descriptor(nir_builder *b, const struct radv_compiler_info *compiler_
* instances at the cost of having to use 64-bit node ids. */
const uint64_t bvh_size = 1ull << 42;
const uint32_t sort_triangles_first = compiler_info->cache_key->bvh8 ? BITFIELD_BIT(52 - 32) : 0;
const uint32_t sort_triangles_first = compiler_info->key.bvh8 ? BITFIELD_BIT(52 - 32) : 0;
const uint32_t box_sort_enable = BITFIELD_BIT(63 - 32);
const uint32_t triangle_return_mode = BITFIELD_BIT(120 - 96); /* Return IJ for triangles */
@ -560,7 +560,7 @@ create_bvh_descriptor(nir_builder *b, const struct radv_compiler_info *compiler_
nir_imm_int(b, (box_sort_largest << 21) | sort_triangles_first | box_sort_enable), dword1);
}
if (compiler_info->cache_key->bvh8) {
if (compiler_info->key.bvh8) {
/* compressed_format_en */
dword3 |= BITFIELD_BIT(115 - 96);
/* wide_sort_en */
@ -591,7 +591,7 @@ insert_traversal_triangle_case(const struct radv_compiler_info *compiler_info, n
{
intersection.frontface = nir_fgt_imm(b, div, 0);
nir_def *not_cull;
if (compiler_info->ac->gfx_level < GFX11 || compiler_info->cache_key->emulate_rt) {
if (compiler_info->ac->gfx_level < GFX11 || compiler_info->key.emulate_rt) {
nir_def *switch_ccw =
nir_test_mask(b, nir_load_deref(b, args->vars.sbt_offset_and_flags), RADV_INSTANCE_TRIANGLE_FLIP_FACING);
intersection.frontface = nir_ixor(b, intersection.frontface, switch_ccw);
@ -749,7 +749,7 @@ insert_traversal_aabb_case_gfx12(const struct radv_compiler_info *compiler_info,
static nir_def *
fetch_parent_node(const struct radv_compiler_info *compiler_info, nir_builder *b, nir_def *bvh, nir_def *node)
{
nir_def *offset = nir_iadd_imm(b, nir_imul_imm(b, nir_udiv_imm(b, node, compiler_info->cache_key->bvh8 ? 16 : 8), 4), 4);
nir_def *offset = nir_iadd_imm(b, nir_imul_imm(b, nir_udiv_imm(b, node, compiler_info->key.bvh8 ? 16 : 8), 4), 4);
return nir_load_global(b, 1, 32, nir_isub(b, bvh, nir_u2u64(b, offset)), .align_mul = 4);
}
@ -771,7 +771,7 @@ static nir_def *
build_bvh_base(nir_builder *b, const struct radv_compiler_info *compiler_info, nir_def *base_addr, nir_def *ptr_flags,
bool overwrite)
{
if (compiler_info->ac->gfx_level < GFX11 || compiler_info->cache_key->emulate_rt)
if (compiler_info->ac->gfx_level < GFX11 || compiler_info->key.emulate_rt)
return base_addr;
nir_def *base_addr_vec = nir_unpack_64_2x32(b, base_addr);
@ -793,7 +793,7 @@ build_instance_exit(nir_builder *b, const struct radv_compiler_info *compiler_in
nir_if *instance_exit = nir_push_if(b, nir_ior(b, stack_instance_exit, root_instance_exit));
instance_exit->control = nir_selection_control_dont_flatten;
{
if (compiler_info->cache_key->bvh8 && args->use_bvh_stack_rtn)
if (compiler_info->key.bvh8 && args->use_bvh_stack_rtn)
nir_store_deref(b, args->vars.stack,
nir_ior_imm(b, nir_load_deref(b, args->vars.stack), RADV_BVH_STACK_FLAG_TLAS_POP), 0x1);
else
@ -801,8 +801,9 @@ build_instance_exit(nir_builder *b, const struct radv_compiler_info *compiler_in
nir_store_deref(b, args->vars.previous_node, nir_load_deref(b, args->vars.instance_top_node), 1);
nir_store_deref(b, args->vars.instance_bottom_node, nir_imm_int(b, RADV_BVH_NO_INSTANCE_ROOT), 1);
nir_def *root_bvh_base =
compiler_info->cache_key->bvh8 ? args->root_bvh_base : build_bvh_base(b, compiler_info, args->root_bvh_base, ptr_flags, true);
nir_def *root_bvh_base = compiler_info->key.bvh8
? args->root_bvh_base
: build_bvh_base(b, compiler_info, args->root_bvh_base, ptr_flags, true);
nir_store_deref(b, args->vars.bvh_base, root_bvh_base, 0x1);
nir_store_deref(b, args->vars.origin, args->origin, 7);
@ -932,7 +933,7 @@ radv_build_ray_traversal(const struct radv_compiler_info *compiler_info, nir_bui
nir_def *global_bvh_node = nir_iadd(b, nir_load_deref(b, args->vars.bvh_base), nir_u2u64(b, bvh_node));
bool has_result = false;
if (compiler_info->ac->has_image_bvh_intersect_ray && !compiler_info->cache_key->emulate_rt) {
if (compiler_info->ac->has_image_bvh_intersect_ray && !compiler_info->key.emulate_rt) {
nir_store_var(
b, intrinsic_result,
nir_bvh64_intersect_ray_amd(b, 32, desc, nir_unpack_64_2x32(b, global_bvh_node),

2
src/amd/vulkan/nir/radv_nir_rt_traversal_shader.c
View file

@ -1282,7 +1282,7 @@ radv_build_traversal(const struct radv_compiler_info *compiler_info, struct radv
.data = &data,
};
if (compiler_info->cache_key->bvh8)
if (compiler_info->key.bvh8)
radv_build_ray_traversal_gfx12(compiler_info, b, &args);
else
radv_build_ray_traversal(compiler_info, b, &args);

1
src/amd/vulkan/radv_device.c
View file

@ -1223,7 +1223,6 @@ radv_device_init_compiler_info(struct radv_device *device)
.cache_disabled = radv_device_is_cache_disabled(device),
.enable_nir_cache = !!(instance->debug_flags & RADV_PERFTEST_NIR_CACHE),
.mem_cache = device->mem_cache,
.cache_key = pdev_key,
.override_graphics_shader_version = instance->drirc.misc.override_graphics_shader_version,
.override_ray_tracing_shader_version = instance->drirc.misc.override_ray_tracing_shader_version,
.override_compute_shader_version = instance->drirc.misc.override_compute_shader_version,

10
src/amd/vulkan/radv_pipeline.c
View file

@ -299,7 +299,7 @@ radv_postprocess_nir(const struct radv_compiler_info *compiler_info, const struc
NIR_PASS(progress, stage->nir, nir_opt_load_store_vectorize, &vectorize_opts);
if (progress) {
NIR_PASS(_, stage->nir, nir_opt_copy_prop);
NIR_PASS(_, stage->nir, nir_opt_shrink_stores, !compiler_info->cache_key->disable_shrink_image_store);
NIR_PASS(_, stage->nir, nir_opt_shrink_stores, !compiler_info->key.disable_shrink_image_store);
constant_fold_for_push_const = true;
}
@ -338,7 +338,7 @@ radv_postprocess_nir(const struct radv_compiler_info *compiler_info, const struc
&(ac_nir_lower_image_tex_options){
.gfx_level = gfx_level,
.lower_array_layer_round_even =
!compiler_info->ac->conformant_trunc_coord && !compiler_info->cache_key->disable_trunc_coord,
!compiler_info->ac->conformant_trunc_coord && !compiler_info->key.disable_trunc_coord,
.fix_derivs_in_divergent_cf = stage->stage == MESA_SHADER_FRAGMENT && !use_llvm,
.max_wqm_vgprs = 64, // TODO: improve spiller and RA support for linear VGPRs
});
@ -376,7 +376,7 @@ radv_postprocess_nir(const struct radv_compiler_info *compiler_info, const struc
NIR_PASS(_, stage->nir, nir_opt_sink, sink_opts);
NIR_PASS(_, stage->nir, nir_opt_move, sink_opts);
} else {
if (stage->stage != MESA_SHADER_FRAGMENT || !compiler_info->cache_key->disable_sinking_load_input_fs)
if (stage->stage != MESA_SHADER_FRAGMENT || !compiler_info->key.disable_sinking_load_input_fs)
sink_opts |= nir_move_load_input | nir_move_load_frag_coord;
NIR_PASS(_, stage->nir, nir_opt_sink, sink_opts);
@ -526,7 +526,7 @@ radv_postprocess_nir(const struct radv_compiler_info *compiler_info, const struc
NIR_PASS(_, stage->nir, ac_nir_lower_global_access);
NIR_PASS(_, stage->nir, nir_lower_int64);
if (compiler_info->cache_key->mitigate_smem_oob)
if (compiler_info->key.mitigate_smem_oob)
NIR_PASS(_, stage->nir, ac_nir_fixup_mem_access_gfx6, &stage->args.ac, 4096, true, true);
bool opt_intrinsics = false;
@ -624,7 +624,7 @@ radv_shader_should_clear_lds(const struct radv_compiler_info *compiler_info, con
{
return (shader->info.stage == MESA_SHADER_COMPUTE || shader->info.stage == MESA_SHADER_MESH ||
shader->info.stage == MESA_SHADER_TASK) &&
shader->info.shared_size > 0 && compiler_info->cache_key->clear_lds;
shader->info.shared_size > 0 && compiler_info->key.clear_lds;
}
static uint32_t

6
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -1522,7 +1522,7 @@ radv_generate_ps_epilog_key(const struct radv_compiler_info *compiler_info, cons
key.spi_shader_col_format = col_format;
key.color_is_int8 = compiler_info->ac->has_cb_lt16bit_int_clamp_bug ? is_int8 : 0;
key.color_is_int10 = compiler_info->ac->has_cb_lt16bit_int_clamp_bug ? is_int10 : 0;
key.enable_mrt_output_nan_fixup = compiler_info->cache_key->enable_mrt_output_nan_fixup ? is_float32 : 0;
key.enable_mrt_output_nan_fixup = compiler_info->key.enable_mrt_output_nan_fixup ? is_float32 : 0;
key.no_signed_zero = no_signed_zero;
key.colors_written = state->colors_written;
key.mrt0_is_dual_src = state->mrt0_is_dual_src && key.colors_needed & 0xf;
@ -1816,7 +1816,7 @@ static void
radv_fill_shader_info_ngg(const struct radv_compiler_info *compiler_info, struct radv_shader_stage *stages,
VkShaderStageFlagBits active_nir_stages)
{
if (!compiler_info->cache_key->use_ngg)
if (!compiler_info->key.use_ngg)
return;
if (stages[MESA_SHADER_VERTEX].nir && stages[MESA_SHADER_VERTEX].info.next_stage != MESA_SHADER_TESS_CTRL) {
@ -1852,7 +1852,7 @@ radv_fill_shader_info_ngg(const struct radv_compiler_info *compiler_info, struct
}
if ((last_vgt_stage && last_vgt_stage->nir->xfb_info) ||
(compiler_info->cache_key->no_ngg_gs && stages[MESA_SHADER_GEOMETRY].nir)) {
(compiler_info->key.no_ngg_gs && stages[MESA_SHADER_GEOMETRY].nir)) {
/* NGG needs to be disabled on GFX10/GFX10.3 when:
* - streamout is used because NGG streamout isn't supported
* - NGG GS is explictly disabled to workaround performance issues

4
src/amd/vulkan/radv_sampler.c
View file

@ -209,7 +209,7 @@ radv_make_sampler_descriptor(const struct radv_compiler_info *compiler_info,
const bool trunc_coord =
((sampler_state->min_filter == VK_FILTER_NEAREST && sampler_state->mag_filter == VK_FILTER_NEAREST) ||
compiler_info->ac->conformant_trunc_coord) &&
!compiler_info->cache_key->disable_trunc_coord;
!compiler_info->key.disable_trunc_coord;
const VkBorderColor border_color = radv_get_border_color(sampler_state);
const bool disable_cube_wrap = sampler_state->flags & VK_SAMPLER_CREATE_NON_SEAMLESS_CUBE_MAP_BIT_EXT;
@ -236,7 +236,7 @@ radv_make_sampler_descriptor(const struct radv_compiler_info *compiler_info,
.min_lod = sampler_state->min_lod,
.max_lod = sampler_state->max_lod,
.lod_bias = sampler_state->mip_lod_bias,
.aniso_single_level = !compiler_info->cache_key->disable_aniso_single_level,
.aniso_single_level = !compiler_info->key.disable_aniso_single_level,
.border_color_type = radv_tex_bordercolor(border_color),
.border_color_ptr = border_color_ptr,
};

17
src/amd/vulkan/radv_shader.c
View file

@ -56,8 +56,7 @@ static void
get_nir_options_for_stage(struct radv_compiler_info *compiler_info, mesa_shader_stage stage)
{
nir_shader_compiler_options *options = &compiler_info->nir_options[stage];
const bool split_fma =
(stage <= MESA_SHADER_GEOMETRY || stage == MESA_SHADER_MESH) && compiler_info->cache_key->split_fma;
const bool split_fma = (stage <= MESA_SHADER_GEOMETRY || stage == MESA_SHADER_MESH) && compiler_info->key.split_fma;
ac_nir_set_options(compiler_info->ac, compiler_info->key.use_llvm, options);
@ -361,7 +360,7 @@ radv_shader_choose_subgroup_size(const struct radv_compiler_info *compiler_info,
};
/* Do not allow for the SPIR-V 1.6 varying subgroup size rules. */
if (compiler_info->cache_key->no_implicit_varying_subgroup_size)
if (compiler_info->key.no_implicit_varying_subgroup_size)
spirv_version = 0x10000;
vk_set_subgroup_size(nir, compiler_info->subgroup_size, compiler_info->min_subgroup_size,
@ -508,9 +507,9 @@ radv_shader_spirv_to_nir(const struct radv_compiler_info *compiler_info, struct
},
.workarounds =
{
.force_tex_non_uniform = compiler_info->cache_key->tex_non_uniform,
.force_ssbo_non_uniform = compiler_info->cache_key->ssbo_non_uniform,
.lower_terminate_to_discard = compiler_info->cache_key->lower_terminate_to_discard,
.force_tex_non_uniform = compiler_info->key.tex_non_uniform,
.force_ssbo_non_uniform = compiler_info->key.ssbo_non_uniform,
.lower_terminate_to_discard = compiler_info->key.lower_terminate_to_discard,
},
.emit_debug_break = compiler_info->debug.trap_enabled,
.debug_info = compiler_info->debug.nir_debug_info,
@ -613,7 +612,7 @@ radv_shader_spirv_to_nir(const struct radv_compiler_info *compiler_info, struct
NIR_PASS(_, nir, nir_lower_vars_to_ssa);
NIR_PASS(_, nir, nir_propagate_invariant, compiler_info->cache_key->invariant_geom);
NIR_PASS(_, nir, nir_propagate_invariant, compiler_info->key.invariant_geom);
nir_gather_clip_cull_distance_sizes_from_vars(nir);
NIR_PASS(_, nir, nir_merge_clip_cull_distance_vars);
@ -750,7 +749,7 @@ radv_shader_spirv_to_nir(const struct radv_compiler_info *compiler_info, struct
});
NIR_PASS(_, nir, nir_lower_load_const_to_scalar);
NIR_PASS(_, nir, nir_opt_shrink_stores, !compiler_info->cache_key->disable_shrink_image_store);
NIR_PASS(_, nir, nir_opt_shrink_stores, !compiler_info->key.disable_shrink_image_store);
if (nir->info.stage == MESA_SHADER_FRAGMENT && nir->info.fs.uses_discard)
NIR_PASS(_, nir, nir_lower_discard_if, nir_move_terminate_out_of_loops);
@ -891,7 +890,7 @@ radv_consider_culling(const struct radv_compiler_info *compiler_info, struct nir
if (info->vs.has_prolog)
return false;
if (!compiler_info->cache_key->use_ngg_culling)
if (!compiler_info->key.use_ngg_culling)
return false;
/* TODO: consider other heuristics here, such as PS execution time */

1
src/amd/vulkan/radv_shader.h
View file

@ -591,7 +591,6 @@ struct radv_compiler_info {
bool cache_disabled;
bool enable_nir_cache;
struct vk_pipeline_cache *mem_cache;
const struct radv_physical_device_cache_key *cache_key;
uint8_t override_compute_shader_version;
uint8_t override_graphics_shader_version;
uint8_t override_ray_tracing_shader_version;