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freedreno/a6xx: Add ctx->emit_sysmem()

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Once we introduce subpass, it won't be just a single IB.  But per
subpass clears + IB.  So interoduce a sysmem counterpart for
emit_tile().

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
This commit is contained in:
Rob Clark 2023-04-19 15:21:11 -07:00 • committed by Marge Bot
parent df1e357de8
commit 1a7590a47a
4 changed files with 28 additions and 12 deletions
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1
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -944,6 +944,5 @@ void
fd6_emit_init_screen(struct pipe_screen *pscreen)
{
struct fd_screen *screen = fd_screen(pscreen);
screen->emit_ib = fd6_emit_ib;
screen->mem_to_mem = fd6_mem_to_mem;
}

32
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -1630,7 +1630,6 @@ static void
fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
{
struct fd_ringbuffer *ring = batch->gmem;
struct fd_screen *screen = batch->ctx->screen;
fd6_emit_restore<CHIP>(batch, ring);
fd6_emit_lrz_flush(ring);
@ -1663,8 +1662,6 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
.buffers_location = BUFFERS_IN_SYSMEM,
});
emit_sysmem_clears<CHIP>(batch, ring);
emit_marker6(ring, 7);
OUT_PKT7(ring, CP_SET_MARKER, 1);
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
@ -1677,12 +1674,6 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
OUT_RING(ring, 0x1);
fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
fd6_cache_inv(batch, ring);
fd_wfi(batch, ring);
fd6_emit_ccu_cntl(ring, screen, false);
/* enable stream-out, with sysmem there is only one pass: */
OUT_REG(ring, A6XX_VPC_SO_DISABLE(false));
@ -1694,9 +1685,29 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
emit_msaa(ring, pfb->samples);
patch_fb_read_sysmem(batch);
emit_common_init(batch);
}
template <chip CHIP>
static void
fd6_emit_sysmem(struct fd_batch *batch)
assert_dt
{
struct fd_ringbuffer *ring = batch->gmem;
struct fd_screen *screen = batch->ctx->screen;
emit_sysmem_clears<CHIP>(batch, ring);
fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
fd6_cache_inv(batch, ring);
fd_wfi(batch, ring);
fd6_emit_ccu_cntl(ring, screen, false);
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
update_render_cntl<CHIP>(batch, pfb, false);
emit_common_init(batch);
fd6_emit_ib(ring, batch->draw);
}
static void
@ -1737,6 +1748,7 @@ fd6_gmem_init(struct pipe_context *pctx)
ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
ctx->emit_tile_fini = fd6_emit_tile_fini;
ctx->emit_sysmem_prep = fd6_emit_sysmem_prep<CHIP>;
ctx->emit_sysmem = fd6_emit_sysmem<CHIP>;
ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
}

1
src/gallium/drivers/freedreno/freedreno_context.h
View file

@ -559,6 +559,7 @@ struct fd_context {
/* optional, for GMEM bypass: */
void (*emit_sysmem_prep)(struct fd_batch *batch) dt;
void (*emit_sysmem)(struct fd_batch *batch) dt;
void (*emit_sysmem_fini)(struct fd_batch *batch) dt;
/* draw: */

6
src/gallium/drivers/freedreno/freedreno_gmem.c
View file

@ -672,7 +672,11 @@ render_sysmem(struct fd_batch *batch) assert_dt
trace_start_draw_ib(&batch->trace, batch->gmem);
}
/* emit IB to drawcmds: */
ctx->screen->emit_ib(batch->gmem, batch->draw);
if (ctx->emit_sysmem) {
ctx->emit_sysmem(batch);
} else {
ctx->screen->emit_ib(batch->gmem, batch->draw);
}
if (!batch->nondraw) {
trace_end_draw_ib(&batch->trace, batch->gmem);