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freedreno/a6xx: Move LRZ clear to blitter

Browse source 
This is where it belongs.  And will simplify moving LRZ clears to
fd6_gmem.cc

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
This commit is contained in:
Rob Clark 2023-04-19 09:33:06 -07:00 • committed by Marge Bot
parent c29e9dc054
commit df1e357de8
3 changed files with 77 additions and 113 deletions
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74
src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc
View file

@ -800,6 +800,80 @@ emit_clear_color(struct fd_ringbuffer *ring, enum pipe_format pfmt,
}
}
template <chip CHIP>
void
fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
{
struct fd_ringbuffer *ring = fd_batch_get_prologue(batch);
struct fd_context *ctx = batch->ctx;
if (DEBUG_BLIT) {
fprintf(stderr, "lrz clear:\ndst resource: ");
util_dump_resource(stderr, &zsbuf->b.b);
fprintf(stderr, "\n");
}
fd6_emit_ccu_cntl(ring, ctx->screen, false);
OUT_PKT7(ring, CP_SET_MARKER, 1);
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) | A6XX_GRAS_2D_DST_TL_Y(0));
OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(zsbuf->lrz_width - 1) |
A6XX_GRAS_2D_DST_BR_Y(zsbuf->lrz_height - 1));
union pipe_color_union clear_color = { .f = {depth} };
emit_clear_color(ring, PIPE_FORMAT_Z16_UNORM, &clear_color);
emit_blit_setup<CHIP>(ring, PIPE_FORMAT_Z16_UNORM, false, &clear_color, 0, ROTATE_0);
OUT_REG(ring,
A6XX_RB_2D_DST_INFO(
.color_format = FMT6_16_UNORM,
.tile_mode = TILE6_LINEAR,
.color_swap = WZYX,
),
A6XX_RB_2D_DST(
.bo = zsbuf->lrz,
),
A6XX_RB_2D_DST_PITCH(zsbuf->lrz_pitch * 2),
);
/*
* Blit command:
*/
if (ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit != ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL) {
/* This a non-context register, so we have to WFI before changing. */
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit);
}
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
if (ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit != ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL) {
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL);
}
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
fd_wfi(batch, ring);
zsbuf->lrz_valid = true;
zsbuf->lrz_direction = FD_LRZ_UNKNOWN;
}
template void fd6_clear_lrz<A6XX>(struct fd_batch *batch, struct fd_resource *zsbuf, double depth);
template void fd6_clear_lrz<A7XX>(struct fd_batch *batch, struct fd_resource *zsbuf, double depth);
/**
* Handle conversion of clear color
*/

2
src/gallium/drivers/freedreno/a6xx/fd6_blitter.h
View file

@ -42,6 +42,8 @@ unsigned fd6_tile_mode(const struct pipe_resource *tmpl);
* instead of CP_EVENT_WRITE::BLITs
*/
template <chip CHIP>
void fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth) assert_dt;
template <chip CHIP>
void fd6_clear_surface(struct fd_context *ctx, struct fd_ringbuffer *ring,
struct pipe_surface *psurf, const struct pipe_box *box2d,

114
src/gallium/drivers/freedreno/a6xx/fd6_draw.cc
View file

@ -36,6 +36,7 @@
#include "freedreno_state.h"
#include "fd6_barrier.h"
#include "fd6_blitter.h"
#include "fd6_context.h"
#include "fd6_draw.h"
#include "fd6_emit.h"
@ -419,117 +420,6 @@ fd6_draw_vbos(struct fd_context *ctx, const struct pipe_draw_info *info,
fd_context_all_clean(ctx);
}
template <chip CHIP>
static void
fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth) assert_dt
{
struct fd_ringbuffer *ring;
struct fd_screen *screen = batch->ctx->screen;
ring = fd_batch_get_prologue(batch);
emit_marker6(ring, 7);
OUT_PKT7(ring, CP_SET_MARKER, 1);
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
emit_marker6(ring, 7);
OUT_WFI5(ring);
fd6_emit_ccu_cntl(ring, screen, false);
OUT_REG(ring,
HLSQ_INVALIDATE_CMD(CHIP, .vs_state = true, .hs_state = true,
.ds_state = true, .gs_state = true,
.fs_state = true, .cs_state = true,
.cs_ibo = true, .gfx_ibo = true,
.gfx_shared_const = true,
.cs_bindless = 0x1f, .gfx_bindless = 0x1f));
emit_marker6(ring, 7);
OUT_PKT7(ring, CP_SET_MARKER, 1);
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
emit_marker6(ring, 7);
OUT_PKT4(ring, REG_A6XX_RB_2D_UNKNOWN_8C01, 1);
OUT_RING(ring, 0x0);
OUT_REG(ring,
SP_PS_2D_SRC_INFO(CHIP),
SP_PS_2D_SRC_SIZE(CHIP),
SP_PS_2D_SRC(CHIP),
SP_PS_2D_SRC_PITCH(CHIP),
);
OUT_REG(ring, SP_2D_DST_FORMAT(
CHIP,
// TODO probably FMT6_16_UNORM, but this matches what we used to emit:
.color_format = FMT6_32_32_32_32_FLOAT,
.mask = 0xf,
));
OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
OUT_RING(ring,
A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(FMT6_16_UNORM) | 0x4f00080);
OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
OUT_RING(ring, A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(FMT6_16_UNORM) | 0x4f00080);
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
fd_wfi(batch, ring);
OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
OUT_RING(ring, fui(depth));
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_16_UNORM) |
A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
OUT_RELOC(ring, zsbuf->lrz, 0, 0, 0);
OUT_RING(ring, A6XX_RB_2D_DST_PITCH(zsbuf->lrz_pitch * 2).value);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_REG(ring, A6XX_GRAS_2D_SRC_TL_X(0), A6XX_GRAS_2D_SRC_BR_X(0),
A6XX_GRAS_2D_SRC_TL_Y(0), A6XX_GRAS_2D_SRC_BR_Y(0));
OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) | A6XX_GRAS_2D_DST_TL_Y(0));
OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(zsbuf->lrz_width - 1) |
A6XX_GRAS_2D_DST_BR_Y(zsbuf->lrz_height - 1));
fd6_event_write(batch, ring, (enum vgt_event_type)0x3f, false);
if (screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit != screen->info->a6xx.magic.RB_DBG_ECO_CNTL) {
/* This a non-context register, so we have to WFI before changing. */
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
OUT_RING(ring, screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit);
}
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
if (screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit != screen->info->a6xx.magic.RB_DBG_ECO_CNTL) {
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
OUT_RING(ring, screen->info->a6xx.magic.RB_DBG_ECO_CNTL);
}
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
fd_wfi(batch, ring);
fd6_cache_inv(batch, ring);
}
static bool
is_z32(enum pipe_format format)
{
@ -563,8 +453,6 @@ fd6_clear(struct fd_context *ctx, enum fd_buffer_mask buffers,
if (has_depth && (buffers & FD_BUFFER_DEPTH)) {
struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
if (zsbuf->lrz && !is_z32(pfb->zsbuf->format)) {
zsbuf->lrz_valid = true;
zsbuf->lrz_direction = FD_LRZ_UNKNOWN;
fd6_clear_lrz<CHIP>(ctx->batch, zsbuf, depth);
}
}