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radv: simplify determining when a VS prolog is needed

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Only if a VS is compiled without the vertex input state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30045>
This commit is contained in:
Samuel Pitoiset 2024-07-04 17:42:56 +02:00 • committed by Marge Bot
parent 7608aada6f
commit 1a3b3b845b
1 changed files with 1 additions and 2 deletions
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3
src/amd/vulkan/radv_pipeline_graphics.c
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@ -1708,8 +1708,7 @@ radv_generate_graphics_state_key(const struct radv_device *device, const struct
}
/* Compile the pre-rasterization stages only when the vertex input interface is missing. */
if ((lib_flags & VK_GRAPHICS_PIPELINE_LIBRARY_PRE_RASTERIZATION_SHADERS_BIT_EXT) &&
!(lib_flags & VK_GRAPHICS_PIPELINE_LIBRARY_VERTEX_INPUT_INTERFACE_BIT_EXT)) {
if ((state->shader_stages && VK_SHADER_STAGE_VERTEX_BIT) && !state->vi) {
key.vs.has_prolog = true;
}