diff --git a/src/amd/common/ac_rgp_elf_object_pack.c b/src/amd/common/ac_rgp_elf_object_pack.c index 586c7d4492e..d84d71dff76 100644 --- a/src/amd/common/ac_rgp_elf_object_pack.c +++ b/src/amd/common/ac_rgp_elf_object_pack.c @@ -48,7 +48,7 @@ char hw_stage_symbol_string[RGP_HW_STAGE_MAX][16] = { }; static const char * -get_api_stage_string(gl_shader_stage stage) +get_api_stage_string(mesa_shader_stage stage) { switch (stage) { case MESA_SHADER_VERTEX: @@ -82,7 +82,7 @@ get_hw_stage_symbol(struct rgp_code_object_record *record, unsigned index) } static const char * -rt_subtype_from_stage(gl_shader_stage stage) +rt_subtype_from_stage(mesa_shader_stage stage) { switch (stage) { case MESA_SHADER_RAYGEN: diff --git a/src/amd/common/ac_rtld.h b/src/amd/common/ac_rtld.h index 166cb7f430a..a9edc4c63cc 100644 --- a/src/amd/common/ac_rtld.h +++ b/src/amd/common/ac_rtld.h @@ -68,7 +68,7 @@ typedef bool (*ac_rtld_get_external_symbol_cb)(enum amd_gfx_level gfx_level, voi struct ac_rtld_open_info { const struct radeon_info *info; struct ac_rtld_options options; - gl_shader_stage shader_type; + mesa_shader_stage shader_type; unsigned wave_size; unsigned num_parts; diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c index 3efaf222ba4..38b44421abc 100644 --- a/src/amd/common/ac_shader_util.c +++ b/src/amd/common/ac_shader_util.c @@ -865,7 +865,7 @@ unsigned ac_compute_cs_workgroup_size(const uint16_t sizes[3], bool variable, un return sizes[0] * sizes[1] * sizes[2]; } -unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_stage stage, +unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, mesa_shader_stage stage, unsigned tess_num_patches, unsigned tess_patch_in_vtx, unsigned tess_patch_out_vtx) @@ -1352,7 +1352,7 @@ ac_legacy_gs_compute_subgroup_info(enum mesa_prim input_prim, unsigned gs_vertic * upload depend on the subgroup size. */ bool -ac_ngg_compute_subgroup_info(enum amd_gfx_level gfx_level, gl_shader_stage es_stage, bool is_gs, +ac_ngg_compute_subgroup_info(enum amd_gfx_level gfx_level, mesa_shader_stage es_stage, bool is_gs, enum mesa_prim input_prim, unsigned gs_vertices_out, unsigned gs_invocations, unsigned max_workgroup_size, unsigned wave_size, unsigned esgs_vertex_stride, unsigned ngg_lds_vertex_size, unsigned ngg_lds_scratch_size, bool tess_turns_off_ngg, diff --git a/src/amd/common/ac_shader_util.h b/src/amd/common/ac_shader_util.h index 902fad5f5a2..8b853196572 100644 --- a/src/amd/common/ac_shader_util.h +++ b/src/amd/common/ac_shader_util.h @@ -282,7 +282,7 @@ void ac_compute_late_alloc(const struct radeon_info *info, bool ngg, bool ngg_cu unsigned ac_compute_cs_workgroup_size(const uint16_t sizes[3], bool variable, unsigned max); -unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_stage stage, +unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, mesa_shader_stage stage, unsigned tess_num_patches, unsigned tess_patch_in_vtx, unsigned tess_patch_out_vtx); @@ -304,7 +304,7 @@ void ac_get_scratch_tmpring_size(const struct radeon_info *info, unsigned num_sc unsigned bytes_per_wave, uint32_t *tmpring_size); unsigned -ac_ngg_get_scratch_lds_size(gl_shader_stage stage, +ac_ngg_get_scratch_lds_size(mesa_shader_stage stage, unsigned workgroup_size, unsigned wave_size, bool streamout_enabled, @@ -340,7 +340,7 @@ typedef struct { } ac_ngg_subgroup_info; bool -ac_ngg_compute_subgroup_info(enum amd_gfx_level gfx_level, gl_shader_stage es_stage, bool is_gs, +ac_ngg_compute_subgroup_info(enum amd_gfx_level gfx_level, mesa_shader_stage es_stage, bool is_gs, enum mesa_prim input_prim, unsigned gs_vertices_out, unsigned gs_invocations, unsigned max_workgroup_size, unsigned wave_size, unsigned esgs_vertex_stride, unsigned ngg_lds_vertex_size, unsigned ngg_lds_scratch_size, bool tess_turns_off_ngg, diff --git a/src/amd/common/nir/ac_nir_lower_ngg.c b/src/amd/common/nir/ac_nir_lower_ngg.c index 525810d4d0d..03eae2d8fb3 100644 --- a/src/amd/common/nir/ac_nir_lower_ngg.c +++ b/src/amd/common/nir/ac_nir_lower_ngg.c @@ -907,7 +907,7 @@ clipdist_culling_es_part(nir_builder *b, lower_ngg_nogs_state *s, } static unsigned -ngg_nogs_get_culling_pervertex_lds_size(gl_shader_stage stage, +ngg_nogs_get_culling_pervertex_lds_size(mesa_shader_stage stage, bool uses_instance_id, bool uses_primitive_id, unsigned *num_repacked_variables) @@ -1404,7 +1404,7 @@ ngg_nogs_build_streamout(nir_builder *b, lower_ngg_nogs_state *s) static unsigned ngg_nogs_get_pervertex_lds_size(lower_ngg_nogs_state *s, - gl_shader_stage stage, + mesa_shader_stage stage, bool streamout_enabled, bool export_prim_id, bool has_user_edgeflags) @@ -1455,7 +1455,7 @@ ngg_nogs_gather_outputs(nir_builder *b, struct exec_list *cf_list, lower_ngg_nog static unsigned ac_ngg_nogs_get_pervertex_lds_size(lower_ngg_nogs_state *s, - gl_shader_stage stage, + mesa_shader_stage stage, bool streamout_enabled, bool export_prim_id, bool has_user_edgeflags, @@ -1795,7 +1795,7 @@ ac_nir_lower_ngg_nogs(nir_shader *shader, const ac_nir_lower_ngg_options *option } unsigned -ac_ngg_get_scratch_lds_size(gl_shader_stage stage, +ac_ngg_get_scratch_lds_size(mesa_shader_stage stage, unsigned workgroup_size, unsigned wave_size, bool streamout_enabled, diff --git a/src/amd/compiler/aco_shader_info.h b/src/amd/compiler/aco_shader_info.h index 9d43331ff04..191bac4d74c 100644 --- a/src/amd/compiler/aco_shader_info.h +++ b/src/amd/compiler/aco_shader_info.h @@ -43,7 +43,7 @@ struct aco_vs_prolog_info { uint32_t misaligned_mask; uint32_t unaligned_mask; bool is_ngg; - gl_shader_stage next_stage; + mesa_shader_stage next_stage; }; struct aco_ps_epilog_info { diff --git a/src/amd/compiler/tests/helpers.cpp b/src/amd/compiler/tests/helpers.cpp index f9eb269f725..af764e957f7 100644 --- a/src/amd/compiler/tests/helpers.cpp +++ b/src/amd/compiler/tests/helpers.cpp @@ -129,7 +129,7 @@ setup_cs(const char* input_spec, enum amd_gfx_level gfx_level, enum radeon_famil } bool -setup_nir_cs(enum amd_gfx_level gfx_level, gl_shader_stage stage, enum radeon_family family, const char* subvariant) +setup_nir_cs(enum amd_gfx_level gfx_level, mesa_shader_stage stage, enum radeon_family family, const char* subvariant) { if (!set_variant(gfx_level, subvariant)) return false; diff --git a/src/amd/compiler/tests/helpers.h b/src/amd/compiler/tests/helpers.h index 006645a4389..c8181001264 100644 --- a/src/amd/compiler/tests/helpers.h +++ b/src/amd/compiler/tests/helpers.h @@ -63,7 +63,7 @@ bool setup_cs(const char* input_spec, enum amd_gfx_level gfx_level, enum radeon_family family = CHIP_UNKNOWN, const char* subvariant = "", unsigned wave_size = 64); bool -setup_nir_cs(enum amd_gfx_level gfx_level, gl_shader_stage stage = MESA_SHADER_COMPUTE, +setup_nir_cs(enum amd_gfx_level gfx_level, mesa_shader_stage stage = MESA_SHADER_COMPUTE, enum radeon_family family = CHIP_UNKNOWN, const char* subvariant = ""); void finish_program(aco::Program* program, bool endpgm = true, bool dominance = false); diff --git a/src/amd/llvm/ac_llvm_build.c b/src/amd/llvm/ac_llvm_build.c index e8d45ed5c15..9bacaa7d3fc 100644 --- a/src/amd/llvm/ac_llvm_build.c +++ b/src/amd/llvm/ac_llvm_build.c @@ -386,7 +386,7 @@ LLVMValueRef ac_build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type, unsigne return phi; } -void ac_build_s_barrier(struct ac_llvm_context *ctx, gl_shader_stage stage) +void ac_build_s_barrier(struct ac_llvm_context *ctx, mesa_shader_stage stage) { /* GFX6 only: s_barrier isn’t needed in TCS because an entire patch always fits into * a single wave due to a bug workaround disallowing multi-wave HS workgroups. diff --git a/src/amd/llvm/ac_llvm_build.h b/src/amd/llvm/ac_llvm_build.h index 3e973dd745a..94789b0dcae 100644 --- a/src/amd/llvm/ac_llvm_build.h +++ b/src/amd/llvm/ac_llvm_build.h @@ -176,7 +176,7 @@ void ac_build_type_name_for_intr(LLVMTypeRef type, char *buf, unsigned bufsize); LLVMValueRef ac_build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type, unsigned count_incoming, LLVMValueRef *values, LLVMBasicBlockRef *blocks); -void ac_build_s_barrier(struct ac_llvm_context *ctx, gl_shader_stage stage); +void ac_build_s_barrier(struct ac_llvm_context *ctx, mesa_shader_stage stage); void ac_build_optimization_barrier(struct ac_llvm_context *ctx, LLVMValueRef *pgpr, bool sgpr); LLVMValueRef ac_build_shader_clock(struct ac_llvm_context *ctx, mesa_scope scope); diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 3ea0475c1b7..00840d39eae 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -24,7 +24,7 @@ struct ac_nir_context { struct ac_shader_abi *abi; const struct ac_shader_args *args; - gl_shader_stage stage; + mesa_shader_stage stage; shader_info *info; LLVMValueRef *ssa_defs; diff --git a/src/amd/vulkan/layers/radv_sqtt_layer.c b/src/amd/vulkan/layers/radv_sqtt_layer.c index 0d8f7ffbf59..0ff829fd35b 100644 --- a/src/amd/vulkan/layers/radv_sqtt_layer.c +++ b/src/amd/vulkan/layers/radv_sqtt_layer.c @@ -43,7 +43,7 @@ radv_sqtt_emit_relocated_shaders(struct radv_cmd_buffer *cmd_buffer, struct radv } static uint64_t -radv_sqtt_shader_get_va_reloc(struct radv_pipeline *pipeline, gl_shader_stage stage) +radv_sqtt_shader_get_va_reloc(struct radv_pipeline *pipeline, mesa_shader_stage stage) { if (pipeline->type == RADV_PIPELINE_GRAPHICS) { struct radv_graphics_pipeline *graphics_pipeline = radv_pipeline_to_graphics(pipeline); diff --git a/src/amd/vulkan/nir/radv_meta_nir.c b/src/amd/vulkan/nir/radv_meta_nir.c index 6a8100ceafd..e76c3a3aade 100644 --- a/src/amd/vulkan/nir/radv_meta_nir.c +++ b/src/amd/vulkan/nir/radv_meta_nir.c @@ -16,7 +16,7 @@ #include "radv_physical_device.h" nir_builder PRINTFLIKE(3, 4) - radv_meta_nir_init_shader(struct radv_device *dev, gl_shader_stage stage, const char *name, ...) + radv_meta_nir_init_shader(struct radv_device *dev, mesa_shader_stage stage, const char *name, ...) { const struct radv_physical_device *pdev = radv_device_physical(dev); nir_builder b = nir_builder_init_simple_shader(stage, NULL, NULL); diff --git a/src/amd/vulkan/nir/radv_meta_nir.h b/src/amd/vulkan/nir/radv_meta_nir.h index f046560ed0f..43263326f34 100644 --- a/src/amd/vulkan/nir/radv_meta_nir.h +++ b/src/amd/vulkan/nir/radv_meta_nir.h @@ -22,7 +22,7 @@ struct radv_device; struct radeon_surf; nir_builder PRINTFLIKE(3, 4) - radv_meta_nir_init_shader(struct radv_device *dev, gl_shader_stage stage, const char *name, ...); + radv_meta_nir_init_shader(struct radv_device *dev, mesa_shader_stage stage, const char *name, ...); nir_shader *radv_meta_nir_build_vs_generate_vertices(struct radv_device *dev); nir_shader *radv_meta_nir_build_fs_noop(struct radv_device *dev); diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c b/src/amd/vulkan/nir/radv_nir_lower_abi.c index 6f3e8400891..d006c18eaa1 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_abi.c +++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c @@ -63,7 +63,7 @@ static bool lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state) { lower_abi_state *s = (lower_abi_state *)state; - gl_shader_stage stage = b->shader->info.stage; + mesa_shader_stage stage = b->shader->info.stage; b->cursor = nir_before_instr(&intrin->instr); diff --git a/src/amd/vulkan/nir/radv_nir_rt_shader.c b/src/amd/vulkan/nir/radv_nir_rt_shader.c index 82eecf6747f..f25b241a34e 100644 --- a/src/amd/vulkan/nir/radv_nir_rt_shader.c +++ b/src/amd/vulkan/nir/radv_nir_rt_shader.c @@ -1917,7 +1917,7 @@ lower_rt_instructions_monolithic(nir_shader *shader, struct radv_device *device, static nir_def * select_next_shader(nir_builder *b, nir_def *shader_addr, unsigned wave_size) { - gl_shader_stage stage = b->shader->info.stage; + mesa_shader_stage stage = b->shader->info.stage; nir_def *prio = nir_iand_imm(b, shader_addr, radv_rt_priority_mask); nir_def *ballot = nir_ballot(b, 1, wave_size, nir_imm_bool(b, true)); nir_def *ballot_traversal = nir_ballot(b, 1, wave_size, nir_ieq_imm(b, prio, radv_rt_priority_traversal)); diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 2adc0008154..bb721754b14 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2178,7 +2178,7 @@ radv_emit_hw_ngg(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *e const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); const uint64_t va = radv_shader_get_va(shader); - gl_shader_stage es_type; + mesa_shader_stage es_type; const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info; if (shader->info.stage == MESA_SHADER_GEOMETRY) { @@ -7702,7 +7702,7 @@ radv_bind_rt_prolog(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *rt_p /* This function binds/unbinds a shader to the cmdbuffer state. */ static void -radv_bind_shader(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *shader, gl_shader_stage stage) +radv_bind_shader(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *shader, mesa_shader_stage stage) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); @@ -10860,7 +10860,7 @@ radv_emit_streamout_enable_state(struct radv_cmd_buffer *cmd_buffer) cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_ENABLE; } -static gl_shader_stage +static mesa_shader_stage radv_cmdbuf_get_last_vgt_api_stage(const struct radv_cmd_buffer *cmd_buffer) { if (cmd_buffer->state.active_stages & VK_SHADER_STAGE_MESH_BIT_EXT) @@ -11504,7 +11504,7 @@ radv_bind_graphics_shaders(struct radv_cmd_buffer *cmd_buffer) } /* Determine the last VGT shader. */ - const gl_shader_stage last_vgt_api_stage = radv_cmdbuf_get_last_vgt_api_stage(cmd_buffer); + const mesa_shader_stage last_vgt_api_stage = radv_cmdbuf_get_last_vgt_api_stage(cmd_buffer); assume(last_vgt_api_stage != MESA_SHADER_NONE); if (pdev->info.has_vgt_flush_ngg_legacy_bug && @@ -14483,7 +14483,7 @@ radv_CmdBindShadersEXT(VkCommandBuffer commandBuffer, uint32_t stageCount, const VkShaderStageFlagBits bound_stages = 0; for (uint32_t i = 0; i < stageCount; i++) { - const gl_shader_stage stage = vk_to_mesa_shader_stage(pStages[i]); + const mesa_shader_stage stage = vk_to_mesa_shader_stage(pStages[i]); if (!pShaders) { cmd_buffer->state.shader_objs[stage] = NULL; diff --git a/src/amd/vulkan/radv_cmd_buffer.h b/src/amd/vulkan/radv_cmd_buffer.h index 06c82e15adf..cd6b89302c3 100644 --- a/src/amd/vulkan/radv_cmd_buffer.h +++ b/src/amd/vulkan/radv_cmd_buffer.h @@ -698,7 +698,7 @@ radv_get_push_constants_state(const struct radv_cmd_buffer *cmd_buffer, VkPipeli } static inline bool -radv_cmdbuf_has_stage(const struct radv_cmd_buffer *cmd_buffer, gl_shader_stage stage) +radv_cmdbuf_has_stage(const struct radv_cmd_buffer *cmd_buffer, mesa_shader_stage stage) { return !!(cmd_buffer->state.active_stages & mesa_to_vk_shader_stage(stage)); } diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c index 53fed63b28d..fd68ad2b357 100644 --- a/src/amd/vulkan/radv_debug.c +++ b/src/amd/vulkan/radv_debug.c @@ -439,7 +439,7 @@ radv_add_split_disasm(const char *disasm, uint64_t start_addr, unsigned *num, st } static void -radv_dump_annotated_shader(const struct radv_shader *shader, gl_shader_stage stage, struct ac_wave_info *waves, +radv_dump_annotated_shader(const struct radv_shader *shader, mesa_shader_stage stage, struct ac_wave_info *waves, unsigned num_waves, FILE *f) { uint64_t start_addr, end_addr; @@ -520,7 +520,7 @@ radv_dump_spirv(const struct radv_shader *shader, const char *sha1, const char * static void radv_dump_shader(struct radv_device *device, struct radv_pipeline *pipeline, struct radv_shader *shader, - gl_shader_stage stage, const char *dump_dir, FILE *f) + mesa_shader_stage stage, const char *dump_dir, FILE *f) { const struct radv_physical_device *pdev = radv_device_physical(device); diff --git a/src/amd/vulkan/radv_dgc.c b/src/amd/vulkan/radv_dgc.c index fe31b7dffd3..f13307457d6 100644 --- a/src/amd/vulkan/radv_dgc.c +++ b/src/amd/vulkan/radv_dgc.c @@ -132,7 +132,7 @@ radv_dgc_use_preamble(const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo) struct radv_shader * radv_dgc_get_shader(const VkGeneratedCommandsPipelineInfoEXT *pipeline_info, - const VkGeneratedCommandsShaderInfoEXT *eso_info, gl_shader_stage stage) + const VkGeneratedCommandsShaderInfoEXT *eso_info, mesa_shader_stage stage) { if (pipeline_info) { VK_FROM_HANDLE(radv_pipeline, pipeline, pipeline_info->pipeline); @@ -411,7 +411,7 @@ radv_get_sequence_size(const struct radv_indirect_command_layout *layout, const for (unsigned i = 0; i < eso_info->shaderCount; ++i) { VK_FROM_HANDLE(radv_shader_object, shader_object, eso_info->pShaders[i]); struct radv_shader *shader = shader_object->shader; - gl_shader_stage stage = shader->info.stage; + mesa_shader_stage stage = shader->info.stage; shaders[stage] = shader; } @@ -1576,7 +1576,7 @@ dgc_get_push_constant_stages(struct dgc_cmdbuf *cs) } static nir_def * -dgc_get_upload_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, gl_shader_stage stage) +dgc_get_upload_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, mesa_shader_stage stage) { const struct radv_indirect_command_layout *layout = cs->layout; nir_builder *b = cs->b; @@ -1593,7 +1593,7 @@ dgc_get_upload_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, gl_shader_stag } static nir_def * -dgc_get_inline_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, gl_shader_stage stage) +dgc_get_inline_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, mesa_shader_stage stage) { const struct radv_indirect_command_layout *layout = cs->layout; nir_builder *b = cs->b; @@ -1610,7 +1610,7 @@ dgc_get_inline_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, gl_shader_stag } static nir_def * -dgc_get_inline_mask(struct dgc_cmdbuf *cs, nir_def *param_offset, gl_shader_stage stage) +dgc_get_inline_mask(struct dgc_cmdbuf *cs, nir_def *param_offset, mesa_shader_stage stage) { const struct radv_indirect_command_layout *layout = cs->layout; nir_builder *b = cs->b; @@ -1693,7 +1693,7 @@ dgc_alloc_push_constant(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *se static void dgc_emit_push_constant_for_stage(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *sequence_id, - const struct dgc_pc_params *params, gl_shader_stage stage) + const struct dgc_pc_params *params, mesa_shader_stage stage) { const struct radv_indirect_command_layout *layout = cs->layout; VK_FROM_HANDLE(radv_pipeline_layout, pipeline_layout, layout->vk.layout); @@ -3047,7 +3047,7 @@ radv_prepare_dgc_graphics(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedC const VkGeneratedCommandsShaderInfoEXT *eso_info = vk_find_struct_const(pGeneratedCommandsInfo->pNext, GENERATED_COMMANDS_SHADER_INFO_EXT); - const gl_shader_stage first_stage = + const mesa_shader_stage first_stage = (layout->vk.dgc_info & BITFIELD_BIT(MESA_VK_DGC_DRAW_MESH)) ? MESA_SHADER_MESH : MESA_SHADER_VERTEX; struct radv_shader *first_shader = radv_dgc_get_shader(pipeline_info, eso_info, first_stage); @@ -3206,7 +3206,7 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn for (unsigned i = 0; i < eso_info->shaderCount; ++i) { VK_FROM_HANDLE(radv_shader_object, shader_object, eso_info->pShaders[i]); struct radv_shader *shader = shader_object->shader; - gl_shader_stage stage = shader->info.stage; + mesa_shader_stage stage = shader->info.stage; shaders[stage] = shader; } diff --git a/src/amd/vulkan/radv_dgc.h b/src/amd/vulkan/radv_dgc.h index 95b3581596d..4fa5e1826f1 100644 --- a/src/amd/vulkan/radv_dgc.h +++ b/src/amd/vulkan/radv_dgc.h @@ -65,6 +65,6 @@ bool radv_use_dgc_predication(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo); struct radv_shader *radv_dgc_get_shader(const VkGeneratedCommandsPipelineInfoEXT *pipeline_info, - const VkGeneratedCommandsShaderInfoEXT *eso_info, gl_shader_stage stage); + const VkGeneratedCommandsShaderInfoEXT *eso_info, mesa_shader_stage stage); #endif /* RADV_DGC_H */ diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index f4110dc4a6d..1d63ed68b9d 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -31,7 +31,7 @@ struct radv_shader_context { const struct radv_shader_info *shader_info; const struct radv_shader_args *args; - gl_shader_stage stage; + mesa_shader_stage stage; unsigned max_workgroup_size; LLVMContextRef context; @@ -63,7 +63,7 @@ create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module, LLVMBuil } static enum ac_llvm_calling_convention -get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage) +get_llvm_calling_convention(LLVMValueRef func, mesa_shader_stage stage) { switch (stage) { case MESA_SHADER_VERTEX: @@ -89,13 +89,13 @@ get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage) /* Returns whether the stage is a stage that can be directly before the GS */ static bool -is_pre_gs_stage(gl_shader_stage stage) +is_pre_gs_stage(mesa_shader_stage stage) { return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL; } static void -create_function(struct radv_shader_context *ctx, gl_shader_stage stage, bool has_previous_stage) +create_function(struct radv_shader_context *ctx, mesa_shader_stage stage, bool has_previous_stage) { if (ctx->ac.gfx_level >= GFX10) { if (is_pre_gs_stage(stage) && ctx->shader_info->is_ngg) { diff --git a/src/amd/vulkan/radv_physical_device.h b/src/amd/vulkan/radv_physical_device.h index 2daf091221c..63b82dfbe5b 100644 --- a/src/amd/vulkan/radv_physical_device.h +++ b/src/amd/vulkan/radv_physical_device.h @@ -256,7 +256,7 @@ vk_queue_to_radv(const struct radv_physical_device *pdev, int queue_family_index * specific shader stage (developers only). */ static inline bool -radv_use_llvm_for_stage(const struct radv_physical_device *pdev, UNUSED gl_shader_stage stage) +radv_use_llvm_for_stage(const struct radv_physical_device *pdev, UNUSED mesa_shader_stage stage) { return pdev->use_llvm; } diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 1412a69f7b6..7e71f87634f 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -137,7 +137,7 @@ radv_pipeline_get_shader_key(const struct radv_device *device, const VkPipelineS { const struct radv_physical_device *pdev = radv_device_physical(device); const struct radv_instance *instance = radv_physical_device_instance(pdev); - gl_shader_stage s = vk_to_mesa_shader_stage(stage->stage); + mesa_shader_stage s = vk_to_mesa_shader_stage(stage->stage); struct vk_pipeline_robustness_state rs; struct radv_shader_stage_key key = {0}; @@ -225,7 +225,7 @@ radv_pipeline_stage_init(VkPipelineCreateFlags2 pipeline_flags, const VkPipeline } void -radv_shader_layout_init(const struct radv_pipeline_layout *pipeline_layout, gl_shader_stage stage, +radv_shader_layout_init(const struct radv_pipeline_layout *pipeline_layout, mesa_shader_stage stage, struct radv_shader_layout *layout) { layout->num_sets = pipeline_layout->num_sets; @@ -740,7 +740,7 @@ radv_get_executable_count(struct radv_pipeline *pipeline) } static struct radv_shader * -radv_get_shader_from_executable_index(struct radv_pipeline *pipeline, int index, gl_shader_stage *stage) +radv_get_shader_from_executable_index(struct radv_pipeline *pipeline, int index, mesa_shader_stage *stage) { if (pipeline->type == RADV_PIPELINE_RAY_TRACING) { struct radv_ray_tracing_pipeline *rt_pipeline = radv_pipeline_to_ray_tracing(pipeline); @@ -794,7 +794,7 @@ radv_GetPipelineExecutablePropertiesKHR(VkDevice _device, const VkPipelineInfoKH if (!props) continue; - gl_shader_stage stage; + mesa_shader_stage stage; struct radv_shader *shader = radv_get_shader_from_executable_index(pipeline, executable_idx, &stage); props->stages = mesa_to_vk_shader_stage(stage); @@ -884,7 +884,7 @@ radv_GetPipelineExecutableStatisticsKHR(VkDevice _device, const VkPipelineExecut { VK_FROM_HANDLE(radv_device, device, _device); VK_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline); - gl_shader_stage stage; + mesa_shader_stage stage; struct radv_shader *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage); @@ -1070,7 +1070,7 @@ radv_GetPipelineExecutableInternalRepresentationsKHR( VK_FROM_HANDLE(radv_device, device, _device); VK_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline); const struct radv_physical_device *pdev = radv_device_physical(device); - gl_shader_stage stage; + mesa_shader_stage stage; struct radv_shader *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage); diff --git a/src/amd/vulkan/radv_pipeline.h b/src/amd/vulkan/radv_pipeline.h index f8d96a72cc8..dbb641d0861 100644 --- a/src/amd/vulkan/radv_pipeline.h +++ b/src/amd/vulkan/radv_pipeline.h @@ -91,7 +91,7 @@ void radv_pipeline_stage_init(VkPipelineCreateFlags2 pipeline_flags, const VkPip const struct radv_pipeline_layout *layout, const struct radv_shader_stage_key *stage_key, struct radv_shader_stage *out_stage); -void radv_shader_layout_init(const struct radv_pipeline_layout *pipeline_layout, gl_shader_stage stage, +void radv_shader_layout_init(const struct radv_pipeline_layout *pipeline_layout, mesa_shader_stage stage, struct radv_shader_layout *layout); void radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_state_key *gfx_state, diff --git a/src/amd/vulkan/radv_pipeline_cache.c b/src/amd/vulkan/radv_pipeline_cache.c index 79bfc11f280..0483936279e 100644 --- a/src/amd/vulkan/radv_pipeline_cache.c +++ b/src/amd/vulkan/radv_pipeline_cache.c @@ -365,7 +365,7 @@ radv_graphics_pipeline_cache_search(struct radv_device *device, struct vk_pipeli return false; for (unsigned i = 0; i < pipeline_obj->num_shaders; i++) { - gl_shader_stage s = pipeline_obj->shaders[i]->info.stage; + mesa_shader_stage s = pipeline_obj->shaders[i]->info.stage; if (s == MESA_SHADER_VERTEX && i > 0) { /* The GS copy-shader is a VS placed after all other stages */ assert(i == pipeline_obj->num_shaders - 1 && pipeline->base.shaders[MESA_SHADER_GEOMETRY]); @@ -539,7 +539,7 @@ radv_ray_tracing_pipeline_cache_insert(struct radv_device *device, struct vk_pip } nir_shader * -radv_pipeline_cache_lookup_nir(struct radv_device *device, struct vk_pipeline_cache *cache, gl_shader_stage stage, +radv_pipeline_cache_lookup_nir(struct radv_device *device, struct vk_pipeline_cache *cache, mesa_shader_stage stage, const blake3_hash key) { const struct radv_physical_device *pdev = radv_device_physical(device); @@ -704,7 +704,7 @@ radv_pipeline_cache_get_binaries(struct radv_device *device, const VkAllocationC for (unsigned i = 0; i < pipeline_obj->num_shaders; i++) { struct radv_shader *shader = pipeline_obj->shaders[i]; - gl_shader_stage s = shader->info.stage; + mesa_shader_stage s = shader->info.stage; if (s == MESA_SHADER_VERTEX && i > 0) { /* The GS copy-shader is a VS placed after all other stages */ diff --git a/src/amd/vulkan/radv_pipeline_cache.h b/src/amd/vulkan/radv_pipeline_cache.h index b60d2e7e147..0f0ae503b79 100644 --- a/src/amd/vulkan/radv_pipeline_cache.h +++ b/src/amd/vulkan/radv_pipeline_cache.h @@ -54,7 +54,7 @@ void radv_ray_tracing_pipeline_cache_insert(struct radv_device *device, struct v struct radv_ray_tracing_pipeline *pipeline, unsigned num_stages); nir_shader *radv_pipeline_cache_lookup_nir(struct radv_device *device, struct vk_pipeline_cache *cache, - gl_shader_stage stage, const blake3_hash key); + mesa_shader_stage stage, const blake3_hash key); void radv_pipeline_cache_insert_nir(struct radv_device *device, struct vk_pipeline_cache *cache, const blake3_hash key, const nir_shader *nir); diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 9a8c69295a9..0683732d077 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -1014,7 +1014,7 @@ radv_pipeline_init_dynamic_state(const struct radv_device *device, struct radv_g } struct radv_shader * -radv_get_shader(struct radv_shader *const *shaders, gl_shader_stage stage) +radv_get_shader(struct radv_shader *const *shaders, mesa_shader_stage stage) { if (stage == MESA_SHADER_VERTEX) { if (shaders[MESA_SHADER_VERTEX]) @@ -1250,7 +1250,7 @@ radv_link_shaders(const struct radv_device *device, struct radv_shader_stage *pr } } -static const gl_shader_stage graphics_shader_order[] = { +static const mesa_shader_stage graphics_shader_order[] = { MESA_SHADER_VERTEX, MESA_SHADER_TESS_CTRL, MESA_SHADER_TESS_EVAL, MESA_SHADER_GEOMETRY, MESA_SHADER_TASK, MESA_SHADER_MESH, @@ -1431,7 +1431,7 @@ radv_graphics_shaders_link(const struct radv_device *device, const struct radv_g /* Walk backwards to link */ struct radv_shader_stage *next_stage = NULL; for (int i = ARRAY_SIZE(graphics_shader_order) - 1; i >= 0; i--) { - gl_shader_stage s = graphics_shader_order[i]; + mesa_shader_stage s = graphics_shader_order[i]; if (!stages[s].nir) continue; @@ -1565,8 +1565,8 @@ radv_graphics_shaders_link_varyings(struct radv_shader_stage *stages) { /* Prepare shaders before running nir_opt_varyings. */ for (int i = 0; i < ARRAY_SIZE(graphics_shader_order); ++i) { - const gl_shader_stage s = graphics_shader_order[i]; - const gl_shader_stage next = stages[s].info.next_stage; + const mesa_shader_stage s = graphics_shader_order[i]; + const mesa_shader_stage next = stages[s].info.next_stage; if (!stages[s].nir || next == MESA_SHADER_NONE || !stages[next].nir) continue; @@ -1595,8 +1595,8 @@ radv_graphics_shaders_link_varyings(struct radv_shader_stage *stages) /* Optimize varyings from first to last stage. */ for (int i = 0; i < ARRAY_SIZE(graphics_shader_order); ++i) { - const gl_shader_stage s = graphics_shader_order[i]; - const gl_shader_stage next = stages[s].info.next_stage; + const mesa_shader_stage s = graphics_shader_order[i]; + const mesa_shader_stage next = stages[s].info.next_stage; if (!stages[s].nir || next == MESA_SHADER_NONE || !stages[next].nir) continue; @@ -1623,8 +1623,8 @@ radv_graphics_shaders_link_varyings(struct radv_shader_stage *stages) /* Optimize varyings from last to first stage. */ for (int i = highest_changed_producer; i >= 0; --i) { - const gl_shader_stage s = graphics_shader_order[i]; - const gl_shader_stage next = stages[s].info.next_stage; + const mesa_shader_stage s = graphics_shader_order[i]; + const mesa_shader_stage next = stages[s].info.next_stage; if (!stages[s].nir || next == MESA_SHADER_NONE || !stages[next].nir) continue; @@ -1649,8 +1649,8 @@ radv_graphics_shaders_link_varyings(struct radv_shader_stage *stages) /* Run optimizations and fixups after linking. */ for (int i = 0; i < ARRAY_SIZE(graphics_shader_order); ++i) { - const gl_shader_stage s = graphics_shader_order[i]; - const gl_shader_stage next = stages[s].info.next_stage; + const mesa_shader_stage s = graphics_shader_order[i]; + const mesa_shader_stage next = stages[s].info.next_stage; if (!stages[s].nir) continue; @@ -1687,8 +1687,8 @@ radv_graphics_shaders_link_varyings(struct radv_shader_stage *stages) * This needs to be done after all optimizations are done and shader info gathered. */ for (int i = 0; i < ARRAY_SIZE(graphics_shader_order); ++i) { - const gl_shader_stage s = graphics_shader_order[i]; - const gl_shader_stage next = stages[s].info.next_stage; + const mesa_shader_stage s = graphics_shader_order[i]; + const mesa_shader_stage next = stages[s].info.next_stage; if (!stages[s].nir || next == MESA_SHADER_NONE || !stages[next].nir) continue; @@ -2027,7 +2027,7 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const VkGr for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) { const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->pStages[i]; - gl_shader_stage s = vk_to_mesa_shader_stage(stage->stage); + mesa_shader_stage s = vk_to_mesa_shader_stage(stage->stage); key.stage_info[s] = radv_pipeline_get_shader_key(device, stage, create_flags, pCreateInfo->pNext); @@ -2150,8 +2150,8 @@ radv_consider_force_vrs(const struct radv_graphics_state_key *gfx_state, const s return true; } -static gl_shader_stage -radv_get_next_stage(gl_shader_stage stage, VkShaderStageFlagBits active_nir_stages) +static mesa_shader_stage +radv_get_next_stage(mesa_shader_stage stage, VkShaderStageFlagBits active_nir_stages) { switch (stage) { case MESA_SHADER_VERTEX: @@ -2233,7 +2233,7 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_shader_stage } if (gfx_level >= GFX9 && stages[MESA_SHADER_GEOMETRY].nir) { - gl_shader_stage pre_stage = stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; + mesa_shader_stage pre_stage = stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; radv_declare_shader_args(device, gfx_state, &stages[MESA_SHADER_GEOMETRY].info, MESA_SHADER_GEOMETRY, pre_stage, &stages[MESA_SHADER_GEOMETRY].args); stages[MESA_SHADER_GEOMETRY].info.user_sgprs_locs = stages[MESA_SHADER_GEOMETRY].args.user_sgprs_locs; @@ -2346,7 +2346,7 @@ radv_graphics_shaders_nir_to_asm(struct radv_device *device, struct vk_pipeline_ ((s == MESA_SHADER_GEOMETRY && (active_nir_stages & (VK_SHADER_STAGE_VERTEX_BIT | VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT))) || (s == MESA_SHADER_TESS_CTRL && (active_nir_stages & VK_SHADER_STAGE_VERTEX_BIT)))) { - gl_shader_stage pre_stage; + mesa_shader_stage pre_stage; if (s == MESA_SHADER_GEOMETRY && (active_nir_stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)) { pre_stage = MESA_SHADER_TESS_EVAL; @@ -2442,7 +2442,7 @@ radv_pipeline_import_retained_shaders(const struct radv_device *device, struct r /* Import the stages (SPIR-V only in case of cache hits). */ for (uint32_t i = 0; i < lib->stage_count; i++) { const VkPipelineShaderStageCreateInfo *sinfo = &lib->stages[i]; - gl_shader_stage s = vk_to_mesa_shader_stage(sinfo->stage); + mesa_shader_stage s = vk_to_mesa_shader_stage(sinfo->stage); radv_pipeline_stage_init(lib->base.base.create_flags, sinfo, &lib->layout, &lib->stage_keys[s], &stages[s]); } @@ -2670,7 +2670,7 @@ radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cac } radv_foreach_stage (i, active_nir_stages) { - gl_shader_stage next_stage; + mesa_shader_stage next_stage; if (stages[i].next_stage != MESA_SHADER_NONE) { next_stage = stages[i].next_stage; @@ -2925,7 +2925,7 @@ radv_generate_graphics_pipeline_state(struct radv_device *device, const VkGraphi for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) { const VkPipelineShaderStageCreateInfo *sinfo = &pCreateInfo->pStages[i]; - gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage); radv_pipeline_stage_init(create_flags, sinfo, &gfx_state->layout, &gfx_state->key.stage_info[stage], &gfx_state->stages[stage]); @@ -3032,7 +3032,7 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk gfx_pipeline_lib->stage_count = pCreateInfo->stageCount; for (unsigned i = 0; i < pCreateInfo->stageCount; i++) { - gl_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->pStages[i].stage); + mesa_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->pStages[i].stage); gfx_pipeline_lib->stage_keys[s] = gfx_state->key.stage_info[s]; } } @@ -3080,7 +3080,7 @@ done: uint32_t num_feedbacks = 0; for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) { - gl_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->pStages[i].stage); + mesa_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->pStages[i].stage); creation_feedback->pPipelineStageCreationFeedbacks[num_feedbacks++] = stages[s].feedback; } @@ -3270,7 +3270,7 @@ radv_pipeline_init_shader_stages_state(const struct radv_device *device, struct } } - gl_shader_stage first_stage = + mesa_shader_stage first_stage = radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH) ? MESA_SHADER_MESH : MESA_SHADER_VERTEX; const struct radv_shader *shader = radv_get_shader(pipeline->base.shaders, first_stage); diff --git a/src/amd/vulkan/radv_pipeline_graphics.h b/src/amd/vulkan/radv_pipeline_graphics.h index bc550884d8f..fdc0ea8e379 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.h +++ b/src/amd/vulkan/radv_pipeline_graphics.h @@ -112,7 +112,7 @@ struct radv_graphics_pipeline { uint32_t db_render_control; /* Last pre-PS API stage */ - gl_shader_stage last_vgt_api_stage; + mesa_shader_stage last_vgt_api_stage; unsigned rast_prim; @@ -173,7 +173,7 @@ struct radv_graphics_lib_pipeline { RADV_DECL_PIPELINE_DOWNCAST(graphics_lib, RADV_PIPELINE_GRAPHICS_LIB) static inline bool -radv_pipeline_has_stage(const struct radv_graphics_pipeline *pipeline, gl_shader_stage stage) +radv_pipeline_has_stage(const struct radv_graphics_pipeline *pipeline, mesa_shader_stage stage) { return pipeline->base.shaders[stage]; } @@ -589,7 +589,7 @@ struct radv_ia_multi_vgt_param_helpers radv_compute_ia_multi_vgt_param(const str void radv_get_viewport_xform(const VkViewport *viewport, float scale[3], float translate[3]); -struct radv_shader *radv_get_shader(struct radv_shader *const *shaders, gl_shader_stage stage); +struct radv_shader *radv_get_shader(struct radv_shader *const *shaders, mesa_shader_stage stage); struct radv_ps_epilog_state { uint8_t color_attachment_count; diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c index acdcea3dff2..02f59b50a9d 100644 --- a/src/amd/vulkan/radv_pipeline_rt.c +++ b/src/amd/vulkan/radv_pipeline_rt.c @@ -75,7 +75,7 @@ radv_generate_rt_shaders_key(const struct radv_device *device, const VkRayTracin for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) { const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->pStages[i]; - gl_shader_stage s = vk_to_mesa_shader_stage(stage->stage); + mesa_shader_stage s = vk_to_mesa_shader_stage(stage->stage); stage_keys[s] = radv_pipeline_get_shader_key(device, stage, create_flags, pCreateInfo->pNext); } @@ -303,7 +303,7 @@ radv_init_rt_stage_hashes(const struct radv_device *device, VkPipelineCreateFlag } else { for (uint32_t idx = 0; idx < pCreateInfo->stageCount; idx++) { const VkPipelineShaderStageCreateInfo *sinfo = &pCreateInfo->pStages[idx]; - gl_shader_stage s = vk_to_mesa_shader_stage(sinfo->stage); + mesa_shader_stage s = vk_to_mesa_shader_stage(sinfo->stage); struct mesa_sha1 ctx; _mesa_sha1_init(&ctx); @@ -620,7 +620,7 @@ radv_rt_compile_shaders(struct radv_device *device, struct vk_pipeline_cache *ca int64_t stage_start = os_time_get_nano(); struct radv_shader_stage *stage = &stages[i]; - gl_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->pStages[i].stage); + mesa_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->pStages[i].stage); radv_pipeline_stage_init(pipeline->base.base.create_flags, &pCreateInfo->pStages[i], pipeline_layout, &stage_keys[s], stage); diff --git a/src/amd/vulkan/radv_pipeline_rt.h b/src/amd/vulkan/radv_pipeline_rt.h index c1ce703c0d7..787ead3eb3f 100644 --- a/src/amd/vulkan/radv_pipeline_rt.h +++ b/src/amd/vulkan/radv_pipeline_rt.h @@ -93,7 +93,7 @@ struct radv_ray_tracing_stage_info { struct radv_ray_tracing_stage { struct vk_pipeline_cache_object *nir; struct radv_shader *shader; - gl_shader_stage stage; + mesa_shader_stage stage; uint32_t stack_size; struct radv_ray_tracing_stage_info info; diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 3a2843d43dc..9ab49e39f4c 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -49,7 +49,7 @@ #endif static void -get_nir_options_for_stage(struct radv_physical_device *pdev, gl_shader_stage stage) +get_nir_options_for_stage(struct radv_physical_device *pdev, mesa_shader_stage stage) { const struct radv_instance *instance = radv_physical_device_instance(pdev); nir_shader_compiler_options *options = &pdev->nir_options[stage]; @@ -71,7 +71,7 @@ get_nir_options_for_stage(struct radv_physical_device *pdev, gl_shader_stage sta void radv_get_nir_options(struct radv_physical_device *pdev) { - for (gl_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_VULKAN_SHADER_STAGES; stage++) + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_VULKAN_SHADER_STAGES; stage++) get_nir_options_for_stage(pdev, stage); } @@ -111,7 +111,7 @@ is_meta_shader(nir_shader *nir) } static uint64_t -radv_dump_flag_for_stage(const gl_shader_stage stage) +radv_dump_flag_for_stage(const mesa_shader_stage stage) { switch (stage) { case MESA_SHADER_VERTEX: @@ -1367,7 +1367,7 @@ radv_destroy_shader_upload_queue(struct radv_device *device) } static bool -radv_should_use_wgp_mode(const struct radv_device *device, gl_shader_stage stage, const struct radv_shader_info *info) +radv_should_use_wgp_mode(const struct radv_device *device, mesa_shader_stage stage, const struct radv_shader_info *info) { const struct radv_physical_device *pdev = radv_device_physical(device); enum amd_gfx_level chip = pdev->info.gfx_level; @@ -1963,7 +1963,7 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi } const struct radv_shader_info *info = &binary->info; - gl_shader_stage stage = binary->info.stage; + mesa_shader_stage stage = binary->info.stage; bool scratch_enabled = config->scratch_bytes_per_wave > 0; const bool trap_enabled = !!device->trap_handler_shader; /* On GFX12, TRAP_PRESENT doesn't exist for compute shaders and it's enabled by default. */ @@ -2031,7 +2031,7 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi config->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(args->num_user_sgprs >> 5); } - gl_shader_stage es_stage = MESA_SHADER_NONE; + mesa_shader_stage es_stage = MESA_SHADER_NONE; if (pdev->info.gfx_level >= GFX9) { es_stage = stage == MESA_SHADER_GEOMETRY ? info->gs.es_type : stage; } @@ -2625,7 +2625,7 @@ radv_get_max_waves(const struct radv_device *device, const struct ac_shader_conf const struct radeon_info *gpu_info = &pdev->info; const enum amd_gfx_level gfx_level = gpu_info->gfx_level; const uint8_t wave_size = info->wave_size; - gl_shader_stage stage = info->stage; + mesa_shader_stage stage = info->stage; unsigned max_simd_waves = gpu_info->max_waves_per_simd; unsigned lds_per_workgroup = 0; unsigned waves_per_workgroup = 1; @@ -3074,7 +3074,7 @@ radv_fill_nir_compiler_options(struct radv_nir_compiler_options *options, struct } void -radv_set_stage_key_robustness(const struct vk_pipeline_robustness_state *rs, gl_shader_stage stage, +radv_set_stage_key_robustness(const struct vk_pipeline_robustness_state *rs, mesa_shader_stage stage, struct radv_shader_stage_key *key) { if (rs->storage_buffers == VK_PIPELINE_ROBUSTNESS_BUFFER_BEHAVIOR_ROBUST_BUFFER_ACCESS_2) @@ -3088,7 +3088,7 @@ radv_set_stage_key_robustness(const struct vk_pipeline_robustness_state *rs, gl_ } static struct radv_shader_binary * -shader_compile(struct radv_device *device, struct nir_shader *const *shaders, int shader_count, gl_shader_stage stage, +shader_compile(struct radv_device *device, struct nir_shader *const *shaders, int shader_count, mesa_shader_stage stage, const struct radv_shader_info *info, const struct radv_shader_args *args, const struct radv_shader_stage_key *stage_key, struct radv_nir_compiler_options *options) { @@ -3136,7 +3136,7 @@ radv_shader_nir_to_asm(struct radv_device *device, struct radv_shader_stage *pl_ struct nir_shader *const *shaders, int shader_count, const struct radv_graphics_state_key *gfx_state, bool keep_shader_info, bool keep_statistic_info) { - gl_shader_stage stage = shaders[shader_count - 1]->info.stage; + mesa_shader_stage stage = shaders[shader_count - 1]->info.stage; struct radv_shader_info *info = &pl_stage->info; bool dump_shader = false; @@ -3177,7 +3177,7 @@ radv_create_trap_handler_shader(struct radv_device *device) { const struct radv_physical_device *pdev = radv_device_physical(device); const struct radv_instance *instance = radv_physical_device_instance(pdev); - gl_shader_stage stage = MESA_SHADER_COMPUTE; + mesa_shader_stage stage = MESA_SHADER_COMPUTE; struct radv_shader_stage_key stage_key = {0}; struct radv_shader_info info = {0}; struct radv_nir_compiler_options options = {0}; @@ -3490,7 +3490,7 @@ radv_find_shader(struct radv_device *device, uint64_t pc) } const char * -radv_get_shader_name(const struct radv_shader_info *info, gl_shader_stage stage) +radv_get_shader_name(const struct radv_shader_info *info, mesa_shader_stage stage) { switch (stage) { case MESA_SHADER_VERTEX: @@ -3628,7 +3628,7 @@ radv_get_tess_wg_info(const struct radv_physical_device *pdev, const ac_nir_tess VkResult radv_dump_shader_stats(struct radv_device *device, struct radv_pipeline *pipeline, struct radv_shader *shader, - gl_shader_stage stage, FILE *output) + mesa_shader_stage stage, FILE *output) { VkPipelineExecutablePropertiesKHR *props = NULL; uint32_t prop_count = 0; diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 5c39fe44e54..88b671ea496 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -46,7 +46,7 @@ enum { #define RADV_STAGE_MASK ((1 << MESA_VULKAN_SHADER_STAGES) - 1) #define radv_foreach_stage(stage, stage_bits) \ - for (gl_shader_stage stage, __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \ + for (mesa_shader_stage stage, __tmp = (mesa_shader_stage)((stage_bits) & RADV_STAGE_MASK); \ stage = ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage))) enum radv_nggc_settings { @@ -257,8 +257,8 @@ struct radv_shader_layout { }; struct radv_shader_stage { - gl_shader_stage stage; - gl_shader_stage next_stage; + mesa_shader_stage stage; + mesa_shader_stage next_stage; struct { const struct vk_object_base *object; @@ -339,7 +339,7 @@ struct radv_vs_prolog_key { bool as_ls; bool is_ngg; bool wave32; - gl_shader_stage next_stage; + mesa_shader_stage next_stage; }; enum radv_shader_binary_type { RADV_BINARY_TYPE_LEGACY, RADV_BINARY_TYPE_RTLD }; @@ -608,7 +608,7 @@ unsigned radv_get_max_waves(const struct radv_device *device, const struct ac_sh unsigned radv_get_max_scratch_waves(const struct radv_device *device, struct radv_shader *shader); -const char *radv_get_shader_name(const struct radv_shader_info *info, gl_shader_stage stage); +const char *radv_get_shader_name(const struct radv_shader_info *info, mesa_shader_stage stage); unsigned radv_compute_spi_ps_input(const struct radv_physical_device *pdev, const struct radv_graphics_state_key *gfx_state, @@ -619,7 +619,7 @@ bool radv_can_dump_shader(struct radv_device *device, nir_shader *nir); bool radv_can_dump_shader_stats(struct radv_device *device, nir_shader *nir); VkResult radv_dump_shader_stats(struct radv_device *device, struct radv_pipeline *pipeline, struct radv_shader *shader, - gl_shader_stage stage, FILE *output); + mesa_shader_stage stage, FILE *output); /* Returns true on success and false on failure */ bool radv_shader_reupload(struct radv_device *device, struct radv_shader *shader); @@ -700,7 +700,7 @@ enum radv_rt_priority { }; static inline enum radv_rt_priority -radv_get_rt_priority(gl_shader_stage stage) +radv_get_rt_priority(mesa_shader_stage stage) { switch (stage) { case MESA_SHADER_RAYGEN: @@ -739,7 +739,7 @@ uint32_t radv_get_user_sgpr(const struct radv_shader *shader, int idx); void radv_precompute_registers_hw_ngg(struct radv_device *device, const struct ac_shader_config *config, struct radv_shader_info *info); -void radv_set_stage_key_robustness(const struct vk_pipeline_robustness_state *rs, gl_shader_stage stage, +void radv_set_stage_key_robustness(const struct vk_pipeline_robustness_state *rs, mesa_shader_stage stage, struct radv_shader_stage_key *key); #endif /* RADV_SHADER_H */ diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c index 17863a72378..842a501e21f 100644 --- a/src/amd/vulkan/radv_shader_args.c +++ b/src/amd/vulkan/radv_shader_args.c @@ -197,7 +197,7 @@ declare_vs_input_vgprs(enum amd_gfx_level gfx_level, const struct radv_shader_in } static void -declare_streamout_sgprs(const struct radv_shader_info *info, struct radv_shader_args *args, gl_shader_stage stage) +declare_streamout_sgprs(const struct radv_shader_info *info, struct radv_shader_args *args, mesa_shader_stage stage) { int i; @@ -300,7 +300,7 @@ declare_ngg_sgprs(const struct radv_shader_info *info, struct radv_shader_args * } static void -radv_init_shader_args(const struct radv_device *device, gl_shader_stage stage, struct radv_shader_args *args) +radv_init_shader_args(const struct radv_device *device, mesa_shader_stage stage, struct radv_shader_args *args) { const struct radv_physical_device *pdev = radv_device_physical(device); memset(args, 0, sizeof(*args)); @@ -520,7 +520,7 @@ declare_unmerged_vs_tes_gs_args(const enum amd_gfx_level gfx_level, const struct static void declare_shader_args(const struct radv_device *device, const struct radv_graphics_state_key *gfx_state, - const struct radv_shader_info *info, gl_shader_stage stage, gl_shader_stage previous_stage, + const struct radv_shader_info *info, mesa_shader_stage stage, mesa_shader_stage previous_stage, struct radv_shader_args *args, struct user_sgpr_info *user_sgpr_info) { const struct radv_physical_device *pdev = radv_device_physical(device); @@ -878,7 +878,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics void radv_declare_shader_args(const struct radv_device *device, const struct radv_graphics_state_key *gfx_state, - const struct radv_shader_info *info, gl_shader_stage stage, gl_shader_stage previous_stage, + const struct radv_shader_info *info, mesa_shader_stage stage, mesa_shader_stage previous_stage, struct radv_shader_args *args) { declare_shader_args(device, gfx_state, info, stage, previous_stage, args, NULL); diff --git a/src/amd/vulkan/radv_shader_args.h b/src/amd/vulkan/radv_shader_args.h index 894eb70003b..2006c967cd4 100644 --- a/src/amd/vulkan/radv_shader_args.h +++ b/src/amd/vulkan/radv_shader_args.h @@ -135,8 +135,8 @@ struct radv_ps_epilog_key; struct radv_device; void radv_declare_shader_args(const struct radv_device *device, const struct radv_graphics_state_key *gfx_state, - const struct radv_shader_info *info, gl_shader_stage stage, - gl_shader_stage previous_stage, struct radv_shader_args *args); + const struct radv_shader_info *info, mesa_shader_stage stage, + mesa_shader_stage previous_stage, struct radv_shader_args *args); void radv_declare_ps_epilog_args(const struct radv_device *device, const struct radv_ps_epilog_key *key, struct radv_shader_args *args); diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 79f9872aec9..ed589a7495a 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -471,7 +471,7 @@ radv_set_vs_output_param(struct radv_device *device, const struct nir_shader *ni } static uint8_t -radv_get_wave_size(struct radv_device *device, gl_shader_stage stage, const struct radv_shader_info *info, +radv_get_wave_size(struct radv_device *device, mesa_shader_stage stage, const struct radv_shader_info *info, const struct radv_shader_stage_key *stage_key) { const struct radv_physical_device *pdev = radv_device_physical(device); @@ -492,7 +492,7 @@ radv_get_wave_size(struct radv_device *device, gl_shader_stage stage, const stru } static uint8_t -radv_get_ballot_bit_size(struct radv_device *device, gl_shader_stage stage, const struct radv_shader_info *info, +radv_get_ballot_bit_size(struct radv_device *device, mesa_shader_stage stage, const struct radv_shader_info *info, const struct radv_shader_stage_key *stage_key) { if (stage_key->subgroup_required_size) @@ -1064,7 +1064,7 @@ radv_is_merged_shader_compiled_separately(const struct radv_device *device, cons } void -radv_nir_shader_info_init(gl_shader_stage stage, gl_shader_stage next_stage, struct radv_shader_info *info) +radv_nir_shader_info_init(mesa_shader_stage stage, mesa_shader_stage next_stage, struct radv_shader_info *info) { memset(info, 0, sizeof(*info)); @@ -1573,7 +1573,7 @@ radv_nir_shader_info_link(struct radv_device *device, const struct radv_graphics /* Merge shader info for VS+GS or TES+GS. */ if ((stages[MESA_SHADER_VERTEX].nir || stages[MESA_SHADER_TESS_EVAL].nir) && stages[MESA_SHADER_GEOMETRY].nir) { - gl_shader_stage pre_stage = stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; + mesa_shader_stage pre_stage = stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; radv_nir_shader_info_merge(&stages[pre_stage], &stages[MESA_SHADER_GEOMETRY]); } diff --git a/src/amd/vulkan/radv_shader_info.h b/src/amd/vulkan/radv_shader_info.h index f9aa4bf69f0..e65cccc3ab4 100644 --- a/src/amd/vulkan/radv_shader_info.h +++ b/src/amd/vulkan/radv_shader_info.h @@ -103,8 +103,8 @@ struct radv_shader_info { struct radv_vs_output_info outinfo; unsigned workgroup_size; bool force_vrs_per_vertex; - gl_shader_stage stage; - gl_shader_stage next_stage; + mesa_shader_stage stage; + mesa_shader_stage next_stage; enum radv_shader_type type; uint32_t user_data_0; bool inputs_linked; @@ -319,7 +319,7 @@ struct radv_shader_info { } regs; }; -void radv_nir_shader_info_init(gl_shader_stage stage, gl_shader_stage next_stage, struct radv_shader_info *info); +void radv_nir_shader_info_init(mesa_shader_stage stage, mesa_shader_stage next_stage, struct radv_shader_info *info); void radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir, const struct radv_shader_layout *layout, const struct radv_shader_stage_key *stage_key, diff --git a/src/amd/vulkan/radv_shader_object.c b/src/amd/vulkan/radv_shader_object.c index ee7adfdb80b..bb551e2a817 100644 --- a/src/amd/vulkan/radv_shader_object.c +++ b/src/amd/vulkan/radv_shader_object.c @@ -123,7 +123,7 @@ static VkResult radv_shader_object_init_graphics(struct radv_shader_object *shader_obj, struct radv_device *device, const VkShaderCreateInfoEXT *pCreateInfo) { - gl_shader_stage stage = vk_to_mesa_shader_stage(pCreateInfo->stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(pCreateInfo->stage); struct radv_shader_stage stages[MESA_VULKAN_SHADER_STAGES]; for (unsigned i = 0; i < MESA_VULKAN_SHADER_STAGES; i++) { @@ -440,7 +440,7 @@ radv_shader_object_create_linked(VkDevice _device, uint32_t createInfoCount, con for (unsigned i = 0; i < createInfoCount; i++) { const VkShaderCreateInfoEXT *pCreateInfo = &pCreateInfos[i]; - gl_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->stage); + mesa_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->stage); radv_shader_stage_init(pCreateInfo, &stages[s]); } @@ -497,7 +497,7 @@ radv_shader_object_create_linked(VkDevice _device, uint32_t createInfoCount, con for (unsigned i = 0; i < createInfoCount; i++) { const VkShaderCreateInfoEXT *pCreateInfo = &pCreateInfos[i]; - gl_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->stage); + mesa_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->stage); struct radv_shader_object *shader_obj; shader_obj = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*shader_obj), 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); diff --git a/src/amd/vulkan/radv_shader_object.h b/src/amd/vulkan/radv_shader_object.h index f3e4444943b..f1718b36eb2 100644 --- a/src/amd/vulkan/radv_shader_object.h +++ b/src/amd/vulkan/radv_shader_object.h @@ -16,7 +16,7 @@ struct radv_shader_object { struct vk_object_base base; - gl_shader_stage stage; + mesa_shader_stage stage; VkShaderCodeTypeEXT code_type; diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c index 9d0698166d7..a6c86b6f37a 100644 --- a/src/asahi/compiler/agx_compile.c +++ b/src/asahi/compiler/agx_compile.c @@ -1322,7 +1322,7 @@ agx_emit_intrinsic(agx_builder *b, nir_intrinsic_instr *instr) agx_index dst = nir_intrinsic_infos[instr->intrinsic].has_dest ? agx_def_index(&instr->def) : agx_null(); - gl_shader_stage stage = b->shader->stage; + mesa_shader_stage stage = b->shader->stage; switch (instr->intrinsic) { case nir_intrinsic_load_barycentric_pixel: diff --git a/src/asahi/compiler/agx_compiler.h b/src/asahi/compiler/agx_compiler.h index d57181e9d8b..e7dc9cd1aac 100644 --- a/src/asahi/compiler/agx_compiler.h +++ b/src/asahi/compiler/agx_compiler.h @@ -483,7 +483,7 @@ typedef struct agx_block { typedef struct { nir_shader *nir; - gl_shader_stage stage; + mesa_shader_stage stage; bool is_preamble; unsigned scratch_size_B; diff --git a/src/asahi/vulkan/hk_cmd_buffer.c b/src/asahi/vulkan/hk_cmd_buffer.c index cc88e79a0de..3c14113f658 100644 --- a/src/asahi/vulkan/hk_cmd_buffer.c +++ b/src/asahi/vulkan/hk_cmd_buffer.c @@ -337,7 +337,7 @@ hk_CmdPipelineBarrier2(VkCommandBuffer commandBuffer, void hk_cmd_bind_shaders(struct vk_command_buffer *vk_cmd, uint32_t stage_count, - const gl_shader_stage *stages, + const mesa_shader_stage *stages, struct vk_shader **const shaders) { struct hk_cmd_buffer *cmd = container_of(vk_cmd, struct hk_cmd_buffer, vk); diff --git a/src/asahi/vulkan/hk_cmd_buffer.h b/src/asahi/vulkan/hk_cmd_buffer.h index 8f1928c93c7..aaf3d172a3f 100644 --- a/src/asahi/vulkan/hk_cmd_buffer.h +++ b/src/asahi/vulkan/hk_cmd_buffer.h @@ -786,11 +786,11 @@ void hk_cmd_invalidate_graphics_state(struct hk_cmd_buffer *cmd); void hk_cmd_invalidate_compute_state(struct hk_cmd_buffer *cmd); void hk_cmd_bind_shaders(struct vk_command_buffer *vk_cmd, uint32_t stage_count, - const gl_shader_stage *stages, + const mesa_shader_stage *stages, struct vk_shader **const shaders); void hk_cmd_bind_graphics_shader(struct hk_cmd_buffer *cmd, - const gl_shader_stage stage, + const mesa_shader_stage stage, struct hk_api_shader *shader); void hk_cmd_bind_compute_shader(struct hk_cmd_buffer *cmd, diff --git a/src/asahi/vulkan/hk_cmd_draw.c b/src/asahi/vulkan/hk_cmd_draw.c index 8d5ae5b3b89..f3170b38edf 100644 --- a/src/asahi/vulkan/hk_cmd_draw.c +++ b/src/asahi/vulkan/hk_cmd_draw.c @@ -1701,7 +1701,7 @@ hk_launch_tess(struct hk_cmd_buffer *cmd, struct hk_cs *cs, void hk_cmd_bind_graphics_shader(struct hk_cmd_buffer *cmd, - const gl_shader_stage stage, + const mesa_shader_stage stage, struct hk_api_shader *shader) { struct hk_device *dev = hk_cmd_buffer_device(cmd); @@ -1946,7 +1946,7 @@ hk_update_fast_linked(struct hk_cmd_buffer *cmd, struct hk_shader *shader, { struct hk_device *dev = hk_cmd_buffer_device(cmd); struct hk_linked_shader *new = hk_get_fast_linked(dev, shader, key); - gl_shader_stage stage = shader->info.stage; + mesa_shader_stage stage = shader->info.stage; if (cmd->state.gfx.linked[stage] != new) { cmd->state.gfx.linked[stage] = new; diff --git a/src/asahi/vulkan/hk_shader.c b/src/asahi/vulkan/hk_shader.c index bfbe9f4f430..fc2bee43563 100644 --- a/src/asahi/vulkan/hk_shader.c +++ b/src/asahi/vulkan/hk_shader.c @@ -104,7 +104,7 @@ hk_physical_device_compiler_flags(const struct hk_physical_device *pdev) } const nir_shader_compiler_options * -hk_get_nir_options(struct vk_physical_device *vk_pdev, gl_shader_stage stage, +hk_get_nir_options(struct vk_physical_device *vk_pdev, mesa_shader_stage stage, UNUSED const struct vk_pipeline_robustness_state *rs) { return &agx_nir_options; @@ -112,7 +112,7 @@ hk_get_nir_options(struct vk_physical_device *vk_pdev, gl_shader_stage stage, static struct spirv_to_nir_options hk_get_spirv_options(struct vk_physical_device *vk_pdev, - UNUSED gl_shader_stage stage, + UNUSED mesa_shader_stage stage, const struct vk_pipeline_robustness_state *rs) { return (struct spirv_to_nir_options){ @@ -971,7 +971,7 @@ DERIVE_HASH_TABLE(hk_fast_link_key_vs); DERIVE_HASH_TABLE(hk_fast_link_key_fs); static VkResult -hk_init_link_ht(struct hk_shader *shader, gl_shader_stage sw_stage) +hk_init_link_ht(struct hk_shader *shader, mesa_shader_stage sw_stage) { simple_mtx_init(&shader->linked.lock, mtx_plain); @@ -1064,7 +1064,7 @@ hk_compile_nir(struct hk_device *dev, const VkAllocationCallbacks *pAllocator, nir_shader *nir, VkShaderCreateFlagsEXT shader_flags, const struct vk_pipeline_robustness_state *rs, const union hk_key *key, enum hk_feature_key features, - struct hk_shader *shader, gl_shader_stage sw_stage, bool hw, + struct hk_shader *shader, mesa_shader_stage sw_stage, bool hw, nir_xfb_info *xfb_info, unsigned set_count) { unsigned nr_vbos = 0; @@ -1311,7 +1311,7 @@ hk_compile_shader(struct hk_device *dev, struct vk_shader_compile_info *info, info->set_layouts, features); } - gl_shader_stage sw_stage = nir->info.stage; + mesa_shader_stage sw_stage = nir->info.stage; union hk_key key_tmp, *key = NULL; if (sw_stage == MESA_SHADER_FRAGMENT) { @@ -1640,7 +1640,7 @@ hk_deserialize_api_shader(struct vk_device *vk_dev, struct blob_reader *blob, { struct hk_device *dev = container_of(vk_dev, struct hk_device, vk); - gl_shader_stage stage = blob_read_uint8(blob); + mesa_shader_stage stage = blob_read_uint8(blob); if (blob->overrun) return vk_error(dev, VK_ERROR_INCOMPATIBLE_SHADER_BINARY_EXT); diff --git a/src/asahi/vulkan/hk_shader.h b/src/asahi/vulkan/hk_shader.h index c3f4917e718..836c7fbffaa 100644 --- a/src/asahi/vulkan/hk_shader.h +++ b/src/asahi/vulkan/hk_shader.h @@ -105,7 +105,7 @@ struct hk_shader_info { /* Transform feedback buffer strides */ uint8_t xfb_stride[MAX_XFB_BUFFERS]; - gl_shader_stage stage : 8; + mesa_shader_stage stage : 8; uint8_t clip_distance_array_size; uint8_t cull_distance_array_size; uint8_t set_count; @@ -204,7 +204,7 @@ static const char *hk_gs_variant_name[] = { /* clang-format on */ static inline unsigned -hk_num_variants(gl_shader_stage stage) +hk_num_variants(mesa_shader_stage stage) { switch (stage) { case MESA_SHADER_VERTEX: @@ -365,7 +365,7 @@ void hk_api_shader_destroy(struct vk_device *vk_dev, const VkAllocationCallbacks *pAllocator); const nir_shader_compiler_options * -hk_get_nir_options(struct vk_physical_device *vk_pdev, gl_shader_stage stage, +hk_get_nir_options(struct vk_physical_device *vk_pdev, mesa_shader_stage stage, UNUSED const struct vk_pipeline_robustness_state *rs); struct hk_api_shader *hk_meta_shader(struct hk_device *dev, diff --git a/src/broadcom/common/v3d_debug.c b/src/broadcom/common/v3d_debug.c index cf77ec98393..bb4b42f72ae 100644 --- a/src/broadcom/common/v3d_debug.c +++ b/src/broadcom/common/v3d_debug.c @@ -114,7 +114,7 @@ static const struct debug_named_value debug_control[] = { DEBUG_GET_ONCE_FLAGS_OPTION(v3d_debug, "V3D_DEBUG", debug_control, 0) bool -v3d_debug_flag_for_shader_stage(gl_shader_stage stage) +v3d_debug_flag_for_shader_stage(mesa_shader_stage stage) { uint32_t flags[] = { [MESA_SHADER_VERTEX] = V3D_DEBUG_VS, diff --git a/src/broadcom/common/v3d_debug.h b/src/broadcom/common/v3d_debug.h index 668b1be36bb..d949d278cc0 100644 --- a/src/broadcom/common/v3d_debug.h +++ b/src/broadcom/common/v3d_debug.h @@ -93,7 +93,7 @@ extern uint32_t v3d_mesa_debug; #define dbg_printf(...) fprintf(stderr, __VA_ARGS__) #endif /* HAVE_ANDROID_PLATFORM */ -extern bool v3d_debug_flag_for_shader_stage(gl_shader_stage stage); +extern bool v3d_debug_flag_for_shader_stage(mesa_shader_stage stage); extern void v3d_process_debug_variable(void); diff --git a/src/broadcom/compiler/v3d_compiler.h b/src/broadcom/compiler/v3d_compiler.h index 4c49de7b00e..9770043298f 100644 --- a/src/broadcom/compiler/v3d_compiler.h +++ b/src/broadcom/compiler/v3d_compiler.h @@ -1138,7 +1138,7 @@ uint64_t *v3d_compile(const struct v3d_compiler *compiler, int program_id, int variant_id, uint32_t *final_assembly_size); -uint32_t v3d_prog_data_size(gl_shader_stage stage); +uint32_t v3d_prog_data_size(mesa_shader_stage stage); void v3d_nir_to_vir(struct v3d_compile *c); void vir_compile_destroy(struct v3d_compile *c); diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c index 754981186c9..de88bcecd55 100644 --- a/src/broadcom/compiler/vir.c +++ b/src/broadcom/compiler/vir.c @@ -1828,7 +1828,7 @@ v3d_attempt_compile(struct v3d_compile *c) } uint32_t -v3d_prog_data_size(gl_shader_stage stage) +v3d_prog_data_size(mesa_shader_stage stage) { static const int prog_data_size[] = { [MESA_SHADER_VERTEX] = sizeof(struct v3d_vs_prog_data), diff --git a/src/broadcom/vulkan/v3dv_pipeline.c b/src/broadcom/vulkan/v3dv_pipeline.c index cf67fee4b66..3e81d5e315b 100644 --- a/src/broadcom/vulkan/v3dv_pipeline.c +++ b/src/broadcom/vulkan/v3dv_pipeline.c @@ -373,7 +373,7 @@ shader_module_compile_to_nir(struct v3dv_device *device, const nir_shader_compiler_options *nir_options = v3dv_pipeline_get_nir_options(&device->devinfo); - gl_shader_stage gl_stage = broadcom_shader_stage_to_gl(stage->stage); + mesa_shader_stage gl_stage = broadcom_shader_stage_to_gl(stage->stage); const VkPipelineShaderStageCreateInfo stage_info = { .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, @@ -492,7 +492,7 @@ lower_load_push_constant(nir_builder *b, nir_intrinsic_instr *instr, static struct v3dv_descriptor_map* pipeline_get_descriptor_map(struct v3dv_pipeline *pipeline, VkDescriptorType desc_type, - gl_shader_stage gl_stage, + mesa_shader_stage gl_stage, bool is_sampler) { enum broadcom_shader_stage broadcom_stage = @@ -1688,7 +1688,7 @@ pipeline_compile_shader_variant(struct v3dv_pipeline_stage *p_stage, struct v3dv_pipeline *pipeline = p_stage->pipeline; struct v3dv_physical_device *physical_device = pipeline->device->pdevice; const struct v3d_compiler *compiler = physical_device->compiler; - gl_shader_stage gl_stage = broadcom_shader_stage_to_gl(p_stage->stage); + mesa_shader_stage gl_stage = broadcom_shader_stage_to_gl(p_stage->stage); if (V3D_DBG(NIR) || v3d_debug_flag_for_shader_stage(gl_stage)) { fprintf(stderr, "Just before v3d_compile: %s prog %d NIR:\n", @@ -2214,7 +2214,7 @@ write_creation_feedback(struct v3dv_pipeline *pipeline, assert(feedback_stage_count <= stage_count); for (uint32_t i = 0; i < feedback_stage_count; i++) { - gl_shader_stage s = vk_to_mesa_shader_stage(stages[i].stage); + mesa_shader_stage s = vk_to_mesa_shader_stage(stages[i].stage); enum broadcom_shader_stage bs = gl_shader_stage_to_broadcom(s); create_feedback->pPipelineStageCreationFeedbacks[i] = @@ -2439,7 +2439,7 @@ pipeline_compile_graphics(struct v3dv_pipeline *pipeline, */ for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) { const VkPipelineShaderStageCreateInfo *sinfo = &pCreateInfo->pStages[i]; - gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage); struct v3dv_pipeline_stage *p_stage = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*p_stage), 8, @@ -3187,7 +3187,7 @@ pipeline_compile_compute(struct v3dv_pipeline *pipeline, struct v3dv_physical_device *physical_device = device->pdevice; const VkPipelineShaderStageCreateInfo *sinfo = &info->stage; - gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage); struct v3dv_pipeline_stage *p_stage = vk_zalloc2(&device->vk.alloc, alloc, sizeof(*p_stage), 8, @@ -3594,7 +3594,7 @@ v3dv_GetPipelineExecutablePropertiesKHR( util_dynarray_foreach(&pipeline->executables.data, struct v3dv_pipeline_executable_data, exe) { vk_outarray_append_typed(VkPipelineExecutablePropertiesKHR, &out, props) { - gl_shader_stage mesa_stage = broadcom_shader_stage_to_gl(exe->stage); + mesa_shader_stage mesa_stage = broadcom_shader_stage_to_gl(exe->stage); props->stages = mesa_to_vk_shader_stage(mesa_stage); VK_PRINT_STR(props->name, "%s (%s)", diff --git a/src/broadcom/vulkan/v3dv_private.h b/src/broadcom/vulkan/v3dv_private.h index 053c898f020..74b7820d9d3 100644 --- a/src/broadcom/vulkan/v3dv_private.h +++ b/src/broadcom/vulkan/v3dv_private.h @@ -346,7 +346,7 @@ struct v3dv_pipeline_cache_stats { uint32_t on_disk_hit; }; -/* Equivalent to gl_shader_stage, but including the coordinate shaders +/* Equivalent to mesa_shader_stage, but including the coordinate shaders * * FIXME: perhaps move to common */ @@ -363,7 +363,7 @@ enum broadcom_shader_stage { /* Assumes that coordinate shaders will be custom-handled by the caller */ static inline enum broadcom_shader_stage -gl_shader_stage_to_broadcom(gl_shader_stage stage) +gl_shader_stage_to_broadcom(mesa_shader_stage stage) { switch (stage) { case MESA_SHADER_VERTEX: @@ -379,7 +379,7 @@ gl_shader_stage_to_broadcom(gl_shader_stage stage) } } -static inline gl_shader_stage +static inline mesa_shader_stage broadcom_shader_stage_to_gl(enum broadcom_shader_stage stage) { switch (stage) { diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp index 305ae0ff721..45c13b0e096 100644 --- a/src/compiler/glsl/ast_to_hir.cpp +++ b/src/compiler/glsl/ast_to_hir.cpp @@ -2787,7 +2787,7 @@ ast_fully_specified_type::glsl_type(const char **name, * this function will produce undefined results. */ static bool -is_varying_var(ir_variable *var, gl_shader_stage target) +is_varying_var(ir_variable *var, mesa_shader_stage target) { switch (target) { case MESA_SHADER_VERTEX: diff --git a/src/compiler/glsl/gl_nir_link_uniform_blocks.c b/src/compiler/glsl/gl_nir_link_uniform_blocks.c index 1d7a8c62ded..42801068a5e 100644 --- a/src/compiler/glsl/gl_nir_link_uniform_blocks.c +++ b/src/compiler/glsl/gl_nir_link_uniform_blocks.c @@ -1026,7 +1026,7 @@ fill_block(void *mem_ctx, const struct gl_constants *consts, const char *name, unsigned binding_offset, unsigned linearized_index, struct gl_shader_program *prog, - const gl_shader_stage stage, + const mesa_shader_stage stage, enum block_type block_type) { struct gl_uniform_block *block = &blocks[*block_index]; @@ -1136,7 +1136,7 @@ fill_block_array(struct uniform_block_array_elements *ub_array, struct gl_uniform_buffer_variable *variables, unsigned *variable_index, unsigned binding_offset, struct gl_shader_program *prog, - const gl_shader_stage stage, enum block_type block_type, + const mesa_shader_stage stage, enum block_type block_type, unsigned *block_index, unsigned first_index) { for (unsigned j = 0; j < ub_array->num_array_elements; j++) { diff --git a/src/compiler/glsl/gl_nir_link_uniforms.c b/src/compiler/glsl/gl_nir_link_uniforms.c index 93a048248d5..fa9e37e1cd9 100644 --- a/src/compiler/glsl/gl_nir_link_uniforms.c +++ b/src/compiler/glsl/gl_nir_link_uniforms.c @@ -1306,7 +1306,7 @@ static int nir_link_uniform(const struct gl_constants *consts, struct gl_shader_program *prog, struct gl_program *stage_program, - gl_shader_stage stage, + mesa_shader_stage stage, const struct glsl_type *type, unsigned index_in_parent, int location, diff --git a/src/compiler/glsl/gl_nir_link_varyings.c b/src/compiler/glsl/gl_nir_link_varyings.c index 30b83b6c666..2ac5b373821 100644 --- a/src/compiler/glsl/gl_nir_link_varyings.c +++ b/src/compiler/glsl/gl_nir_link_varyings.c @@ -74,7 +74,7 @@ compare_attr(const void *a, const void *b) * geometry shader inputs). */ static const struct glsl_type * -get_varying_type(const nir_variable *var, gl_shader_stage stage) +get_varying_type(const nir_variable *var, mesa_shader_stage stage) { const struct glsl_type *type = var->type; if (nir_is_arrayed_io(var, stage)) { @@ -147,8 +147,8 @@ cross_validate_types_and_qualifiers(const struct gl_constants *consts, struct gl_shader_program *prog, const nir_variable *input, const nir_variable *output, - gl_shader_stage consumer_stage, - gl_shader_stage producer_stage) + mesa_shader_stage consumer_stage, + mesa_shader_stage producer_stage) { /* Check that the types match between stages. */ @@ -355,8 +355,8 @@ cross_validate_front_and_back_color(const struct gl_constants *consts, const nir_variable *input, const nir_variable *front_color, const nir_variable *back_color, - gl_shader_stage consumer_stage, - gl_shader_stage producer_stage) + mesa_shader_stage consumer_stage, + mesa_shader_stage producer_stage) { if (front_color != NULL && front_color->data.assigned) cross_validate_types_and_qualifiers(consts, prog, input, front_color, @@ -368,7 +368,7 @@ cross_validate_front_and_back_color(const struct gl_constants *consts, } static unsigned -compute_variable_location_slot(nir_variable *var, gl_shader_stage stage) +compute_variable_location_slot(nir_variable *var, mesa_shader_stage stage) { unsigned location_start = VARYING_SLOT_VAR0; @@ -416,7 +416,7 @@ check_location_aliasing(struct explicit_location_info explicit_locations[][4], bool sample, bool patch, struct gl_shader_program *prog, - gl_shader_stage stage) + mesa_shader_stage stage) { unsigned last_comp; unsigned base_type_bit_size; @@ -742,8 +742,8 @@ validate_explicit_variable_location(const struct gl_constants *consts, bool gl_nir_validate_first_and_last_interface_explicit_locations(const struct gl_constants *consts, struct gl_shader_program *prog, - gl_shader_stage first_stage, - gl_shader_stage last_stage) + mesa_shader_stage first_stage, + mesa_shader_stage last_stage) { /* VS inputs and FS outputs are validated in * assign_attribute_or_color_locations() @@ -755,7 +755,7 @@ gl_nir_validate_first_and_last_interface_explicit_locations(const struct gl_cons struct explicit_location_info explicit_locations[MAX_VARYING][4]; - gl_shader_stage stages[2] = { first_stage, last_stage }; + mesa_shader_stage stages[2] = { first_stage, last_stage }; bool validate_stage[2] = { validate_first_stage, validate_last_stage }; nir_variable_mode var_mode[2] = { nir_var_shader_in, nir_var_shader_out }; @@ -763,7 +763,7 @@ gl_nir_validate_first_and_last_interface_explicit_locations(const struct gl_cons if (!validate_stage[i]) continue; - gl_shader_stage stage = stages[i]; + mesa_shader_stage stage = stages[i]; struct gl_linked_shader *sh = prog->_LinkedShaders[stage]; assert(sh); @@ -2449,8 +2449,8 @@ struct varying_matches */ unsigned matches_capacity; - gl_shader_stage producer_stage; - gl_shader_stage consumer_stage; + mesa_shader_stage producer_stage; + mesa_shader_stage consumer_stage; }; /** @@ -2514,8 +2514,8 @@ varying_matches_not_xfb_comparator(const void *x_generic, const void *y_generic) } static bool -is_unpackable_tess(gl_shader_stage producer_stage, - gl_shader_stage consumer_stage) +is_unpackable_tess(mesa_shader_stage producer_stage, + mesa_shader_stage consumer_stage) { if (consumer_stage == MESA_SHADER_TESS_EVAL || consumer_stage == MESA_SHADER_TESS_CTRL || @@ -2529,8 +2529,8 @@ static void init_varying_matches(void *mem_ctx, struct varying_matches *vm, const struct gl_constants *consts, const struct gl_extensions *exts, - gl_shader_stage producer_stage, - gl_shader_stage consumer_stage, + mesa_shader_stage producer_stage, + mesa_shader_stage consumer_stage, bool sso) { /* Tessellation shaders treat inputs and outputs as shared memory and can @@ -3098,7 +3098,7 @@ struct tfeedback_candidate_generator_state { */ struct hash_table *tfeedback_candidates; - gl_shader_stage stage; + mesa_shader_stage stage; /** * Pointer to the toplevel variable that is being traversed. @@ -3895,7 +3895,7 @@ remove_unused_shader_inputs_and_outputs(struct gl_shader_program *prog, static void linker_error_io_limit_exceeded(struct gl_shader_program *prog, gl_api api, - gl_shader_stage stage, unsigned num_comps, + mesa_shader_stage stage, unsigned num_comps, unsigned max_comps, const char *in_or_out_name) { if (api == API_OPENGLES2 || prog->IsES) { diff --git a/src/compiler/glsl/gl_nir_link_varyings.h b/src/compiler/glsl/gl_nir_link_varyings.h index 4cfa7bae8f7..60e9608ef2a 100644 --- a/src/compiler/glsl/gl_nir_link_varyings.h +++ b/src/compiler/glsl/gl_nir_link_varyings.h @@ -229,8 +229,8 @@ gl_assign_attribute_or_color_locations(const struct gl_constants *consts, bool gl_nir_validate_first_and_last_interface_explicit_locations(const struct gl_constants *consts, struct gl_shader_program *prog, - gl_shader_stage first_stage, - gl_shader_stage last_stage); + mesa_shader_stage first_stage, + mesa_shader_stage last_stage); void gl_nir_cross_validate_outputs_to_inputs(const struct gl_constants *consts, diff --git a/src/compiler/glsl/gl_nir_linker.c b/src/compiler/glsl/gl_nir_linker.c index 5889fcbbaf1..1c83b760fba 100644 --- a/src/compiler/glsl/gl_nir_linker.c +++ b/src/compiler/glsl/gl_nir_linker.c @@ -1061,7 +1061,7 @@ nir_build_program_resource_list(const struct gl_constants *consts, continue; GLenum type = - _mesa_shader_stage_to_subroutine_uniform((gl_shader_stage)j); + _mesa_shader_stage_to_subroutine_uniform((mesa_shader_stage)j); /* add shader subroutines */ if (!link_util_add_program_resource(prog, resource_set, type, uniform, 0)) @@ -1130,7 +1130,7 @@ nir_build_program_resource_list(const struct gl_constants *consts, const int i = u_bit_scan(&mask); struct gl_program *p = prog->_LinkedShaders[i]->Program; - GLuint type = _mesa_shader_stage_to_subroutine((gl_shader_stage)i); + GLuint type = _mesa_shader_stage_to_subroutine((mesa_shader_stage)i); for (unsigned j = 0; j < p->sh.NumSubroutineFunctions; j++) { if (!link_util_add_program_resource(prog, resource_set, type, @@ -1282,7 +1282,7 @@ preprocess_shader(const struct pipe_screen *screen, const struct gl_extensions *exts, struct gl_program *prog, struct gl_shader_program *shader_program, - gl_shader_stage stage) + mesa_shader_stage stage) { const struct gl_shader_compiler_options *gl_options = &consts->ShaderCompilerOptions[prog->info.stage]; @@ -3550,7 +3550,7 @@ gl_nir_link_glsl(struct gl_context *ctx, struct gl_shader_program *prog) goto done; } - gl_shader_stage shader_type = prog->Shaders[i]->Stage; + mesa_shader_stage shader_type = prog->Shaders[i]->Stage; shader_list[shader_type][num_shaders[shader_type]] = prog->Shaders[i]; num_shaders[shader_type]++; } @@ -3818,8 +3818,8 @@ gl_nir_link_glsl(struct gl_context *ctx, struct gl_shader_program *prog) * is no cross validation for these. */ if (!gl_nir_validate_first_and_last_interface_explicit_locations(consts, prog, - (gl_shader_stage)first, - (gl_shader_stage)last)) + (mesa_shader_stage)first, + (mesa_shader_stage)last)) goto done; if (prog->SeparateShader) diff --git a/src/compiler/glsl/gl_nir_lower_buffers.c b/src/compiler/glsl/gl_nir_lower_buffers.c index cb782f4278e..82faf840b66 100644 --- a/src/compiler/glsl/gl_nir_lower_buffers.c +++ b/src/compiler/glsl/gl_nir_lower_buffers.c @@ -119,7 +119,7 @@ get_block_array_index(nir_builder *b, nir_deref_instr *deref, static void get_block_index_offset(nir_variable *var, const struct gl_shader_program *shader_program, - gl_shader_stage stage, + mesa_shader_stage stage, unsigned *index, unsigned *offset) { diff --git a/src/compiler/glsl/gl_nir_lower_samplers_as_deref.c b/src/compiler/glsl/gl_nir_lower_samplers_as_deref.c index 74591bfba58..02bdfabae14 100644 --- a/src/compiler/glsl/gl_nir_lower_samplers_as_deref.c +++ b/src/compiler/glsl/gl_nir_lower_samplers_as_deref.c @@ -148,7 +148,7 @@ lower_deref(nir_builder *b, struct lower_samplers_as_deref_state *state, nir_deref_instr *deref) { nir_variable *var = nir_deref_instr_get_variable(deref); - gl_shader_stage stage = state->shader->info.stage; + mesa_shader_stage stage = state->shader->info.stage; if (!(var->data.mode & (nir_var_uniform | nir_var_image)) || var->data.bindless) diff --git a/src/compiler/glsl/glsl_parser_extras.cpp b/src/compiler/glsl/glsl_parser_extras.cpp index 3c086cf8523..23aa6fd760d 100644 --- a/src/compiler/glsl/glsl_parser_extras.cpp +++ b/src/compiler/glsl/glsl_parser_extras.cpp @@ -61,7 +61,7 @@ static const unsigned known_desktop_gl_versions[] = _mesa_glsl_parse_state::_mesa_glsl_parse_state(struct gl_context *_ctx, - gl_shader_stage stage, + mesa_shader_stage stage, void *mem_ctx) : ctx(_ctx), exts(&_ctx->Extensions), consts(&_ctx->Const), api(_ctx->API), cs_input_local_size_specified(false), cs_input_local_size(), diff --git a/src/compiler/glsl/glsl_parser_extras.h b/src/compiler/glsl/glsl_parser_extras.h index 06f66cc1f79..c42cd1e70ea 100644 --- a/src/compiler/glsl/glsl_parser_extras.h +++ b/src/compiler/glsl/glsl_parser_extras.h @@ -81,7 +81,7 @@ extern void _mesa_glsl_error(YYLTYPE *locp, _mesa_glsl_parse_state *state, struct _mesa_glsl_parse_state { - _mesa_glsl_parse_state(struct gl_context *_ctx, gl_shader_stage stage, + _mesa_glsl_parse_state(struct gl_context *_ctx, mesa_shader_stage stage, void *mem_ctx); DECLARE_RZALLOC_CXX_OPERATORS(_mesa_glsl_parse_state); @@ -404,7 +404,7 @@ struct _mesa_glsl_parse_state { /* Bitfield of ir_variable_mode to zero init */ uint32_t zero_init; unsigned gl_version; - gl_shader_stage stage; + mesa_shader_stage stage; /** * Default uniform layout qualifiers tracked during parsing. diff --git a/src/compiler/glsl/lower_vector_derefs.cpp b/src/compiler/glsl/lower_vector_derefs.cpp index bfab9b5587c..ef4dbbffc20 100644 --- a/src/compiler/glsl/lower_vector_derefs.cpp +++ b/src/compiler/glsl/lower_vector_derefs.cpp @@ -32,7 +32,7 @@ namespace { class vector_deref_visitor : public ir_rvalue_enter_visitor { public: - vector_deref_visitor(linear_ctx *linalloc, gl_shader_stage shader_stage) + vector_deref_visitor(linear_ctx *linalloc, mesa_shader_stage shader_stage) : progress(false), shader_stage(shader_stage), factory(&factory_instructions, linalloc) { @@ -46,7 +46,7 @@ public: virtual ir_visitor_status visit_enter(ir_assignment *ir); bool progress; - gl_shader_stage shader_stage; + mesa_shader_stage shader_stage; ir_exec_list factory_instructions; ir_factory factory; }; diff --git a/src/compiler/glsl/serialize.cpp b/src/compiler/glsl/serialize.cpp index a929d6d0a49..0097f405374 100644 --- a/src/compiler/glsl/serialize.cpp +++ b/src/compiler/glsl/serialize.cpp @@ -1234,7 +1234,7 @@ get_shader_info_and_pointer_sizes(size_t *s_info_size, size_t *s_info_ptrs, static void create_linked_shader_and_program(struct gl_context *ctx, - gl_shader_stage stage, + mesa_shader_stage stage, struct gl_shader_program *prog, struct blob_reader *metadata) { @@ -1341,7 +1341,7 @@ deserialize_glsl_program(struct blob_reader *blob, struct gl_context *ctx, unsigned mask = prog->data->linked_stages; while (mask) { const int j = u_bit_scan(&mask); - create_linked_shader_and_program(ctx, (gl_shader_stage) j, prog, + create_linked_shader_and_program(ctx, (mesa_shader_stage) j, prog, blob); } diff --git a/src/compiler/glsl/standalone_scaffolding.cpp b/src/compiler/glsl/standalone_scaffolding.cpp index b243ed1d329..2a8794c4bcc 100644 --- a/src/compiler/glsl/standalone_scaffolding.cpp +++ b/src/compiler/glsl/standalone_scaffolding.cpp @@ -104,7 +104,7 @@ _mesa_shader_debug(struct gl_context *, GLenum, GLuint *, } struct gl_shader * -_mesa_new_shader(GLuint name, gl_shader_stage stage) +_mesa_new_shader(GLuint name, mesa_shader_stage stage) { struct gl_shader *shader; @@ -181,7 +181,7 @@ _mesa_clear_shader_program_data(struct gl_context *ctx, static void -init_gl_program(struct gl_program *prog, bool is_arb_asm, gl_shader_stage stage) +init_gl_program(struct gl_program *prog, bool is_arb_asm, mesa_shader_stage stage) { prog->RefCount = 1; prog->Format = GL_PROGRAM_FORMAT_ASCII_ARB; @@ -190,7 +190,7 @@ init_gl_program(struct gl_program *prog, bool is_arb_asm, gl_shader_stage stage) } static struct gl_program * -standalone_new_program(UNUSED struct gl_context *ctx, gl_shader_stage stage, +standalone_new_program(UNUSED struct gl_context *ctx, mesa_shader_stage stage, UNUSED GLuint id, bool is_arb_asm) { struct gl_program *prog = rzalloc(NULL, struct gl_program); diff --git a/src/compiler/glsl/standalone_scaffolding.h b/src/compiler/glsl/standalone_scaffolding.h index 9d005f5cc3a..818b6beb7dc 100644 --- a/src/compiler/glsl/standalone_scaffolding.h +++ b/src/compiler/glsl/standalone_scaffolding.h @@ -53,7 +53,7 @@ _mesa_reference_program_(struct gl_context *ctx, struct gl_program **ptr, struct gl_program *prog); extern "C" struct gl_shader * -_mesa_new_shader(GLuint name, gl_shader_stage stage); +_mesa_new_shader(GLuint name, mesa_shader_stage stage); extern "C" void _mesa_delete_shader(struct gl_context *ctx, struct gl_shader *sh); @@ -77,7 +77,7 @@ _mesa_program_state_flags(const gl_state_index16 state[STATE_LENGTH]); extern "C" char * _mesa_program_state_string(const gl_state_index16 state[STATE_LENGTH]); -static inline gl_shader_stage +static inline mesa_shader_stage _mesa_shader_enum_to_shader_stage(GLenum v) { switch (v) { diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c index f4684377582..ab9429d5dd9 100644 --- a/src/compiler/nir/nir.c +++ b/src/compiler/nir/nir.c @@ -195,7 +195,7 @@ nir_component_mask_reinterpret(nir_component_mask_t mask, nir_shader * nir_shader_create(void *mem_ctx, - gl_shader_stage stage, + mesa_shader_stage stage, const nir_shader_compiler_options *options, shader_info *si) { @@ -3597,7 +3597,7 @@ nir_instr_xfb_write_mask(nir_intrinsic_instr *instr) * Whether an output slot is consumed by fixed-function logic. */ bool -nir_slot_is_sysval_output(gl_varying_slot slot, gl_shader_stage next_shader) +nir_slot_is_sysval_output(gl_varying_slot slot, mesa_shader_stage next_shader) { switch (next_shader) { case MESA_SHADER_FRAGMENT: @@ -3647,7 +3647,7 @@ nir_slot_is_sysval_output(gl_varying_slot slot, gl_shader_stage next_shader) * Pass MESA_SHADER_NONE if the next shader is unknown. */ bool -nir_slot_is_varying(gl_varying_slot slot, gl_shader_stage next_shader) +nir_slot_is_varying(gl_varying_slot slot, mesa_shader_stage next_shader) { bool unknown = next_shader == MESA_SHADER_NONE; bool exactly_before_fs = next_shader == MESA_SHADER_FRAGMENT || unknown; @@ -3680,7 +3680,7 @@ nir_slot_is_varying(gl_varying_slot slot, gl_shader_stage next_shader) bool nir_slot_is_sysval_output_and_varying(gl_varying_slot slot, - gl_shader_stage next_shader) + mesa_shader_stage next_shader) { return nir_slot_is_sysval_output(slot, next_shader) && nir_slot_is_varying(slot, next_shader); @@ -3691,7 +3691,7 @@ nir_slot_is_sysval_output_and_varying(gl_varying_slot slot, * stage. If the instruction has no other use, it's removed. */ bool -nir_remove_varying(nir_intrinsic_instr *intr, gl_shader_stage next_shader) +nir_remove_varying(nir_intrinsic_instr *intr, mesa_shader_stage next_shader) { nir_io_semantics sem = nir_intrinsic_io_semantics(intr); @@ -3713,7 +3713,7 @@ nir_remove_varying(nir_intrinsic_instr *intr, gl_shader_stage next_shader) * logic. If the instruction has no other use, it's removed. */ bool -nir_remove_sysval_output(nir_intrinsic_instr *intr, gl_shader_stage next_shader) +nir_remove_sysval_output(nir_intrinsic_instr *intr, mesa_shader_stage next_shader) { nir_io_semantics sem = nir_intrinsic_io_semantics(intr); diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 918a740216e..562f1207d24 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -3937,7 +3937,7 @@ void nir_remove_entrypoints(nir_shader *shader); void nir_fixup_is_exported(nir_shader *shader); nir_shader *nir_shader_create(void *mem_ctx, - gl_shader_stage stage, + mesa_shader_stage stage, const nir_shader_compiler_options *options, shader_info *si); @@ -5063,12 +5063,12 @@ nir_opt_varyings_bulk(nir_shader **shaders, uint32_t num_shaders, bool spirv, void (*optimize)(nir_shader *)); bool nir_slot_is_sysval_output(gl_varying_slot slot, - gl_shader_stage next_shader); -bool nir_slot_is_varying(gl_varying_slot slot, gl_shader_stage next_shader); + mesa_shader_stage next_shader); +bool nir_slot_is_varying(gl_varying_slot slot, mesa_shader_stage next_shader); bool nir_slot_is_sysval_output_and_varying(gl_varying_slot slot, - gl_shader_stage next_shader); -bool nir_remove_varying(nir_intrinsic_instr *intr, gl_shader_stage next_shader); -bool nir_remove_sysval_output(nir_intrinsic_instr *intr, gl_shader_stage next_shader); + mesa_shader_stage next_shader); +bool nir_remove_varying(nir_intrinsic_instr *intr, mesa_shader_stage next_shader); +bool nir_remove_sysval_output(nir_intrinsic_instr *intr, mesa_shader_stage next_shader); bool nir_lower_amul(nir_shader *shader, int (*type_size)(const struct glsl_type *, bool)); @@ -5079,7 +5079,7 @@ void nir_sort_variables_by_location(nir_shader *shader, nir_variable_mode mode); void nir_assign_io_var_locations(nir_shader *shader, nir_variable_mode mode, unsigned *size, - gl_shader_stage stage); + mesa_shader_stage stage); bool nir_opt_clip_cull_const(nir_shader *shader); @@ -5318,7 +5318,7 @@ nir_src *nir_get_io_arrayed_index_src(nir_intrinsic_instr *instr); nir_src *nir_get_shader_call_payload_src(nir_intrinsic_instr *call); bool nir_is_output_load(nir_intrinsic_instr *intr); -bool nir_is_arrayed_io(const nir_variable *var, gl_shader_stage stage); +bool nir_is_arrayed_io(const nir_variable *var, mesa_shader_stage stage); bool nir_lower_reg_intrinsics_to_ssa_impl(nir_function_impl *impl); bool nir_lower_reg_intrinsics_to_ssa(nir_shader *shader); diff --git a/src/compiler/nir/nir_builder.c b/src/compiler/nir/nir_builder.c index f9554d7f903..ab76587ee46 100644 --- a/src/compiler/nir/nir_builder.c +++ b/src/compiler/nir/nir_builder.c @@ -31,7 +31,7 @@ #include "nir_serialize.h" nir_builder MUST_CHECK PRINTFLIKE(3, 4) - nir_builder_init_simple_shader(gl_shader_stage stage, + nir_builder_init_simple_shader(mesa_shader_stage stage, const nir_shader_compiler_options *options, const char *name, ...) { diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index 9467bce0a2c..8cacba5a42e 100644 --- a/src/compiler/nir/nir_builder.h +++ b/src/compiler/nir/nir_builder.h @@ -70,7 +70,7 @@ nir_builder_at(nir_cursor cursor) } nir_builder MUST_CHECK PRINTFLIKE(3, 4) - nir_builder_init_simple_shader(gl_shader_stage stage, + nir_builder_init_simple_shader(mesa_shader_stage stage, const nir_shader_compiler_options *options, const char *name, ...); diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index d2c6121eb29..e997e7845fd 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -39,7 +39,7 @@ */ struct divergence_state { - const gl_shader_stage stage; + const mesa_shader_stage stage; nir_shader *shader; nir_function_impl *impl; nir_divergence_options options; @@ -180,7 +180,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state) return false; nir_divergence_options options = state->options; - gl_shader_stage stage = state->stage; + mesa_shader_stage stage = state->stage; bool is_divergent = false; switch (instr->intrinsic) { case nir_intrinsic_shader_clock: @@ -1059,7 +1059,7 @@ nir_variable_is_uniform(nir_shader *shader, nir_variable *var, } nir_divergence_options options = state->options; - gl_shader_stage stage = shader->info.stage; + mesa_shader_stage stage = shader->info.stage; if (stage == MESA_SHADER_FRAGMENT && (options & nir_divergence_single_prim_per_subgroup) && diff --git a/src/compiler/nir/nir_linking_helpers.c b/src/compiler/nir/nir_linking_helpers.c index 74e729768b3..5d1e925e0f1 100644 --- a/src/compiler/nir/nir_linking_helpers.c +++ b/src/compiler/nir/nir_linking_helpers.c @@ -36,7 +36,7 @@ * bitfield corresponding to this variable. */ static uint64_t -get_variable_io_mask(nir_variable *var, gl_shader_stage stage) +get_variable_io_mask(nir_variable *var, mesa_shader_stage stage) { if (var->data.location < 0) return 0; @@ -326,7 +326,7 @@ static void get_unmoveable_components_masks(nir_shader *shader, nir_variable_mode mode, struct assigned_comps *comps, - gl_shader_stage stage, + mesa_shader_stage stage, bool default_to_smooth_interp) { nir_foreach_variable_with_modes_safe(var, shader, mode) { @@ -423,7 +423,7 @@ remap_slots_and_components(nir_shader *shader, nir_variable_mode mode, uint64_t *slots_used, uint64_t *out_slots_read, uint32_t *p_slots_used, uint32_t *p_out_slots_read) { - const gl_shader_stage stage = shader->info.stage; + const mesa_shader_stage stage = shader->info.stage; uint64_t out_slots_read_tmp[2] = { 0 }; uint64_t slots_used_tmp[2] = { 0 }; @@ -1484,7 +1484,7 @@ nir_sort_variables_by_location(nir_shader *shader, nir_variable_mode mode) void nir_assign_io_var_locations(nir_shader *shader, nir_variable_mode mode, - unsigned *size, gl_shader_stage stage) + unsigned *size, mesa_shader_stage stage) { unsigned location = 0; unsigned assigned_locations[VARYING_SLOT_TESS_MAX][2]; diff --git a/src/compiler/nir/nir_lower_clip_cull_distance_array_vars.c b/src/compiler/nir/nir_lower_clip_cull_distance_array_vars.c index 941908b8c06..a65b2dc3aeb 100644 --- a/src/compiler/nir/nir_lower_clip_cull_distance_array_vars.c +++ b/src/compiler/nir/nir_lower_clip_cull_distance_array_vars.c @@ -81,7 +81,7 @@ struct lower_distance_state { /** * Type of shader we are compiling (e.g. MESA_SHADER_VERTEX) */ - gl_shader_stage shader_stage; + mesa_shader_stage shader_stage; const char *in_name; int total_size; int offset; diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c index 6f22483a7fd..523682e49c5 100644 --- a/src/compiler/nir/nir_lower_io.c +++ b/src/compiler/nir/nir_lower_io.c @@ -64,7 +64,7 @@ add_variable_name(struct lower_io_state *state, const char *name) * the vertex index within the primitive. */ bool -nir_is_arrayed_io(const nir_variable *var, gl_shader_stage stage) +nir_is_arrayed_io(const nir_variable *var, mesa_shader_stage stage) { if (var->data.patch || !glsl_type_is_array(var->type)) return false; diff --git a/src/compiler/nir/nir_lower_io_array_vars_to_elements.c b/src/compiler/nir/nir_lower_io_array_vars_to_elements.c index 52ccda56ec2..dfcf0b37205 100644 --- a/src/compiler/nir/nir_lower_io_array_vars_to_elements.c +++ b/src/compiler/nir/nir_lower_io_array_vars_to_elements.c @@ -81,7 +81,7 @@ get_io_offset(nir_builder *b, nir_deref_instr *deref, nir_variable *var, static nir_variable ** get_array_elements(struct hash_table *ht, nir_variable *var, - gl_shader_stage stage) + mesa_shader_stage stage) { nir_variable **elements; struct hash_entry *entry = _mesa_hash_table_search(ht, var); diff --git a/src/compiler/nir/nir_lower_io_indirect_loads.c b/src/compiler/nir/nir_lower_io_indirect_loads.c index 0c95f439f56..00f0a8750ea 100644 --- a/src/compiler/nir/nir_lower_io_indirect_loads.c +++ b/src/compiler/nir/nir_lower_io_indirect_loads.c @@ -74,7 +74,7 @@ get_load_var(nir_intrinsic_instr *intr, lower_io_indir_loads_state *state) } static nir_variable ** -get_load_once_variable(gl_shader_stage stage, nir_intrinsic_instr *intr, +get_load_once_variable(mesa_shader_stage stage, nir_intrinsic_instr *intr, lower_io_indir_loads_state *state) { if (intr->intrinsic == nir_intrinsic_load_interpolated_input) { diff --git a/src/compiler/nir/nir_opt_varyings.c b/src/compiler/nir/nir_opt_varyings.c index 820808238b4..7255baeefe8 100644 --- a/src/compiler/nir/nir_opt_varyings.c +++ b/src/compiler/nir/nir_opt_varyings.c @@ -660,8 +660,8 @@ struct linkage_info { bool always_interpolate_convergent_fs_inputs; bool group_tes_inputs_into_pos_var_groups; - gl_shader_stage producer_stage; - gl_shader_stage consumer_stage; + mesa_shader_stage producer_stage; + mesa_shader_stage consumer_stage; nir_builder producer_builder; nir_builder consumer_builder; unsigned max_varying_expression_cost; diff --git a/src/compiler/nir/nir_precompiled.h b/src/compiler/nir/nir_precompiled.h index 39d5233318d..c94d70a1284 100644 --- a/src/compiler/nir/nir_precompiled.h +++ b/src/compiler/nir/nir_precompiled.h @@ -628,7 +628,7 @@ nir_precomp_print_target_binary_map(FILE *fp_c, FILE *fp_h, const char *prefix, static inline nir_shader * nir_precompiled_build_variant(const nir_function *libfunc, - gl_shader_stage stage, unsigned variant, + mesa_shader_stage stage, unsigned variant, const nir_shader_compiler_options *opts, const struct nir_precomp_opts *precomp_opt, nir_def *(*load_arg)(nir_builder *b, diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index ad68014a882..a93eaab8a9b 100644 --- a/src/compiler/nir/nir_print.c +++ b/src/compiler/nir/nir_print.c @@ -776,7 +776,7 @@ get_variable_mode_str(nir_variable_mode mode, bool want_local_global_mode) } static const char * -get_location_str(unsigned location, gl_shader_stage stage, +get_location_str(unsigned location, mesa_shader_stage stage, nir_variable_mode mode, char *buf) { switch (stage) { diff --git a/src/compiler/nir/tests/nir_opt_varyings_test.h b/src/compiler/nir/tests/nir_opt_varyings_test.h index 672bda10cef..1e6020ac6f4 100644 --- a/src/compiler/nir/tests/nir_opt_varyings_test.h +++ b/src/compiler/nir/tests/nir_opt_varyings_test.h @@ -76,8 +76,8 @@ protected: return UINT_MAX; } - void create_shaders(gl_shader_stage producer_stage, - gl_shader_stage consumer_stage) + void create_shaders(mesa_shader_stage producer_stage, + mesa_shader_stage consumer_stage) { _producer_builder = nir_builder_init_simple_shader(producer_stage, &options, diff --git a/src/compiler/nir/tests/nir_test.h b/src/compiler/nir/tests/nir_test.h index f7160affd04..94de496e142 100644 --- a/src/compiler/nir/tests/nir_test.h +++ b/src/compiler/nir/tests/nir_test.h @@ -25,7 +25,7 @@ class nir_test : public ::testing::Test { { } - nir_test(const char *name, gl_shader_stage stage) + nir_test(const char *name, mesa_shader_stage stage) { glsl_type_singleton_init_or_ref(); diff --git a/src/compiler/rust/meson.build b/src/compiler/rust/meson.build index b50ea756cd0..4880872ce22 100644 --- a/src/compiler/rust/meson.build +++ b/src/compiler/rust/meson.build @@ -19,7 +19,7 @@ _compiler_binding_types = [ 'gl_access_qualifier', 'gl_frag_result', 'gl_interp_mode', - 'gl_shader_stage', + 'mesa_shader_stage', 'gl_subgroup_size', 'gl_system_value', 'gl_tess_spacing', diff --git a/src/compiler/shader_enums.c b/src/compiler/shader_enums.c index bac1b92d52a..6e63d6f3d03 100644 --- a/src/compiler/shader_enums.c +++ b/src/compiler/shader_enums.c @@ -34,7 +34,7 @@ #define NAME(val) ((((val) < ARRAY_SIZE(names)) && names[(val)]) ? names[(val)] : "UNKNOWN") const char * -gl_shader_stage_name(gl_shader_stage stage) +gl_shader_stage_name(mesa_shader_stage stage) { static const char *names[] = { ENUM(MESA_SHADER_VERTEX), @@ -58,7 +58,7 @@ gl_shader_stage_name(gl_shader_stage stage) } /** - * Translate a gl_shader_stage to a short shader stage name for debug + * Translate a mesa_shader_stage to a short shader stage name for debug * printouts and error messages. */ const char * @@ -86,7 +86,7 @@ _mesa_shader_stage_to_string(unsigned stage) } /** - * Translate a gl_shader_stage to a shader stage abbreviation (VS, GS, FS) + * Translate a mesa_shader_stage to a shader stage abbreviation (VS, GS, FS) * for debug printouts and error messages. */ const char * @@ -155,7 +155,7 @@ gl_vert_attrib_name(gl_vert_attrib attrib) } const char * -gl_varying_slot_name_for_stage(gl_varying_slot slot, gl_shader_stage stage) +gl_varying_slot_name_for_stage(gl_varying_slot slot, mesa_shader_stage stage) { if (stage != MESA_SHADER_FRAGMENT && slot == VARYING_SLOT_PRIMITIVE_SHADING_RATE) return "VARYING_SLOT_PRIMITIVE_SHADING_RATE"; diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h index aebb8fb9f89..bb9c8180d51 100644 --- a/src/compiler/shader_enums.h +++ b/src/compiler/shader_enums.h @@ -82,23 +82,23 @@ typedef enum pipe_shader_type /* must be last so it doesn't affect the GL pipeline */ MESA_SHADER_KERNEL = 14, -} gl_shader_stage; +} mesa_shader_stage; static inline bool -gl_shader_stage_is_compute(gl_shader_stage stage) +gl_shader_stage_is_compute(mesa_shader_stage stage) { return stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL; } static inline bool -gl_shader_stage_is_mesh(gl_shader_stage stage) +gl_shader_stage_is_mesh(mesa_shader_stage stage) { return stage == MESA_SHADER_TASK || stage == MESA_SHADER_MESH; } static inline bool -gl_shader_stage_is_graphics(gl_shader_stage stage) +gl_shader_stage_is_graphics(mesa_shader_stage stage) { switch (stage) { case MESA_SHADER_VERTEX: @@ -115,7 +115,7 @@ gl_shader_stage_is_graphics(gl_shader_stage stage) } static inline bool -gl_shader_stage_uses_workgroup(gl_shader_stage stage) +gl_shader_stage_uses_workgroup(mesa_shader_stage stage) { return stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL || @@ -124,7 +124,7 @@ gl_shader_stage_uses_workgroup(gl_shader_stage stage) } static inline bool -gl_shader_stage_is_callable(gl_shader_stage stage) +gl_shader_stage_is_callable(mesa_shader_stage stage) { return stage == MESA_SHADER_ANY_HIT || stage == MESA_SHADER_CLOSEST_HIT || @@ -134,13 +134,13 @@ gl_shader_stage_is_callable(gl_shader_stage stage) } static inline bool -gl_shader_stage_is_rt(gl_shader_stage stage) +gl_shader_stage_is_rt(mesa_shader_stage stage) { return stage == MESA_SHADER_RAYGEN || gl_shader_stage_is_callable(stage); } static inline bool -gl_shader_stage_can_set_fragment_shading_rate(gl_shader_stage stage) +gl_shader_stage_can_set_fragment_shading_rate(mesa_shader_stage stage) { /* According to EXT_fragment_shading_rate : * @@ -160,16 +160,16 @@ gl_shader_stage_can_set_fragment_shading_rate(gl_shader_stage stage) typedef short gl_state_index16; /* see enum gl_state_index */ -const char *gl_shader_stage_name(gl_shader_stage stage); +const char *gl_shader_stage_name(mesa_shader_stage stage); /** - * Translate a gl_shader_stage to a short shader stage name for debug + * Translate a mesa_shader_stage to a short shader stage name for debug * printouts and error messages. */ const char *_mesa_shader_stage_to_string(unsigned stage); /** - * Translate a gl_shader_stage to a shader stage abbreviation (VS, GS, FS) + * Translate a mesa_shader_stage to a shader stage abbreviation (VS, GS, FS) * for debug printouts and error messages. */ const char *_mesa_shader_stage_to_abbrev(unsigned stage); @@ -485,7 +485,7 @@ typedef enum #define MAX_VARYINGS_INCL_PATCH (VARYING_SLOT_TESS_MAX - VARYING_SLOT_VAR0) const char *gl_varying_slot_name_for_stage(gl_varying_slot slot, - gl_shader_stage stage); + mesa_shader_stage stage); /** * Determine if the given gl_varying_slot appears in the fragment shader. diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index 03b33c1a257..ccac90e0354 100644 --- a/src/compiler/shader_info.h +++ b/src/compiler/shader_info.h @@ -50,13 +50,13 @@ typedef struct shader_info { blake3_hash source_blake3; /** The shader stage, such as MESA_SHADER_VERTEX. */ - gl_shader_stage stage:8; + mesa_shader_stage stage:8; /* If the shader is linked, this is the previous shader, else MESA_SHADER_NONE. */ - gl_shader_stage prev_stage:8; + mesa_shader_stage prev_stage:8; /* If the shader is linked, this is the next shader, else MESA_SHADER_NONE. */ - gl_shader_stage next_stage:8; + mesa_shader_stage next_stage:8; /* Whether the previous stage has XFB if the shader is linked (prev_stage != NONE). */ bool prev_stage_has_xfb; diff --git a/src/compiler/spirv/gl_spirv.c b/src/compiler/spirv/gl_spirv.c index 99a4fb8e06d..c4dccf07f27 100644 --- a/src/compiler/spirv/gl_spirv.c +++ b/src/compiler/spirv/gl_spirv.c @@ -230,7 +230,7 @@ enum spirv_verify_result spirv_verify_gl_specialization_constants( const uint32_t *words, size_t word_count, struct nir_spirv_specialization *spec, unsigned num_spec, - gl_shader_stage stage, const char *entry_point_name) + mesa_shader_stage stage, const char *entry_point_name) { /* vtn_warn/vtn_log uses debug.func. Setting a null to prevent crash. Not * need to print the warnings now, would be done later, on the real diff --git a/src/compiler/spirv/nir_spirv.h b/src/compiler/spirv/nir_spirv.h index 16b8a681af5..6177ad892f0 100644 --- a/src/compiler/spirv/nir_spirv.h +++ b/src/compiler/spirv/nir_spirv.h @@ -164,12 +164,12 @@ enum spirv_verify_result { enum spirv_verify_result spirv_verify_gl_specialization_constants( const uint32_t *words, size_t word_count, struct nir_spirv_specialization *spec, unsigned num_spec, - gl_shader_stage stage, const char *entry_point_name); + mesa_shader_stage stage, const char *entry_point_name); nir_shader *spirv_to_nir(const uint32_t *words, size_t word_count, struct nir_spirv_specialization *specializations, unsigned num_specializations, - gl_shader_stage stage, const char *entry_point_name, + mesa_shader_stage stage, const char *entry_point_name, const struct spirv_to_nir_options *options, const nir_shader_compiler_options *nir_options); diff --git a/src/compiler/spirv/spirv2nir.c b/src/compiler/spirv/spirv2nir.c index 9301139e905..200a60133ce 100644 --- a/src/compiler/spirv/spirv2nir.c +++ b/src/compiler/spirv/spirv2nir.c @@ -46,7 +46,7 @@ struct { const char *name; - gl_shader_stage stage; + mesa_shader_stage stage; } abbrev_stage_table[] = { { "vs", MESA_SHADER_VERTEX }, { "tcs", MESA_SHADER_TESS_CTRL }, @@ -68,7 +68,7 @@ struct { { "kernel", MESA_SHADER_KERNEL }, }; -static gl_shader_stage +static mesa_shader_stage abbrev_to_stage(const char *name) { for (unsigned i = 0; i < ARRAY_SIZE(abbrev_stage_table); i++) { @@ -79,7 +79,7 @@ abbrev_to_stage(const char *name) } static const char * -stage_to_abbrev(gl_shader_stage stage) +stage_to_abbrev(mesa_shader_stage stage) { for (unsigned i = 0; i < ARRAY_SIZE(abbrev_stage_table); i++) { if (abbrev_stage_table[i].stage == stage) @@ -111,7 +111,7 @@ print_usage(char *exec_name, FILE *f) struct entry_point { const char *name; - gl_shader_stage stage; + mesa_shader_stage stage; }; static struct entry_point @@ -139,7 +139,7 @@ select_entry_point(void *mem_ctx, const uint32_t *words, size_t word_count, unsigned name_words; const char *name = vtn_string_literal(b, &w[3], count - 3, &name_words); - gl_shader_stage stage = vtn_stage_for_execution_model(w[1]); + mesa_shader_stage stage = vtn_stage_for_execution_model(w[1]); struct entry_point e = { name, stage }; util_dynarray_append(&candidates, struct entry_point, e); @@ -214,7 +214,7 @@ int main(int argc, char **argv) print_usage(argv[0], stdout); return 0; case 's': { - gl_shader_stage s = abbrev_to_stage(optarg); + mesa_shader_stage s = abbrev_to_stage(optarg); if (s == MESA_SHADER_NONE) { fprintf(stderr, "Unknown stage \"%s\"\n", optarg); print_usage(argv[0], stderr); diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 612cf539fb9..8310f55d8dd 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -5081,7 +5081,7 @@ vertices_in_from_spv_execution_mode(struct vtn_builder *b, } } -gl_shader_stage +mesa_shader_stage vtn_stage_for_execution_model(SpvExecutionModel model) { switch (model) { @@ -5132,7 +5132,7 @@ vtn_handle_entry_point(struct vtn_builder *b, const uint32_t *w, entry_point->name = vtn_string_literal(b, &w[3], count - 3, &name_words); entry_point->is_entrypoint = true; - gl_shader_stage stage = vtn_stage_for_execution_model(w[1]); + mesa_shader_stage stage = vtn_stage_for_execution_model(w[1]); vtn_fail_if(stage == MESA_SHADER_NONE, "Unsupported execution model: %s (%u)", spirv_executionmodel_to_string(w[1]), w[1]); @@ -6952,7 +6952,7 @@ is_glslang(const struct vtn_builder *b) struct vtn_builder* vtn_create_builder(const uint32_t *words, size_t word_count, - gl_shader_stage stage, const char *entry_point_name, + mesa_shader_stage stage, const char *entry_point_name, const struct spirv_to_nir_options *options) { /* Initialize the vtn_builder object */ @@ -7197,7 +7197,7 @@ can_remove(nir_variable *var, void *data) nir_shader * spirv_to_nir(const uint32_t *words, size_t word_count, struct nir_spirv_specialization *spec, unsigned num_spec, - gl_shader_stage stage, const char *entry_point_name, + mesa_shader_stage stage, const char *entry_point_name, const struct spirv_to_nir_options *options, const nir_shader_compiler_options *nir_options) diff --git a/src/compiler/spirv/tests/helpers.h b/src/compiler/spirv/tests/helpers.h index 1ebf9af7f73..5eb1b48cafd 100644 --- a/src/compiler/spirv/tests/helpers.h +++ b/src/compiler/spirv/tests/helpers.h @@ -60,7 +60,7 @@ protected: glsl_type_singleton_decref(); } - void get_nir(size_t num_words, const uint32_t *words, gl_shader_stage stage = MESA_SHADER_COMPUTE) + void get_nir(size_t num_words, const uint32_t *words, mesa_shader_stage stage = MESA_SHADER_COMPUTE) { shader = spirv_to_nir(words, num_words, NULL, 0, stage, "main", &spirv_options, &nir_options); diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h index 00e3744185d..bdb8d0af1c4 100644 --- a/src/compiler/spirv/vtn_private.h +++ b/src/compiler/spirv/vtn_private.h @@ -690,7 +690,7 @@ struct vtn_builder { /* Workaround discard bugs in HLSL -> SPIR-V compilers */ bool convert_discard_to_demote; - gl_shader_stage entry_point_stage; + mesa_shader_stage entry_point_stage; const char *entry_point_name; struct vtn_value *entry_point; struct vtn_value *workgroup_size_builtin; @@ -1003,7 +1003,7 @@ bool vtn_handle_opencl_core_instruction(struct vtn_builder *b, SpvOp opcode, const uint32_t *w, unsigned count); struct vtn_builder* vtn_create_builder(const uint32_t *words, size_t word_count, - gl_shader_stage stage, const char *entry_point_name, + mesa_shader_stage stage, const char *entry_point_name, const struct spirv_to_nir_options *options); void vtn_handle_entry_point(struct vtn_builder *b, const uint32_t *w, @@ -1106,6 +1106,6 @@ struct vtn_ssa_value *vtn_cooperative_matrix_insert(struct vtn_builder *b, struc nir_deref_instr *vtn_create_cmat_temporary(struct vtn_builder *b, const struct glsl_type *t, const char *name); -gl_shader_stage vtn_stage_for_execution_model(SpvExecutionModel model); +mesa_shader_stage vtn_stage_for_execution_model(SpvExecutionModel model); #endif /* _VTN_PRIVATE_H_ */ diff --git a/src/freedreno/common/disasm.h b/src/freedreno/common/disasm.h index d8e60d167e8..0b6d237a22d 100644 --- a/src/freedreno/common/disasm.h +++ b/src/freedreno/common/disasm.h @@ -36,7 +36,7 @@ struct shader_stats { }; int disasm_a2xx(uint32_t *dwords, int sizedwords, int level, - gl_shader_stage type); + mesa_shader_stage type); int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id); int disasm_a3xx_stat(uint32_t *dwords, int sizedwords, int level, FILE *out, diff --git a/src/freedreno/decode/cffdec.c b/src/freedreno/decode/cffdec.c index 8e3d330899d..131c4308798 100644 --- a/src/freedreno/decode/cffdec.c +++ b/src/freedreno/decode/cffdec.c @@ -1209,7 +1209,7 @@ cp_im_loadi(uint32_t *dwords, uint32_t sizedwords, int level) uint32_t start = dwords[1] >> 16; uint32_t size = dwords[1] & 0xffff; const char *type = NULL, *ext = NULL; - gl_shader_stage disasm_type; + mesa_shader_stage disasm_type; switch (dwords[0]) { case 0: @@ -1286,13 +1286,13 @@ enum adreno_state_block { */ static void -a3xx_get_state_type(uint32_t *dwords, gl_shader_stage *stage, +a3xx_get_state_type(uint32_t *dwords, mesa_shader_stage *stage, enum state_t *state, enum state_src_t *src) { unsigned state_block_id = (dwords[0] >> 19) & 0x7; unsigned state_type = dwords[1] & 0x3; static const struct { - gl_shader_stage stage; + mesa_shader_stage stage; enum state_t state; } lookup[0xf][0x3] = { [SB_VERT_TEX][0] = {MESA_SHADER_VERTEX, TEX_SAMP}, @@ -1331,10 +1331,10 @@ _get_state_src(unsigned dword0) static void _get_state_type(unsigned state_block_id, unsigned state_type, - gl_shader_stage *stage, enum state_t *state) + mesa_shader_stage *stage, enum state_t *state) { static const struct { - gl_shader_stage stage; + mesa_shader_stage stage; enum state_t state; } lookup[0x10][0x4] = { // SB4_VS_TEX: @@ -1407,7 +1407,7 @@ _get_state_type(unsigned state_block_id, unsigned state_type, } static void -a4xx_get_state_type(uint32_t *dwords, gl_shader_stage *stage, +a4xx_get_state_type(uint32_t *dwords, mesa_shader_stage *stage, enum state_t *state, enum state_src_t *src) { unsigned state_block_id = (dwords[0] >> 18) & 0xf; @@ -1417,7 +1417,7 @@ a4xx_get_state_type(uint32_t *dwords, gl_shader_stage *stage, } static void -a6xx_get_state_type(uint32_t *dwords, gl_shader_stage *stage, +a6xx_get_state_type(uint32_t *dwords, mesa_shader_stage *stage, enum state_t *state, enum state_src_t *src) { unsigned state_block_id = (dwords[0] >> 18) & 0xf; @@ -1568,7 +1568,7 @@ dump_bindless_descriptors(bool is_compute, int level) static void cp_load_state(uint32_t *dwords, uint32_t sizedwords, int level) { - gl_shader_stage stage; + mesa_shader_stage stage; enum state_t state; enum state_src_t src; uint32_t num_unit = (dwords[0] >> 22) & 0x1ff; diff --git a/src/freedreno/decode/pgmdump.c b/src/freedreno/decode/pgmdump.c index 0f761cac0e3..f557cef96f0 100644 --- a/src/freedreno/decode/pgmdump.c +++ b/src/freedreno/decode/pgmdump.c @@ -1000,7 +1000,7 @@ main(int argc, char **argv) /* figure out what sort of input we are dealing with: */ if (!(check_extension(infile, ".rd") || check_extension(infile, ".rd.gz"))) { - gl_shader_stage shader = ~0; + mesa_shader_stage shader = ~0; int ret; if (check_extension(infile, ".vo")) { shader = MESA_SHADER_VERTEX; diff --git a/src/freedreno/ir2/disasm-a2xx.c b/src/freedreno/ir2/disasm-a2xx.c index 5e30b0abe70..9a750aba733 100644 --- a/src/freedreno/ir2/disasm-a2xx.c +++ b/src/freedreno/ir2/disasm-a2xx.c @@ -87,7 +87,7 @@ print_dstreg(uint32_t num, uint32_t mask, uint32_t dst_exp) } static void -print_export_comment(uint32_t num, gl_shader_stage type) +print_export_comment(uint32_t num, mesa_shader_stage type) { const char *name = NULL; switch (type) { @@ -210,7 +210,7 @@ struct { static int disasm_alu(uint32_t *dwords, uint32_t alu_off, int level, int sync, - gl_shader_stage type) + mesa_shader_stage type) { instr_alu_t *alu = (instr_alu_t *)dwords; @@ -600,7 +600,7 @@ print_cf(instr_cf_t *cf, int level) */ int -disasm_a2xx(uint32_t *dwords, int sizedwords, int level, gl_shader_stage type) +disasm_a2xx(uint32_t *dwords, int sizedwords, int level, mesa_shader_stage type) { instr_cf_t *cfs = (instr_cf_t *)dwords; int idx, max_idx; diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h index ba548f4ced4..035b2387034 100644 --- a/src/freedreno/ir3/ir3.h +++ b/src/freedreno/ir3/ir3.h @@ -619,7 +619,7 @@ struct ir3_instruction_rpt { struct ir3 { struct ir3_compiler *compiler; - gl_shader_stage type; + mesa_shader_stage type; DECLARE_ARRAY(struct ir3_instruction *, inputs); diff --git a/src/freedreno/ir3/ir3_compiler.h b/src/freedreno/ir3/ir3_compiler.h index b552055c372..226073c2a3c 100644 --- a/src/freedreno/ir3/ir3_compiler.h +++ b/src/freedreno/ir3/ir3_compiler.h @@ -393,7 +393,7 @@ extern enum ir3_shader_debug ir3_shader_debug; extern const char *ir3_shader_override_path; static inline bool -shader_debug_enabled(gl_shader_stage type, bool internal) +shader_debug_enabled(mesa_shader_stage type, bool internal) { if (internal) return !!(ir3_shader_debug & IR3_DBG_SHADER_INTERNAL); diff --git a/src/freedreno/ir3/ir3_legalize.c b/src/freedreno/ir3/ir3_legalize.c index ef5a1897fda..98f6049ec3d 100644 --- a/src/freedreno/ir3/ir3_legalize.c +++ b/src/freedreno/ir3/ir3_legalize.c @@ -30,7 +30,7 @@ struct ir3_legalize_ctx { struct ir3_compiler *compiler; struct ir3_shader_variant *so; - gl_shader_stage type; + mesa_shader_stage type; int max_bary; bool early_input_release; bool has_inputs; @@ -427,7 +427,7 @@ ir3_merge_pred_legalize_states(struct ir3_legalize_state *state, &pstate->needs_ss_or_sy_scalar_war); } - gl_shader_stage stage = block->shader->type; + mesa_shader_stage stage = block->shader->type; if (stage == MESA_SHADER_TESS_CTRL || stage == MESA_SHADER_GEOMETRY) { if (block == ir3_start_block(block->shader)) { diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c index 905eff1a69a..542b89f793c 100644 --- a/src/freedreno/ir3/ir3_nir.c +++ b/src/freedreno/ir3/ir3_nir.c @@ -968,7 +968,7 @@ lower_ucp_vs(struct ir3_shader_variant *so) if (!so->key.ucp_enables) return false; - gl_shader_stage last_geom_stage; + mesa_shader_stage last_geom_stage; if (so->key.has_gs) { last_geom_stage = MESA_SHADER_GEOMETRY; @@ -1508,7 +1508,7 @@ void ir3_alloc_driver_params(struct ir3_const_allocations *const_alloc, uint32_t *num_driver_params, struct ir3_compiler *compiler, - gl_shader_stage shader_stage) + mesa_shader_stage shader_stage) { if (*num_driver_params == 0) return; diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c index 1a319aa0bea..dbb4cea9d9c 100644 --- a/src/freedreno/ir3/ir3_ra.c +++ b/src/freedreno/ir3/ir3_ra.c @@ -348,7 +348,7 @@ struct ra_ctx { struct ir3_block *block; const struct ir3_compiler *compiler; - gl_shader_stage stage; + mesa_shader_stage stage; /* Pending moves of top-level intervals that will be emitted once we're * finished: diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c index 6b8f5e3b53c..31523f89b2e 100644 --- a/src/freedreno/ir3/ir3_shader.c +++ b/src/freedreno/ir3/ir3_shader.c @@ -1257,7 +1257,7 @@ ir3_shader_outputs(const struct ir3_shader *so) void ir3_shader_get_subgroup_size(const struct ir3_compiler *compiler, const struct ir3_shader_options *options, - gl_shader_stage stage, unsigned *subgroup_size, + mesa_shader_stage stage, unsigned *subgroup_size, unsigned *max_subgroup_size) { switch (options->api_wavesize) { diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h index 3ee2f8d6aaa..229f455ea72 100644 --- a/src/freedreno/ir3/ir3_shader.h +++ b/src/freedreno/ir3/ir3_shader.h @@ -652,7 +652,7 @@ struct ir3_shader_variant { struct ir3_shader_variant *next; /* replicated here to avoid passing extra ptrs everywhere: */ - gl_shader_stage type; + mesa_shader_stage type; struct ir3_compiler *compiler; char *name; @@ -992,7 +992,7 @@ ir3_has_binning_vs(const struct ir3_shader_key *key) * generated. */ struct ir3_shader { - gl_shader_stage type; + mesa_shader_stage type; /* shader id (for debug): */ uint32_t id; @@ -1191,7 +1191,7 @@ int ir3_glsl_type_size(const struct glsl_type *type, bool bindless); void ir3_shader_get_subgroup_size(const struct ir3_compiler *compiler, const struct ir3_shader_options *options, - gl_shader_stage stage, + mesa_shader_stage stage, unsigned *subgroup_size, unsigned *max_subgroup_size); diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index 4a972e2f230..1d867e8a57d 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -5942,7 +5942,7 @@ TU_GENX(tu_CmdNextSubpass2); static uint32_t tu6_user_consts_size(const struct tu_const_state *const_state, bool ldgk, - gl_shader_stage type) + mesa_shader_stage type) { uint32_t dwords = 0; @@ -5965,7 +5965,7 @@ static void tu6_emit_per_stage_push_consts(struct tu_cs *cs, const struct tu_const_state *const_state, const struct ir3_const_state *ir_const_state, - gl_shader_stage type, + mesa_shader_stage type, uint32_t *push_constants) { if (const_state->push_consts.type == IR3_PUSH_CONSTS_PER_STAGE) { @@ -5995,7 +5995,7 @@ static void tu6_emit_inline_ubo(struct tu_cs *cs, const struct tu_const_state *const_state, unsigned constlen, - gl_shader_stage type, + mesa_shader_stage type, struct tu_descriptor_state *descriptors) { assert(const_state->num_inline_ubos == 0 || !cs->device->physical_device->info->a7xx.load_shader_consts_via_preamble); @@ -6034,7 +6034,7 @@ tu7_emit_inline_ubo(struct tu_cs *cs, const struct tu_const_state *const_state, const struct ir3_const_state *ir_const_state, unsigned constlen, - gl_shader_stage type, + mesa_shader_stage type, struct tu_descriptor_state *descriptors) { uint64_t addresses[7] = {0}; @@ -6070,7 +6070,7 @@ tu_emit_inline_ubo(struct tu_cs *cs, const struct tu_const_state *const_state, const struct ir3_const_state *ir_const_state, unsigned constlen, - gl_shader_stage type, + mesa_shader_stage type, struct tu_descriptor_state *descriptors) { if (!const_state->num_inline_ubos) @@ -6142,7 +6142,7 @@ tu6_const_size(struct tu_cmd_buffer *cmd, tu6_user_consts_size(&cmd->state.shaders[MESA_SHADER_COMPUTE]->const_state, ldgk, MESA_SHADER_COMPUTE); } else { for (uint32_t type = MESA_SHADER_VERTEX; type <= MESA_SHADER_FRAGMENT; type++) - dwords += tu6_user_consts_size(&cmd->state.shaders[type]->const_state, ldgk, (gl_shader_stage) type); + dwords += tu6_user_consts_size(&cmd->state.shaders[type]->const_state, ldgk, (mesa_shader_stage) type); } return dwords; @@ -6189,11 +6189,11 @@ tu_emit_consts(struct tu_cmd_buffer *cmd, bool compute) &cmd->state.program.link[type]; tu6_emit_per_stage_push_consts(&cs, &link->tu_const_state, &link->const_state, - (gl_shader_stage) type, + (mesa_shader_stage) type, cmd->push_constants); tu_emit_inline_ubo(&cs, &link->tu_const_state, &link->const_state, link->constlen, - (gl_shader_stage) type, descriptors); + (mesa_shader_stage) type, descriptors); } } @@ -7446,7 +7446,7 @@ tu_emit_compute_driver_params(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const struct tu_dispatch_info *info) { - gl_shader_stage type = MESA_SHADER_COMPUTE; + mesa_shader_stage type = MESA_SHADER_COMPUTE; const struct tu_shader *shader = cmd->state.shaders[MESA_SHADER_COMPUTE]; const struct ir3_shader_variant *variant = shader->variant; const struct ir3_const_state *const_state = variant->const_state; diff --git a/src/freedreno/vulkan/tu_pipeline.cc b/src/freedreno/vulkan/tu_pipeline.cc index c22d9c70d67..d3c73aee928 100644 --- a/src/freedreno/vulkan/tu_pipeline.cc +++ b/src/freedreno/vulkan/tu_pipeline.cc @@ -375,7 +375,7 @@ static const xs_config xs_configs[] = { template void tu6_emit_xs_config(struct tu_cs *cs, - gl_shader_stage stage, /* xs->type, but xs may be NULL */ + mesa_shader_stage stage, /* xs->type, but xs may be NULL */ const struct ir3_shader_variant *xs) { const struct xs_config *cfg = &xs_configs[stage]; @@ -1293,13 +1293,13 @@ tu6_emit_program_config(struct tu_cs *cs, .gfx_shared_const = shared_consts_enable)); for (size_t stage_idx = MESA_SHADER_VERTEX; stage_idx <= MESA_SHADER_FRAGMENT; stage_idx++) { - gl_shader_stage stage = (gl_shader_stage) stage_idx; + mesa_shader_stage stage = (mesa_shader_stage) stage_idx; tu6_emit_xs_config(cs, stage, variants[stage]); } for (size_t stage_idx = MESA_SHADER_VERTEX; stage_idx <= MESA_SHADER_FRAGMENT; stage_idx++) { - gl_shader_stage stage = (gl_shader_stage) stage_idx; + mesa_shader_stage stage = (mesa_shader_stage) stage_idx; tu6_emit_dynamic_offset(cs, variants[stage], shaders[stage], prog); } @@ -1692,7 +1692,7 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder, if (!(builder->active_stages & builder->create_info->pStages[i].stage)) continue; - gl_shader_stage stage = + mesa_shader_stage stage = vk_to_mesa_shader_stage(builder->create_info->pStages[i].stage); stage_infos[stage] = &builder->create_info->pStages[i]; must_compile = true; @@ -1706,8 +1706,8 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder, bool cache_hit = false; struct tu_shader_key keys[ARRAY_SIZE(stage_infos)] = { }; - for (gl_shader_stage stage = MESA_SHADER_VERTEX; - stage < ARRAY_SIZE(keys); stage = (gl_shader_stage) (stage+1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; + stage < ARRAY_SIZE(keys); stage = (mesa_shader_stage) (stage+1)) { const VkPipelineShaderStageRequiredSubgroupSizeCreateInfo *subgroup_info = NULL; if (stage_infos[stage]) subgroup_info = vk_find_struct_const(stage_infos[stage], @@ -1802,10 +1802,10 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder, keys[MESA_SHADER_VERTEX].multiview_mask = builder->graphics_state.rp->view_mask; - gl_shader_stage last_pre_rast_stage = MESA_SHADER_VERTEX; + mesa_shader_stage last_pre_rast_stage = MESA_SHADER_VERTEX; for (int i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) { if (nir[i]) { - last_pre_rast_stage = (gl_shader_stage)i; + last_pre_rast_stage = (mesa_shader_stage)i; break; } } @@ -1870,8 +1870,8 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder, unsigned char shader_sha1[21]; memcpy(shader_sha1, pipeline_sha1, sizeof(pipeline_sha1)); - for (gl_shader_stage stage = MESA_SHADER_VERTEX; stage < ARRAY_SIZE(nir); - stage = (gl_shader_stage) (stage + 1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < ARRAY_SIZE(nir); + stage = (mesa_shader_stage) (stage + 1)) { if (stage_infos[stage] || nir[stage]) { bool shader_application_cache_hit; shader_sha1[20] = (unsigned char) stage; @@ -1935,8 +1935,8 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder, if (retain_nir) { nir_shaders = tu_nir_shaders_init(builder->device, &nir_sha1, sizeof(nir_sha1)); - for (gl_shader_stage stage = MESA_SHADER_VERTEX; - stage < ARRAY_SIZE(nir); stage = (gl_shader_stage) (stage + 1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; + stage < ARRAY_SIZE(nir); stage = (mesa_shader_stage) (stage + 1)) { if (!post_link_nir[stage]) continue; @@ -1946,8 +1946,8 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder, nir_shaders = tu_nir_cache_insert(builder->cache, nir_shaders); } - for (gl_shader_stage stage = MESA_SHADER_VERTEX; stage < ARRAY_SIZE(nir); - stage = (gl_shader_stage) (stage + 1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < ARRAY_SIZE(nir); + stage = (mesa_shader_stage) (stage + 1)) { if (!nir[stage]) continue; @@ -1986,8 +1986,8 @@ done: } } - for (gl_shader_stage stage = MESA_SHADER_VERTEX; - stage < ARRAY_SIZE(nir); stage = (gl_shader_stage) (stage + 1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; + stage < ARRAY_SIZE(nir); stage = (mesa_shader_stage) (stage + 1)) { if (shaders[stage] && shaders[stage]->variant) { tu_append_executable(pipeline, shaders[stage]->variant, nir_initial_disasm[stage]); @@ -1998,8 +1998,8 @@ done: * post_link_nir may be gone. */ if (nir_shaders) { - for (gl_shader_stage stage = MESA_SHADER_VERTEX; - stage < ARRAY_SIZE(nir); stage = (gl_shader_stage) (stage + 1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; + stage < ARRAY_SIZE(nir); stage = (mesa_shader_stage) (stage + 1)) { if (nir_shaders->nir[stage]) { post_link_nir[stage] = nir_shaders->nir[stage]; } @@ -2012,9 +2012,9 @@ done: */ for (unsigned i = 0; i < builder->num_libraries; i++) { struct tu_graphics_lib_pipeline *library = builder->libraries[i]; - for (gl_shader_stage stage = MESA_SHADER_VERTEX; + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < ARRAY_SIZE(library->shaders); - stage = (gl_shader_stage) (stage + 1)) { + stage = (mesa_shader_stage) (stage + 1)) { if (!post_link_nir[stage] && library->shaders[stage].nir) { post_link_nir[stage] = library->shaders[stage].nir; keys[stage] = library->shaders[stage].key; @@ -2047,16 +2047,16 @@ done: struct tu_graphics_lib_pipeline *library = tu_pipeline_to_graphics_lib(pipeline); library->nir_shaders = nir_shaders; - for (gl_shader_stage stage = MESA_SHADER_VERTEX; + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < ARRAY_SIZE(library->shaders); - stage = (gl_shader_stage) (stage + 1)) { + stage = (mesa_shader_stage) (stage + 1)) { library->shaders[stage].nir = post_link_nir[stage]; library->shaders[stage].key = keys[stage]; } } - for (gl_shader_stage stage = MESA_SHADER_VERTEX; - stage < ARRAY_SIZE(shaders); stage = (gl_shader_stage) (stage + 1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; + stage < ARRAY_SIZE(shaders); stage = (mesa_shader_stage) (stage + 1)) { pipeline->shaders[stage] = shaders[stage]; if (shaders[stage]) pipeline->active_desc_sets |= shaders[stage]->active_desc_sets; @@ -2067,7 +2067,7 @@ done: *creation_feedback->pPipelineCreationFeedback = pipeline_feedback; for (uint32_t i = 0; i < creation_feedback->pipelineStageCreationFeedbackCount; i++) { - gl_shader_stage s = + mesa_shader_stage s = vk_to_mesa_shader_stage(builder->create_info->pStages[i].stage); creation_feedback->pPipelineStageCreationFeedbacks[i] = stage_feedbacks[s]; } @@ -2219,8 +2219,8 @@ tu_emit_program_state(struct tu_cs *sub_cs, const struct ir3_shader_variant *variants[MESA_SHADER_STAGES]; struct tu_draw_state draw_states[MESA_SHADER_STAGES]; - for (gl_shader_stage stage = MESA_SHADER_VERTEX; - stage < ARRAY_SIZE(variants); stage = (gl_shader_stage) (stage+1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; + stage < ARRAY_SIZE(variants); stage = (mesa_shader_stage) (stage+1)) { variants[stage] = shaders[stage] ? shaders[stage]->variant : NULL; } @@ -2229,8 +2229,8 @@ tu_emit_program_state(struct tu_cs *sub_cs, unsigned dynamic_descriptor_sizes[MAX_SETS] = { }; - for (gl_shader_stage stage = MESA_SHADER_VERTEX; - stage < ARRAY_SIZE(variants); stage = (gl_shader_stage) (stage+1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; + stage < ARRAY_SIZE(variants); stage = (mesa_shader_stage) (stage+1)) { if (shaders[stage]) { if (safe_variants & (1u << stage)) { variants[stage] = shaders[stage]->safe_const_variant; @@ -4883,7 +4883,7 @@ tu_GetPipelineExecutablePropertiesKHR( util_dynarray_foreach (&pipeline->executables, struct tu_pipeline_executable, exe) { vk_outarray_append_typed(VkPipelineExecutablePropertiesKHR, &out, props) { - gl_shader_stage stage = exe->stage; + mesa_shader_stage stage = exe->stage; props->stages = mesa_to_vk_shader_stage(stage); if (!exe->is_binning) diff --git a/src/freedreno/vulkan/tu_pipeline.h b/src/freedreno/vulkan/tu_pipeline.h index 97bc9765b2b..08627aa55ea 100644 --- a/src/freedreno/vulkan/tu_pipeline.h +++ b/src/freedreno/vulkan/tu_pipeline.h @@ -155,7 +155,7 @@ struct tu_program_state }; struct tu_pipeline_executable { - gl_shader_stage stage; + mesa_shader_stage stage; struct ir3_info stats; bool is_binning; @@ -299,7 +299,7 @@ struct tu_pvtmem_config { template void tu6_emit_xs_config(struct tu_cs *cs, - gl_shader_stage stage, + mesa_shader_stage stage, const struct ir3_shader_variant *xs); template diff --git a/src/freedreno/vulkan/tu_shader.cc b/src/freedreno/vulkan/tu_shader.cc index 9c828d6c156..b0af380bc0e 100644 --- a/src/freedreno/vulkan/tu_shader.cc +++ b/src/freedreno/vulkan/tu_shader.cc @@ -41,7 +41,7 @@ tu_spirv_to_nir(struct tu_device *dev, VkPipelineCreateFlags2KHR pipeline_flags, const VkPipelineShaderStageCreateInfo *stage_info, const struct tu_shader_key *key, - gl_shader_stage stage) + mesa_shader_stage stage) { /* TODO these are made-up */ const struct spirv_to_nir_options spirv_options = { @@ -1359,7 +1359,7 @@ static const struct xs_config { void tu6_emit_xs(struct tu_cs *cs, - gl_shader_stage stage, /* xs->type, but xs may be NULL */ + mesa_shader_stage stage, /* xs->type, but xs may be NULL */ const struct ir3_shader_variant *xs, const struct tu_pvtmem_config *pvtmem, uint64_t binary_iova) @@ -2192,7 +2192,7 @@ TU_GENX(tu6_emit_fs); template static void tu6_emit_variant(struct tu_cs *cs, - gl_shader_stage stage, + mesa_shader_stage stage, const struct ir3_shader_variant *xs, struct tu_pvtmem_config *pvtmem_config, uint32_t view_mask, @@ -2904,8 +2904,8 @@ static void tu_link_shaders(nir_shader **shaders, unsigned shaders_count) { nir_shader *consumer = NULL; - for (gl_shader_stage stage = (gl_shader_stage) (shaders_count - 1); - stage >= MESA_SHADER_VERTEX; stage = (gl_shader_stage) (stage - 1)) { + for (mesa_shader_stage stage = (mesa_shader_stage) (shaders_count - 1); + stage >= MESA_SHADER_VERTEX; stage = (mesa_shader_stage) (stage - 1)) { if (!shaders[stage]) continue; @@ -2953,8 +2953,8 @@ tu_link_shaders(nir_shader **shaders, unsigned shaders_count) /* Gather info after linking so that we can fill out the ir3 shader key. */ - for (gl_shader_stage stage = MESA_SHADER_VERTEX; - stage <= MESA_SHADER_FRAGMENT; stage = (gl_shader_stage) (stage + 1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; + stage <= MESA_SHADER_FRAGMENT; stage = (mesa_shader_stage) (stage + 1)) { if (shaders[stage]) nir_shader_gather_info(shaders[stage], nir_shader_get_entrypoint(shaders[stage])); @@ -2997,8 +2997,8 @@ tu_compile_shaders(struct tu_device *device, VkResult result = VK_SUCCESS; void *mem_ctx = ralloc_context(NULL); - for (gl_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; - stage = (gl_shader_stage) (stage + 1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; + stage = (mesa_shader_stage) (stage + 1)) { const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage]; if (!stage_info) continue; @@ -3020,9 +3020,9 @@ tu_compile_shaders(struct tu_device *device, ir3_key.has_gs = true; if (nir_initial_disasm) { - for (gl_shader_stage stage = MESA_SHADER_VERTEX; + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; - stage = (gl_shader_stage) (stage + 1)) { + stage = (mesa_shader_stage) (stage + 1)) { if (!nir[stage]) continue; @@ -3034,8 +3034,8 @@ tu_compile_shaders(struct tu_device *device, tu_link_shaders(nir, MESA_SHADER_STAGES); if (nir_out) { - for (gl_shader_stage stage = MESA_SHADER_VERTEX; - stage < MESA_SHADER_STAGES; stage = (gl_shader_stage) (stage + 1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; + stage < MESA_SHADER_STAGES; stage = (mesa_shader_stage) (stage + 1)) { if (!nir[stage]) continue; @@ -3071,8 +3071,8 @@ tu_compile_shaders(struct tu_device *device, ir3_key.tessellation = tu6_get_tessmode(tes); } - for (gl_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; - stage = (gl_shader_stage) (stage + 1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; + stage = (mesa_shader_stage) (stage + 1)) { if (!nir[stage]) continue; @@ -3093,8 +3093,8 @@ tu_compile_shaders(struct tu_device *device, if (nir[MESA_SHADER_TESS_CTRL] && !nir[MESA_SHADER_FRAGMENT]) ir3_key.tcs_store_primid = true; - for (gl_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; - stage = (gl_shader_stage) (stage + 1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; + stage = (mesa_shader_stage) (stage + 1)) { if (!nir[stage] || shaders[stage]) continue; @@ -3122,8 +3122,8 @@ tu_compile_shaders(struct tu_device *device, fail: ralloc_free(mem_ctx); - for (gl_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; - stage = (gl_shader_stage) (stage + 1)) { + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; + stage = (mesa_shader_stage) (stage + 1)) { if (shaders[stage]) { tu_shader_destroy(device, shaders[stage]); } @@ -3188,7 +3188,7 @@ tu_shader_key_robustness(struct tu_shader_key *key, static VkResult tu_empty_shader_create(struct tu_device *dev, struct tu_shader **shader_out, - gl_shader_stage stage) + mesa_shader_stage stage) { struct tu_shader *shader = tu_shader_init(dev, NULL, 0); diff --git a/src/freedreno/vulkan/tu_shader.h b/src/freedreno/vulkan/tu_shader.h index 21a7c035a2a..02b68471bb8 100644 --- a/src/freedreno/vulkan/tu_shader.h +++ b/src/freedreno/vulkan/tu_shader.h @@ -144,11 +144,11 @@ tu_spirv_to_nir(struct tu_device *dev, VkPipelineCreateFlags2KHR pipeline_flags, const VkPipelineShaderStageCreateInfo *stage_info, const struct tu_shader_key *key, - gl_shader_stage stage); + mesa_shader_stage stage); void tu6_emit_xs(struct tu_cs *cs, - gl_shader_stage stage, + mesa_shader_stage stage, const struct ir3_shader_variant *xs, const struct tu_pvtmem_config *pvtmem, uint64_t binary_iova); diff --git a/src/freedreno/vulkan/tu_util.h b/src/freedreno/vulkan/tu_util.h index 48d1b75417c..5e9dd52c488 100644 --- a/src/freedreno/vulkan/tu_util.h +++ b/src/freedreno/vulkan/tu_util.h @@ -141,10 +141,10 @@ tu_framebuffer_tiling_config(struct tu_framebuffer *fb, #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1) #define tu_foreach_stage(stage, stage_bits) \ - for (gl_shader_stage stage, \ - __tmp = (gl_shader_stage) ((stage_bits) &TU_STAGE_MASK); \ - stage = (gl_shader_stage) (__builtin_ffs(__tmp) - 1), __tmp; \ - __tmp = (gl_shader_stage) (__tmp & ~(1 << (stage)))) + for (mesa_shader_stage stage, \ + __tmp = (mesa_shader_stage) ((stage_bits) &TU_STAGE_MASK); \ + stage = (mesa_shader_stage) (__builtin_ffs(__tmp) - 1), __tmp; \ + __tmp = (mesa_shader_stage) (__tmp & ~(1 << (stage)))) static inline enum a3xx_msaa_samples tu_msaa_samples(uint32_t samples) @@ -154,7 +154,7 @@ tu_msaa_samples(uint32_t samples) } static inline uint32_t -tu6_stage2opcode(gl_shader_stage stage) +tu6_stage2opcode(mesa_shader_stage stage) { if (stage == MESA_SHADER_FRAGMENT || stage == MESA_SHADER_COMPUTE) return CP_LOAD_STATE6_FRAG; @@ -162,13 +162,13 @@ tu6_stage2opcode(gl_shader_stage stage) } static inline enum a6xx_state_block -tu6_stage2texsb(gl_shader_stage stage) +tu6_stage2texsb(mesa_shader_stage stage) { return (enum a6xx_state_block) (SB6_VS_TEX + stage); } static inline enum a6xx_state_block -tu6_stage2shadersb(gl_shader_stage stage) +tu6_stage2shadersb(mesa_shader_stage stage) { return (enum a6xx_state_block) (SB6_VS_SHADER + stage); } diff --git a/src/gallium/auxiliary/driver_trace/tr_screen.h b/src/gallium/auxiliary/driver_trace/tr_screen.h index 5e20093788c..6faba08cc55 100644 --- a/src/gallium/auxiliary/driver_trace/tr_screen.h +++ b/src/gallium/auxiliary/driver_trace/tr_screen.h @@ -46,7 +46,7 @@ extern "C" { #define TRACE_FLAG_USER_BUFFER (1 << 31) static inline const char * -tr_util_pipe_shader_type_name(gl_shader_stage stage) +tr_util_pipe_shader_type_name(mesa_shader_stage stage) { return gl_shader_stage_name(stage); } diff --git a/src/gallium/auxiliary/gallivm/lp_bld_nir.h b/src/gallium/auxiliary/gallivm/lp_bld_nir.h index f443ec9d20f..ba7d4b8c1c1 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_nir.h +++ b/src/gallium/auxiliary/gallivm/lp_bld_nir.h @@ -92,7 +92,7 @@ LLVMAtomicRMWBinOp lp_translate_atomic_op(nir_atomic_op op); uint32_t -lp_build_nir_sample_key(gl_shader_stage stage, nir_tex_instr *instr); +lp_build_nir_sample_key(mesa_shader_stage stage, nir_tex_instr *instr); void lp_img_op_from_intrinsic(struct lp_img_params *params, nir_intrinsic_instr *instr); diff --git a/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c b/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c index 9fbe3890eae..88fb2fd889d 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c @@ -5273,7 +5273,7 @@ visit_txs(struct lp_build_nir_soa_context *bld, nir_tex_instr *instr) } static enum lp_sampler_lod_property -lp_build_nir_lod_property(gl_shader_stage stage, nir_src lod_src) +lp_build_nir_lod_property(mesa_shader_stage stage, nir_src lod_src) { enum lp_sampler_lod_property lod_property; @@ -5291,7 +5291,7 @@ lp_build_nir_lod_property(gl_shader_stage stage, nir_src lod_src) } uint32_t -lp_build_nir_sample_key(gl_shader_stage stage, nir_tex_instr *instr) +lp_build_nir_sample_key(mesa_shader_stage stage, nir_tex_instr *instr) { uint32_t sample_key = 0; diff --git a/src/gallium/auxiliary/tgsi/tgsi_from_mesa.h b/src/gallium/auxiliary/tgsi/tgsi_from_mesa.h index 06a401fa731..abdb6c54358 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_from_mesa.h +++ b/src/gallium/auxiliary/tgsi/tgsi_from_mesa.h @@ -59,7 +59,7 @@ enum tgsi_interpolate_mode tgsi_get_interp_mode(enum glsl_interp_mode mode, bool color); static inline enum pipe_shader_type -pipe_shader_type_from_mesa(gl_shader_stage stage) +pipe_shader_type_from_mesa(mesa_shader_stage stage) { STATIC_ASSERT((enum pipe_shader_type) MESA_SHADER_VERTEX == MESA_SHADER_VERTEX); STATIC_ASSERT((enum pipe_shader_type) MESA_SHADER_FRAGMENT == MESA_SHADER_FRAGMENT); @@ -70,10 +70,10 @@ pipe_shader_type_from_mesa(gl_shader_stage stage) return (enum pipe_shader_type)stage; } -static inline gl_shader_stage +static inline mesa_shader_stage tgsi_processor_to_shader_stage(unsigned processor) { - return (gl_shader_stage)processor; + return (mesa_shader_stage)processor; } #ifdef __cplusplus diff --git a/src/gallium/drivers/asahi/agx_nir_lower_sysvals.c b/src/gallium/drivers/asahi/agx_nir_lower_sysvals.c index 7e09b3c1b4d..431bcded6f0 100644 --- a/src/gallium/drivers/asahi/agx_nir_lower_sysvals.c +++ b/src/gallium/drivers/asahi/agx_nir_lower_sysvals.c @@ -43,7 +43,7 @@ struct table_state { }; struct state { - gl_shader_stage stage, hw_stage; + mesa_shader_stage stage, hw_stage; /* Array of nir_intrinsic_instr's to fix up at the end */ struct util_dynarray loads; @@ -95,7 +95,7 @@ load_sysval_indirect(nir_builder *b, unsigned dim, unsigned bitsize, static unsigned stage_table(nir_builder *b) { - gl_shader_stage stage = b->shader->info.stage; + mesa_shader_stage stage = b->shader->info.stage; if (stage == MESA_SHADER_VERTEX && b->shader->info.vs.tes_agx) stage = MESA_SHADER_TESS_EVAL; diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c index 63e4fc54f91..bdc663f2552 100644 --- a/src/gallium/drivers/asahi/agx_state.c +++ b/src/gallium/drivers/asahi/agx_state.c @@ -1937,7 +1937,7 @@ agx_create_shader_state(struct pipe_context *pctx, } agx_shader_initialize(dev, so, nir, ctx->support_lod_bias, ctx->robust); - gl_shader_stage next_stage = nir->info.next_stage; + mesa_shader_stage next_stage = nir->info.next_stage; /* We're done with the NIR, throw it away */ ralloc_free(nir); diff --git a/src/gallium/drivers/crocus/crocus_context.h b/src/gallium/drivers/crocus/crocus_context.h index b0edbc63d9a..ee48acecd19 100644 --- a/src/gallium/drivers/crocus/crocus_context.h +++ b/src/gallium/drivers/crocus/crocus_context.h @@ -838,10 +838,10 @@ void crocus_init_flush_functions(struct pipe_context *ctx); /* crocus_program.c */ const struct shader_info *crocus_get_shader_info(const struct crocus_context *ice, - gl_shader_stage stage); + mesa_shader_stage stage); struct crocus_bo *crocus_get_scratch_space(struct crocus_context *ice, unsigned per_thread_scratch, - gl_shader_stage stage); + mesa_shader_stage stage); /** * Map a pair to a binding table index. * @@ -943,7 +943,7 @@ bool crocus_blorp_upload_shader(struct blorp_batch *blorp_batch, void crocus_predraw_resolve_inputs(struct crocus_context *ice, struct crocus_batch *batch, bool *draw_aux_buffer_disabled, - gl_shader_stage stage, + mesa_shader_stage stage, bool consider_framebuffer); void crocus_predraw_resolve_framebuffer(struct crocus_context *ice, struct crocus_batch *batch, diff --git a/src/gallium/drivers/crocus/crocus_disk_cache.c b/src/gallium/drivers/crocus/crocus_disk_cache.c index fce961c960e..79e8c8b1a50 100644 --- a/src/gallium/drivers/crocus/crocus_disk_cache.c +++ b/src/gallium/drivers/crocus/crocus_disk_cache.c @@ -86,7 +86,7 @@ crocus_disk_cache_store(struct disk_cache *cache, if (!cache) return; - gl_shader_stage stage = ish->nir->info.stage; + mesa_shader_stage stage = ish->nir->info.stage; const struct elk_stage_prog_data *prog_data = shader->prog_data; cache_key cache_key; @@ -137,7 +137,7 @@ crocus_disk_cache_retrieve(struct crocus_context *ice, #ifdef ENABLE_SHADER_CACHE struct crocus_screen *screen = (void *) ice->ctx.screen; struct disk_cache *cache = screen->disk_cache; - gl_shader_stage stage = ish->nir->info.stage; + mesa_shader_stage stage = ish->nir->info.stage; if (!cache) return NULL; diff --git a/src/gallium/drivers/crocus/crocus_draw.c b/src/gallium/drivers/crocus/crocus_draw.c index a848b1869a8..f1db66775e6 100644 --- a/src/gallium/drivers/crocus/crocus_draw.c +++ b/src/gallium/drivers/crocus/crocus_draw.c @@ -422,7 +422,7 @@ crocus_draw_vbo(struct pipe_context *ctx, if (ice->state.dirty & CROCUS_DIRTY_RENDER_RESOLVES_AND_FLUSHES) { bool draw_aux_buffer_disabled[ELK_MAX_DRAW_BUFFERS] = { }; - for (gl_shader_stage stage = 0; stage < MESA_SHADER_COMPUTE; stage++) { + for (mesa_shader_stage stage = 0; stage < MESA_SHADER_COMPUTE; stage++) { if (ice->shaders.prog[stage]) crocus_predraw_resolve_inputs(ice, batch, draw_aux_buffer_disabled, stage, true); diff --git a/src/gallium/drivers/crocus/crocus_pipe.h b/src/gallium/drivers/crocus/crocus_pipe.h index b1370aa05bf..4b4f7f11375 100644 --- a/src/gallium/drivers/crocus/crocus_pipe.h +++ b/src/gallium/drivers/crocus/crocus_pipe.h @@ -26,14 +26,14 @@ #include "pipe/p_defines.h" #include "compiler/shader_enums.h" -static inline gl_shader_stage +static inline mesa_shader_stage stage_from_pipe(enum pipe_shader_type pstage) { - return (gl_shader_stage)pstage; + return (mesa_shader_stage)pstage; } static inline enum pipe_shader_type -stage_to_pipe(gl_shader_stage stage) +stage_to_pipe(mesa_shader_stage stage) { return (enum pipe_shader_type)stage; } diff --git a/src/gallium/drivers/crocus/crocus_program.c b/src/gallium/drivers/crocus/crocus_program.c index baf1a5973ec..9b8eda93907 100644 --- a/src/gallium/drivers/crocus/crocus_program.c +++ b/src/gallium/drivers/crocus/crocus_program.c @@ -150,7 +150,7 @@ gfx6_ff_gs_xfb_setup(const struct pipe_stream_output_info *so_info, static void crocus_populate_sampler_prog_key_data(struct crocus_context *ice, const struct intel_device_info *devinfo, - gl_shader_stage stage, + mesa_shader_stage stage, struct crocus_uncompiled_shader *ish, bool uses_texture_gather, struct elk_sampler_prog_key_data *key) @@ -1069,7 +1069,7 @@ crocus_debug_recompile(struct crocus_context *ice, * * This stage is the one which will feed stream output and the rasterizer. */ -static gl_shader_stage +static mesa_shader_stage last_vue_stage(struct crocus_context *ice) { if (ice->shaders.uncompiled[MESA_SHADER_GEOMETRY]) @@ -1330,7 +1330,7 @@ crocus_update_compiled_vs(struct crocus_context *ice) * Get the shader_info for a given stage, or NULL if the stage is disabled. */ const struct shader_info * -crocus_get_shader_info(const struct crocus_context *ice, gl_shader_stage stage) +crocus_get_shader_info(const struct crocus_context *ice, mesa_shader_stage stage) { const struct crocus_uncompiled_shader *ish = ice->shaders.uncompiled[stage]; @@ -1985,7 +1985,7 @@ update_last_vue_map(struct crocus_context *ice, static void crocus_update_pull_constant_descriptors(struct crocus_context *ice, - gl_shader_stage stage) + mesa_shader_stage stage) { struct crocus_compiled_shader *shader = ice->shaders.prog[stage]; @@ -2014,7 +2014,7 @@ crocus_update_pull_constant_descriptors(struct crocus_context *ice, * Get the prog_data for a given stage, or NULL if the stage is disabled. */ static struct elk_vue_prog_data * -get_vue_prog_data(struct crocus_context *ice, gl_shader_stage stage) +get_vue_prog_data(struct crocus_context *ice, mesa_shader_stage stage) { if (!ice->shaders.prog[stage]) return NULL; @@ -2442,7 +2442,7 @@ crocus_update_compiled_shaders(struct crocus_context *ice) if (!ice->shaders.prog[MESA_SHADER_VERTEX]) return false; - gl_shader_stage last_stage = last_vue_stage(ice); + mesa_shader_stage last_stage = last_vue_stage(ice); struct crocus_compiled_shader *shader = ice->shaders.prog[last_stage]; struct crocus_uncompiled_shader *ish = ice->shaders.uncompiled[last_stage]; update_last_vue_map(ice, shader->prog_data); @@ -2624,7 +2624,7 @@ crocus_fill_cs_push_const_buffer(struct elk_cs_prog_data *cs_prog_data, struct crocus_bo * crocus_get_scratch_space(struct crocus_context *ice, unsigned per_thread_scratch, - gl_shader_stage stage) + mesa_shader_stage stage) { struct crocus_screen *screen = (struct crocus_screen *)ice->ctx.screen; struct crocus_bufmgr *bufmgr = screen->bufmgr; @@ -2915,7 +2915,7 @@ crocus_create_compute_state(struct pipe_context *ctx, * Frees the crocus_uncompiled_shader. */ static void -crocus_delete_shader_state(struct pipe_context *ctx, void *state, gl_shader_stage stage) +crocus_delete_shader_state(struct pipe_context *ctx, void *state, mesa_shader_stage stage) { struct crocus_uncompiled_shader *ish = state; struct crocus_context *ice = (void *) ctx; @@ -2979,7 +2979,7 @@ crocus_delete_cs_state(struct pipe_context *ctx, void *state) static void bind_shader_state(struct crocus_context *ice, struct crocus_uncompiled_shader *ish, - gl_shader_stage stage) + mesa_shader_stage stage) { uint64_t dirty_bit = CROCUS_STAGE_DIRTY_UNCOMPILED_VS << stage; const uint64_t nos = ish ? ish->nos : 0; diff --git a/src/gallium/drivers/crocus/crocus_resolve.c b/src/gallium/drivers/crocus/crocus_resolve.c index b509fe33935..7fd8cd2b434 100644 --- a/src/gallium/drivers/crocus/crocus_resolve.c +++ b/src/gallium/drivers/crocus/crocus_resolve.c @@ -197,7 +197,7 @@ void crocus_predraw_resolve_inputs(struct crocus_context *ice, struct crocus_batch *batch, bool *draw_aux_buffer_disabled, - gl_shader_stage stage, + mesa_shader_stage stage, bool consider_framebuffer) { struct crocus_shader_state *shs = &ice->state.shaders[stage]; diff --git a/src/gallium/drivers/crocus/crocus_screen.h b/src/gallium/drivers/crocus/crocus_screen.h index 6b871d909a4..fbcc0aa81a4 100644 --- a/src/gallium/drivers/crocus/crocus_screen.h +++ b/src/gallium/drivers/crocus/crocus_screen.h @@ -118,17 +118,17 @@ struct crocus_vtable { const struct intel_vue_map *vue_map); void (*populate_vs_key)(const struct crocus_context *ice, const struct shader_info *info, - gl_shader_stage last_stage, + mesa_shader_stage last_stage, struct elk_vs_prog_key *key); void (*populate_tcs_key)(const struct crocus_context *ice, struct elk_tcs_prog_key *key); void (*populate_tes_key)(const struct crocus_context *ice, const struct shader_info *info, - gl_shader_stage last_stage, + mesa_shader_stage last_stage, struct elk_tes_prog_key *key); void (*populate_gs_key)(const struct crocus_context *ice, const struct shader_info *info, - gl_shader_stage last_stage, + mesa_shader_stage last_stage, struct elk_gs_prog_key *key); void (*populate_fs_key)(const struct crocus_context *ice, const struct shader_info *info, diff --git a/src/gallium/drivers/crocus/crocus_state.c b/src/gallium/drivers/crocus/crocus_state.c index 8a316df7103..c7b5ebbed9f 100644 --- a/src/gallium/drivers/crocus/crocus_state.c +++ b/src/gallium/drivers/crocus/crocus_state.c @@ -909,7 +909,7 @@ calculate_curbe_offsets(struct crocus_batch *batch) static void upload_shader_consts(struct crocus_context *ice, - gl_shader_stage stage, + mesa_shader_stage stage, uint32_t *map, unsigned start) { @@ -2302,7 +2302,7 @@ crocus_bind_sampler_states(struct pipe_context *ctx, void **states) { struct crocus_context *ice = (struct crocus_context *) ctx; - gl_shader_stage stage = stage_from_pipe(p_stage); + mesa_shader_stage stage = stage_from_pipe(p_stage); struct crocus_shader_state *shs = &ice->state.shaders[stage]; assert(start + count <= CROCUS_MAX_TEXTURE_SAMPLERS); @@ -2593,7 +2593,7 @@ crocus_upload_border_color(struct crocus_batch *batch, */ static void crocus_upload_sampler_states(struct crocus_context *ice, - struct crocus_batch *batch, gl_shader_stage stage) + struct crocus_batch *batch, mesa_shader_stage stage) { struct crocus_shader_state *shs = &ice->state.shaders[stage]; const struct shader_info *info = crocus_get_shader_info(ice, stage); @@ -3040,7 +3040,7 @@ crocus_set_shader_images(struct pipe_context *ctx, struct crocus_context *ice = (struct crocus_context *) ctx; struct crocus_screen *screen = (struct crocus_screen *)ctx->screen; const struct intel_device_info *devinfo = &screen->devinfo; - gl_shader_stage stage = stage_from_pipe(p_stage); + mesa_shader_stage stage = stage_from_pipe(p_stage); struct crocus_shader_state *shs = &ice->state.shaders[stage]; struct crocus_genx_state *genx = ice->state.genx; struct isl_image_param *image_params = genx->shaders[stage].image_param; @@ -3135,7 +3135,7 @@ crocus_set_sampler_views(struct pipe_context *ctx, struct pipe_sampler_view **views) { struct crocus_context *ice = (struct crocus_context *) ctx; - gl_shader_stage stage = stage_from_pipe(p_stage); + mesa_shader_stage stage = stage_from_pipe(p_stage); struct crocus_shader_state *shs = &ice->state.shaders[stage]; shs->bound_sampler_views &= ~u_bit_consecutive(start, count); @@ -3509,7 +3509,7 @@ crocus_set_constant_buffer(struct pipe_context *ctx, const struct pipe_constant_buffer *input) { struct crocus_context *ice = (struct crocus_context *) ctx; - gl_shader_stage stage = stage_from_pipe(p_stage); + mesa_shader_stage stage = stage_from_pipe(p_stage); struct crocus_shader_state *shs = &ice->state.shaders[stage]; struct pipe_constant_buffer *cbuf = &shs->constbufs[index]; @@ -3549,7 +3549,7 @@ crocus_set_constant_buffer(struct pipe_context *ctx, static void upload_sysvals(struct crocus_context *ice, - gl_shader_stage stage) + mesa_shader_stage stage) { UNUSED struct crocus_genx_state *genx = ice->state.genx; struct crocus_shader_state *shs = &ice->state.shaders[stage]; @@ -3638,7 +3638,7 @@ crocus_set_shader_buffers(struct pipe_context *ctx, unsigned writable_bitmask) { struct crocus_context *ice = (struct crocus_context *) ctx; - gl_shader_stage stage = stage_from_pipe(p_stage); + mesa_shader_stage stage = stage_from_pipe(p_stage); struct crocus_shader_state *shs = &ice->state.shaders[stage]; unsigned modified_bits = u_bit_consecutive(start_slot, count); @@ -4704,7 +4704,7 @@ crocus_emit_sbe(struct crocus_batch *batch, const struct crocus_context *ice) static void crocus_populate_vs_key(const struct crocus_context *ice, const struct shader_info *info, - gl_shader_stage last_stage, + mesa_shader_stage last_stage, struct elk_vs_prog_key *key) { const struct crocus_rasterizer_state *cso_rast = ice->state.cso_rast; @@ -4752,7 +4752,7 @@ crocus_populate_tcs_key(const struct crocus_context *ice, static void crocus_populate_tes_key(const struct crocus_context *ice, const struct shader_info *info, - gl_shader_stage last_stage, + mesa_shader_stage last_stage, struct elk_tes_prog_key *key) { const struct crocus_rasterizer_state *cso_rast = ice->state.cso_rast; @@ -4773,7 +4773,7 @@ crocus_populate_tes_key(const struct crocus_context *ice, static void crocus_populate_gs_key(const struct crocus_context *ice, const struct shader_info *info, - gl_shader_stage last_stage, + mesa_shader_stage last_stage, struct elk_gs_prog_key *key) { const struct crocus_rasterizer_state *cso_rast = ice->state.cso_rast; @@ -5394,7 +5394,7 @@ emit_sol_surface(struct crocus_batch *batch, static void crocus_populate_binding_table(struct crocus_context *ice, struct crocus_batch *batch, - gl_shader_stage stage, bool ff_gs) + mesa_shader_stage stage, bool ff_gs) { struct crocus_compiled_shader *shader = ff_gs ? ice->shaders.ff_gs_prog : ice->shaders.prog[stage]; struct crocus_shader_state *shs = ff_gs ? NULL : &ice->state.shaders[stage]; diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler.h b/src/gallium/drivers/etnaviv/etnaviv_compiler.h index 13b5199baec..056726706e1 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_compiler.h +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler.h @@ -99,7 +99,7 @@ struct etna_shader_variant { #define VARIANT_CACHE_PTR(v) (((char *)v) + VARIANT_CACHE_START) #define VARIANT_CACHE_SIZE (sizeof(struct etna_shader_variant) - VARIANT_CACHE_START) - gl_shader_stage stage; + mesa_shader_stage stage; uint32_t code_size; /* code size in uint32 words */ unsigned num_loops; unsigned num_temps; diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_program.c b/src/gallium/drivers/freedreno/a2xx/fd2_program.c index 9a6f5b944cd..dfdc987e301 100644 --- a/src/gallium/drivers/freedreno/a2xx/fd2_program.c +++ b/src/gallium/drivers/freedreno/a2xx/fd2_program.c @@ -36,7 +36,7 @@ fd2_shader_state_delete(struct pipe_context *pctx, void *hwcso) } static void -emit(struct fd_ringbuffer *ring, gl_shader_stage type, +emit(struct fd_ringbuffer *ring, mesa_shader_stage type, struct ir2_shader_info *info, struct util_dynarray *patches) { unsigned i; diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_program.h b/src/gallium/drivers/freedreno/a2xx/fd2_program.h index b18d82faf5c..94bd320a7cf 100644 --- a/src/gallium/drivers/freedreno/a2xx/fd2_program.h +++ b/src/gallium/drivers/freedreno/a2xx/fd2_program.h @@ -18,7 +18,7 @@ struct fd2_shader_stateobj { nir_shader *nir; - gl_shader_stage type; + mesa_shader_stage type; bool is_a20x; /* note: using same set of immediates for all variants diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c index 7ff0eb670c8..16a3c4b1fd8 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c @@ -81,7 +81,7 @@ fd3_emit_const_bo(struct fd_ringbuffer *ring, } static void -fd3_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type, +fd3_emit_const_ptrs(struct fd_ringbuffer *ring, mesa_shader_stage type, uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets) { diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c index 9a8ac9a3f85..bb4b0cb454b 100644 --- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c +++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c @@ -74,7 +74,7 @@ fd4_emit_const_bo(struct fd_ringbuffer *ring, } static void -fd4_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type, +fd4_emit_const_ptrs(struct fd_ringbuffer *ring, mesa_shader_stage type, uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets) { diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c index 862dbc6ec1b..e8212c371b3 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c @@ -76,7 +76,7 @@ fd5_emit_const_bo(struct fd_ringbuffer *ring, } static void -fd5_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type, +fd5_emit_const_ptrs(struct fd_ringbuffer *ring, mesa_shader_stage type, uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets) { diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h index 49da494c517..19c1a0ffe11 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h @@ -310,7 +310,7 @@ fd6_emit_blit(struct fd_context *ctx, struct fd_ringbuffer *ring) } static inline bool -fd6_geom_stage(gl_shader_stage type) +fd6_geom_stage(mesa_shader_stage type) { switch (type) { case MESA_SHADER_VERTEX: @@ -328,13 +328,13 @@ fd6_geom_stage(gl_shader_stage type) } static inline uint32_t -fd6_stage2opcode(gl_shader_stage type) +fd6_stage2opcode(mesa_shader_stage type) { return fd6_geom_stage(type) ? CP_LOAD_STATE6_GEOM : CP_LOAD_STATE6_FRAG; } static inline enum a6xx_state_block -fd6_stage2shadersb(gl_shader_stage type) +fd6_stage2shadersb(mesa_shader_stage type) { switch (type) { case MESA_SHADER_VERTEX: diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.cc b/src/gallium/drivers/freedreno/a6xx/fd6_program.cc index 21e3a476b27..a15e3a76b7b 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.cc @@ -114,7 +114,7 @@ fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring, fd_emit_string5(ring, name, strlen(name)); #endif - gl_shader_stage type = so->type; + mesa_shader_stage type = so->type; if (type == MESA_SHADER_KERNEL) type = MESA_SHADER_COMPUTE; diff --git a/src/gallium/drivers/freedreno/freedreno_util.h b/src/gallium/drivers/freedreno/freedreno_util.h index f5a7eb0062e..dd748f36133 100644 --- a/src/gallium/drivers/freedreno/freedreno_util.h +++ b/src/gallium/drivers/freedreno/freedreno_util.h @@ -458,7 +458,7 @@ fd_clamp_buffer_size(enum pipe_format format, uint32_t size, */ static inline enum a4xx_state_block -fd4_stage2shadersb(gl_shader_stage type) +fd4_stage2shadersb(mesa_shader_stage type) { switch (type) { case MESA_SHADER_VERTEX: diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cache.c b/src/gallium/drivers/freedreno/ir3/ir3_cache.c index 5ce96417fc3..3ad3d9c565e 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_cache.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_cache.c @@ -102,7 +102,7 @@ ir3_cache_lookup(struct ir3_cache *cache, const struct ir3_cache_key *key, const struct ir3_shader_variant *variants[MESA_SHADER_STAGES]; struct ir3_shader_key shader_key = key->key; - for (gl_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; stage++) { if (shaders[stage]) { variants[stage] = @@ -118,7 +118,7 @@ ir3_cache_lookup(struct ir3_cache *cache, const struct ir3_cache_key *key, uint32_t safe_constlens = ir3_trim_constlen(variants, compiler); shader_key.safe_constlen = true; - for (gl_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_SHADER_STAGES; stage++) { if (safe_constlens & (1 << stage)) { variants[stage] = diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index ff32e31e57d..3350fd7c1b6 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -695,7 +695,7 @@ struct iris_compiled_shader { struct iris_binding_table bt; - gl_shader_stage stage; + mesa_shader_stage stage; /** * Data derived from prog_data. @@ -1333,10 +1333,10 @@ void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice, struct iris_state_ref *surf_state, isl_surf_usage_flags_t usage); const struct shader_info *iris_get_shader_info(const struct iris_context *ice, - gl_shader_stage stage); + mesa_shader_stage stage); struct iris_bo *iris_get_scratch_space(struct iris_context *ice, unsigned per_thread_scratch, - gl_shader_stage stage); + mesa_shader_stage stage); const struct iris_state_ref *iris_get_scratch_surf(struct iris_context *ice, unsigned per_thread_scratch); uint32_t iris_group_index_to_bti(const struct iris_binding_table *bt, @@ -1391,7 +1391,7 @@ struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice, struct iris_compiled_shader *iris_create_shader_variant(const struct iris_screen *, void *mem_ctx, - gl_shader_stage stage, + mesa_shader_stage stage, enum iris_program_cache_id cache_id, uint32_t key_size, const void *key); @@ -1467,17 +1467,17 @@ void iris_ensure_indirect_generation_shader(struct iris_batch *batch); void iris_predraw_resolve_inputs(struct iris_context *ice, struct iris_batch *batch, bool *draw_aux_buffer_disabled, - gl_shader_stage stage, + mesa_shader_stage stage, bool consider_framebuffer); void iris_predraw_resolve_framebuffer(struct iris_context *ice, struct iris_batch *batch, bool *draw_aux_buffer_disabled); void iris_predraw_flush_buffers(struct iris_context *ice, struct iris_batch *batch, - gl_shader_stage stage); + mesa_shader_stage stage); void iris_postdraw_update_resolve_tracking(struct iris_context *ice); void iris_postdraw_update_image_resolve_tracking(struct iris_context *ice, - gl_shader_stage stage); + mesa_shader_stage stage); int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index, struct pipe_driver_query_info *info); int iris_get_driver_query_group_info(struct pipe_screen *pscreen, diff --git a/src/gallium/drivers/iris/iris_disk_cache.c b/src/gallium/drivers/iris/iris_disk_cache.c index 28ce4215d09..d10036a35c0 100644 --- a/src/gallium/drivers/iris/iris_disk_cache.c +++ b/src/gallium/drivers/iris/iris_disk_cache.c @@ -89,7 +89,7 @@ iris_disk_cache_store(struct disk_cache *cache, if (!cache) return; - gl_shader_stage stage = ish->nir->info.stage; + mesa_shader_stage stage = ish->nir->info.stage; const struct brw_stage_prog_data *brw = shader->brw_prog_data; #ifdef INTEL_USE_ELK const struct elk_stage_prog_data *elk = shader->elk_prog_data; @@ -194,7 +194,7 @@ iris_disk_cache_retrieve(struct iris_screen *screen, { #ifdef ENABLE_SHADER_CACHE struct disk_cache *cache = screen->disk_cache; - gl_shader_stage stage = ish->nir->info.stage; + mesa_shader_stage stage = ish->nir->info.stage; if (!cache) return false; diff --git a/src/gallium/drivers/iris/iris_draw.c b/src/gallium/drivers/iris/iris_draw.c index 5ebff010279..97f08f254e3 100644 --- a/src/gallium/drivers/iris/iris_draw.c +++ b/src/gallium/drivers/iris/iris_draw.c @@ -308,7 +308,7 @@ iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info, if (ice->state.dirty & IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES) { bool draw_aux_buffer_disabled[IRIS_MAX_DRAW_BUFFERS] = { }; - for (gl_shader_stage stage = 0; stage < MESA_SHADER_COMPUTE; stage++) { + for (mesa_shader_stage stage = 0; stage < MESA_SHADER_COMPUTE; stage++) { if (ice->shaders.prog[stage]) iris_predraw_resolve_inputs(ice, batch, draw_aux_buffer_disabled, stage, true); @@ -317,7 +317,7 @@ iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info, } if (ice->state.dirty & IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES) { - for (gl_shader_stage stage = 0; stage < MESA_SHADER_COMPUTE; stage++) + for (mesa_shader_stage stage = 0; stage < MESA_SHADER_COMPUTE; stage++) iris_predraw_flush_buffers(ice, batch, stage); } diff --git a/src/gallium/drivers/iris/iris_pipe.h b/src/gallium/drivers/iris/iris_pipe.h index 573d76261cf..779299da770 100644 --- a/src/gallium/drivers/iris/iris_pipe.h +++ b/src/gallium/drivers/iris/iris_pipe.h @@ -26,14 +26,14 @@ #include "pipe/p_defines.h" #include "compiler/shader_enums.h" -static inline gl_shader_stage +static inline mesa_shader_stage stage_from_pipe(enum pipe_shader_type pstage) { - return (gl_shader_stage)pstage; + return (mesa_shader_stage)pstage; } static inline enum pipe_shader_type -stage_to_pipe(gl_shader_stage stage) +stage_to_pipe(mesa_shader_stage stage) { return (enum pipe_shader_type)stage; } diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index 03f3c3979b4..5a73503e7bf 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -1699,7 +1699,7 @@ iris_debug_recompile_elk(struct iris_screen *screen, static void check_urb_size(struct iris_context *ice, unsigned needed_size, - gl_shader_stage stage) + mesa_shader_stage stage) { unsigned last_allocated_size = ice->shaders.urb.cfg.size[stage]; @@ -1720,7 +1720,7 @@ check_urb_size(struct iris_context *ice, * * This stage is the one which will feed stream output and the rasterizer. */ -static gl_shader_stage +static mesa_shader_stage last_vue_stage(struct iris_context *ice) { if (ice->shaders.uncompiled[MESA_SHADER_GEOMETRY]) @@ -1781,7 +1781,7 @@ find_or_add_variant(const struct iris_screen *screen, } } - gl_shader_stage stage = ish->nir->info.stage; + mesa_shader_stage stage = ish->nir->info.stage; if (variant == NULL) { variant = iris_create_shader_variant(screen, NULL, stage, cache_id, @@ -2025,7 +2025,7 @@ iris_update_compiled_vs(struct iris_context *ice) * Get the shader_info for a given stage, or NULL if the stage is disabled. */ const struct shader_info * -iris_get_shader_info(const struct iris_context *ice, gl_shader_stage stage) +iris_get_shader_info(const struct iris_context *ice, mesa_shader_stage stage) { const struct iris_uncompiled_shader *ish = ice->shaders.uncompiled[stage]; @@ -2874,7 +2874,7 @@ update_last_vue_map(struct iris_context *ice, static void iris_update_pull_constant_descriptors(struct iris_context *ice, - gl_shader_stage stage) + mesa_shader_stage stage) { struct iris_compiled_shader *shader = ice->shaders.prog[stage]; @@ -2967,7 +2967,7 @@ iris_update_compiled_shaders(struct iris_context *ice) } } - gl_shader_stage last_stage = last_vue_stage(ice); + mesa_shader_stage last_stage = last_vue_stage(ice); struct iris_compiled_shader *shader = ice->shaders.prog[last_stage]; struct iris_uncompiled_shader *ish = ice->shaders.uncompiled[last_stage]; update_last_vue_map(ice, shader); @@ -3170,7 +3170,7 @@ iris_fill_cs_push_const_buffer(struct iris_screen *screen, struct iris_bo * iris_get_scratch_space(struct iris_context *ice, unsigned per_thread_scratch, - gl_shader_stage stage) + mesa_shader_stage stage) { struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen; struct iris_bufmgr *bufmgr = screen->bufmgr; @@ -3613,7 +3613,7 @@ iris_delete_shader_state(struct pipe_context *ctx, void *state) struct iris_uncompiled_shader *ish = state; struct iris_context *ice = (void *) ctx; - const gl_shader_stage stage = ish->nir->info.stage; + const mesa_shader_stage stage = ish->nir->info.stage; if (ice->shaders.uncompiled[stage] == ish) { ice->shaders.uncompiled[stage] = NULL; @@ -3633,7 +3633,7 @@ iris_delete_shader_state(struct pipe_context *ctx, void *state) static void bind_shader_state(struct iris_context *ice, struct iris_uncompiled_shader *ish, - gl_shader_stage stage) + mesa_shader_stage stage) { uint64_t stage_dirty_bit = IRIS_STAGE_DIRTY_UNCOMPILED_VS << stage; const uint64_t nos = ish ? ish->nos : 0; @@ -4004,7 +4004,7 @@ iris_get_compiler_options(struct pipe_screen *pscreen, enum pipe_shader_type pstage) { struct iris_screen *screen = (struct iris_screen *) pscreen; - gl_shader_stage stage = stage_from_pipe(pstage); + mesa_shader_stage stage = stage_from_pipe(pstage); #ifdef INTEL_USE_ELK return screen->brw ? screen->brw->nir_options[stage] diff --git a/src/gallium/drivers/iris/iris_program_cache.c b/src/gallium/drivers/iris/iris_program_cache.c index fd0a07744b9..451368e7e40 100644 --- a/src/gallium/drivers/iris/iris_program_cache.c +++ b/src/gallium/drivers/iris/iris_program_cache.c @@ -113,7 +113,7 @@ iris_delete_shader_variant(struct iris_compiled_shader *shader) struct iris_compiled_shader * iris_create_shader_variant(const struct iris_screen *screen, void *mem_ctx, - gl_shader_stage stage, + mesa_shader_stage stage, enum iris_program_cache_id cache_id, uint32_t key_size, const void *key) diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index 0ff5eebfe4b..ec03fc46f8c 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -175,7 +175,7 @@ void iris_predraw_resolve_inputs(struct iris_context *ice, struct iris_batch *batch, bool *draw_aux_buffer_disabled, - gl_shader_stage stage, + mesa_shader_stage stage, bool consider_framebuffer) { struct iris_shader_state *shs = &ice->state.shaders[stage]; @@ -288,7 +288,7 @@ iris_predraw_resolve_framebuffer(struct iris_context *ice, void iris_postdraw_update_image_resolve_tracking(struct iris_context *ice, - gl_shader_stage stage) + mesa_shader_stage stage) { struct iris_screen *screen = (void *) ice->ctx.screen; ASSERTED const struct intel_device_info *devinfo = screen->devinfo; @@ -389,7 +389,7 @@ iris_postdraw_update_resolve_tracking(struct iris_context *ice) } if (devinfo->ver >= 12) { - for (gl_shader_stage stage = 0; stage < MESA_SHADER_COMPUTE; stage++) { + for (mesa_shader_stage stage = 0; stage < MESA_SHADER_COMPUTE; stage++) { iris_postdraw_update_image_resolve_tracking(ice, stage); } } @@ -479,7 +479,7 @@ flush_ssbos(struct iris_batch *batch, void iris_predraw_flush_buffers(struct iris_context *ice, struct iris_batch *batch, - gl_shader_stage stage) + mesa_shader_stage stage) { struct iris_shader_state *shs = &ice->state.shaders[stage]; diff --git a/src/gallium/drivers/iris/iris_screen.h b/src/gallium/drivers/iris/iris_screen.h index 927d20e0ce1..c9bbeded842 100644 --- a/src/gallium/drivers/iris/iris_screen.h +++ b/src/gallium/drivers/iris/iris_screen.h @@ -139,17 +139,17 @@ struct iris_vtable { const struct intel_vue_map *vue_map); void (*populate_vs_key)(const struct iris_context *ice, const struct shader_info *info, - gl_shader_stage last_stage, + mesa_shader_stage last_stage, struct iris_vs_prog_key *key); void (*populate_tcs_key)(const struct iris_context *ice, struct iris_tcs_prog_key *key); void (*populate_tes_key)(const struct iris_context *ice, const struct shader_info *info, - gl_shader_stage last_stage, + mesa_shader_stage last_stage, struct iris_tes_prog_key *key); void (*populate_gs_key)(const struct iris_context *ice, const struct shader_info *info, - gl_shader_stage last_stage, + mesa_shader_stage last_stage, struct iris_gs_prog_key *key); void (*populate_fs_key)(const struct iris_context *ice, const struct shader_info *info, diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index cfd03e210d9..76f2cb2e0e6 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -2628,7 +2628,7 @@ iris_bind_sampler_states(struct pipe_context *ctx, void **states) { struct iris_context *ice = (struct iris_context *) ctx; - gl_shader_stage stage = stage_from_pipe(p_stage); + mesa_shader_stage stage = stage_from_pipe(p_stage); struct iris_shader_state *shs = &ice->state.shaders[stage]; assert(start + count <= IRIS_MAX_SAMPLERS); @@ -2654,7 +2654,7 @@ iris_bind_sampler_states(struct pipe_context *ctx, * Also fill out the border color state pointers. */ static void -iris_upload_sampler_states(struct iris_context *ice, gl_shader_stage stage) +iris_upload_sampler_states(struct iris_context *ice, mesa_shader_stage stage) { struct iris_screen *screen = (struct iris_screen *) ice->ctx.screen; struct iris_compiled_shader *shader = ice->shaders.prog[stage]; @@ -3364,7 +3364,7 @@ iris_set_shader_images(struct pipe_context *ctx, { struct iris_context *ice = (struct iris_context *) ctx; struct iris_screen *screen = (struct iris_screen *)ctx->screen; - gl_shader_stage stage = stage_from_pipe(p_stage); + mesa_shader_stage stage = stage_from_pipe(p_stage); struct iris_shader_state *shs = &ice->state.shaders[stage]; #if GFX_VER == 8 struct iris_genx_state *genx = ice->state.genx; @@ -3513,7 +3513,7 @@ iris_set_sampler_views(struct pipe_context *ctx, struct iris_context *ice = (struct iris_context *) ctx; UNUSED struct iris_screen *screen = (void *) ctx->screen; UNUSED const struct intel_device_info *devinfo = screen->devinfo; - gl_shader_stage stage = stage_from_pipe(p_stage); + mesa_shader_stage stage = stage_from_pipe(p_stage); struct iris_shader_state *shs = &ice->state.shaders[stage]; unsigned i; @@ -3953,7 +3953,7 @@ iris_set_constant_buffer(struct pipe_context *ctx, const struct pipe_constant_buffer *input) { struct iris_context *ice = (struct iris_context *) ctx; - gl_shader_stage stage = stage_from_pipe(p_stage); + mesa_shader_stage stage = stage_from_pipe(p_stage); struct iris_shader_state *shs = &ice->state.shaders[stage]; struct pipe_shader_buffer *cbuf = &shs->constbuf[index]; @@ -4011,7 +4011,7 @@ iris_set_constant_buffer(struct pipe_context *ctx, static void upload_sysvals(struct iris_context *ice, - gl_shader_stage stage, + mesa_shader_stage stage, const struct pipe_grid_info *grid) { UNUSED struct iris_genx_state *genx = ice->state.genx; @@ -4114,7 +4114,7 @@ iris_set_shader_buffers(struct pipe_context *ctx, unsigned writable_bitmask) { struct iris_context *ice = (struct iris_context *) ctx; - gl_shader_stage stage = stage_from_pipe(p_stage); + mesa_shader_stage stage = stage_from_pipe(p_stage); struct iris_shader_state *shs = &ice->state.shaders[stage]; unsigned modified_bits = u_bit_consecutive(start_slot, count); @@ -4969,7 +4969,7 @@ iris_emit_sbe(struct iris_batch *batch, const struct iris_context *ice) static void iris_populate_vs_key(const struct iris_context *ice, const struct shader_info *info, - gl_shader_stage last_stage, + mesa_shader_stage last_stage, struct iris_vs_prog_key *key) { const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast; @@ -4995,7 +4995,7 @@ iris_populate_tcs_key(const struct iris_context *ice, static void iris_populate_tes_key(const struct iris_context *ice, const struct shader_info *info, - gl_shader_stage last_stage, + mesa_shader_stage last_stage, struct iris_tes_prog_key *key) { const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast; @@ -5012,7 +5012,7 @@ iris_populate_tes_key(const struct iris_context *ice, static void iris_populate_gs_key(const struct iris_context *ice, const struct shader_info *info, - gl_shader_stage last_stage, + mesa_shader_stage last_stage, struct iris_gs_prog_key *key) { const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast; @@ -5781,7 +5781,7 @@ use_image(struct iris_batch *batch, struct iris_context *ice, static void iris_populate_binding_table(struct iris_context *ice, struct iris_batch *batch, - gl_shader_stage stage, + mesa_shader_stage stage, bool pin_only) { const struct iris_binder *binder = &ice->state.binder; @@ -5936,7 +5936,7 @@ static uint32_t pin_scratch_space(struct iris_context *ice, struct iris_batch *batch, const struct iris_compiled_shader *shader, - gl_shader_stage stage) + mesa_shader_stage stage) { uint32_t scratch_addr = 0; @@ -6779,7 +6779,7 @@ static void shader_program_uses_primitive_id(struct iris_context *ice, struct iris_batch *batch, struct iris_compiled_shader *shader, - gl_shader_stage stage, + mesa_shader_stage stage, bool *uses_primitive_id) { switch (stage) { diff --git a/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp b/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp index 50da8bddb1e..bb644dee31e 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp @@ -7,7 +7,7 @@ #include "sfn_nir.h" bool -r600_lower_tess_io_filter(const nir_instr *instr, gl_shader_stage stage) +r600_lower_tess_io_filter(const nir_instr *instr, mesa_shader_stage stage) { if (instr->type != nir_instr_type_intrinsic) return false; diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c index 88daebb5fc9..14955ab880a 100644 --- a/src/gallium/drivers/radeonsi/si_debug.c +++ b/src/gallium/drivers/radeonsi/si_debug.c @@ -764,7 +764,7 @@ static unsigned si_identity(unsigned slot) return slot; } -static void si_dump_descriptors(struct si_context *sctx, gl_shader_stage stage, +static void si_dump_descriptors(struct si_context *sctx, mesa_shader_stage stage, const struct si_shader_info *info, struct u_log_context *log) { struct si_descriptors *descs = @@ -843,7 +843,7 @@ struct si_shader_inst { static void si_add_split_disasm(struct si_screen *screen, struct ac_rtld_binary *rtld_binary, struct si_shader_binary *binary, uint64_t *addr, unsigned *num, struct si_shader_inst *instructions, - gl_shader_stage stage, unsigned wave_size) + mesa_shader_stage stage, unsigned wave_size) { if (!ac_rtld_open(rtld_binary, (struct ac_rtld_open_info){ .info = &screen->info, @@ -895,7 +895,7 @@ static void si_print_annotated_shader(struct si_shader *shader, struct ac_wave_i return; struct si_screen *screen = shader->selector->screen; - gl_shader_stage stage = shader->selector->stage; + mesa_shader_stage stage = shader->selector->stage; uint64_t start_addr = shader->bo->gpu_address; uint64_t end_addr = start_addr + shader->bo->b.b.width0; unsigned i; diff --git a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c index 086dfb63307..95d93524ee9 100644 --- a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c +++ b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c @@ -231,7 +231,7 @@ static bool lower_intrinsic(nir_builder *b, nir_instr *instr, struct lower_abi_s struct si_shader_args *args = s->args; struct si_shader_selector *sel = shader->selector; union si_shader_key *key = &shader->key; - gl_shader_stage stage = b->shader->info.stage; + mesa_shader_stage stage = b->shader->info.stage; b->cursor = nir_before_instr(instr); diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 8739fee856c..0c7302fbbb7 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -115,7 +115,7 @@ unsigned si_shader_io_get_unique_index(unsigned semantic) unsigned si_get_max_workgroup_size(const struct si_shader *shader) { - gl_shader_stage stage = shader->is_gs_copy_shader ? + mesa_shader_stage stage = shader->is_gs_copy_shader ? MESA_SHADER_VERTEX : shader->selector->stage; assert(shader->wave_size); @@ -159,7 +159,7 @@ unsigned si_get_max_workgroup_size(const struct si_shader *shader) return max_work_group_size; } -static unsigned get_lds_granularity(struct si_screen *screen, gl_shader_stage stage) +static unsigned get_lds_granularity(struct si_screen *screen, mesa_shader_stage stage) { return screen->info.gfx_level >= GFX11 && stage == MESA_SHADER_FRAGMENT ? 1024 : screen->info.gfx_level >= GFX7 ? 512 : 256; @@ -422,7 +422,7 @@ static int upload_binary_elf(struct si_screen *sscreen, struct si_shader *shader static void calculate_needed_lds_size(struct si_screen *sscreen, struct si_shader *shader) { - gl_shader_stage stage = + mesa_shader_stage stage = shader->is_gs_copy_shader ? MESA_SHADER_VERTEX : shader->selector->stage; if (sscreen->info.gfx_level >= GFX9 && stage <= MESA_SHADER_GEOMETRY && @@ -564,7 +564,7 @@ static void print_disassembly(const char *disasm, size_t nbytes, static void si_shader_dump_disassembly(struct si_screen *screen, const struct si_shader_binary *binary, - gl_shader_stage stage, unsigned wave_size, + mesa_shader_stage stage, unsigned wave_size, struct util_debug_callback *debug, const char *name, FILE *file) { @@ -728,7 +728,7 @@ void si_shader_dump_stats_for_shader_db(struct si_screen *screen, struct si_shad stages[shader->selector->stage], shader->wave_size); } -bool si_can_dump_shader(struct si_screen *sscreen, gl_shader_stage stage, +bool si_can_dump_shader(struct si_screen *sscreen, mesa_shader_stage stage, enum si_shader_dump_type dump_type) { static uint64_t filter[] = { @@ -818,7 +818,7 @@ const char *si_get_shader_name(const struct si_shader *shader) void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader, struct util_debug_callback *debug, FILE *file, bool check_debug_option) { - gl_shader_stage stage = shader->selector->stage; + mesa_shader_stage stage = shader->selector->stage; if (!check_debug_option || si_can_dump_shader(sscreen, stage, SI_DUMP_SHADER_KEY)) si_dump_shader_key(shader, file); @@ -878,7 +878,7 @@ static void si_dump_shader_key_vs(const union si_shader_key *key, FILE *f) static void si_dump_shader_key(const struct si_shader *shader, FILE *f) { const union si_shader_key *key = &shader->key; - gl_shader_stage stage = shader->selector->stage; + mesa_shader_stage stage = shader->selector->stage; fprintf(f, "SHADER KEY\n"); fprintf(f, " source_blake3 = {"); @@ -2101,7 +2101,7 @@ out: */ static struct si_shader_part * si_get_shader_part(struct si_screen *sscreen, struct si_shader_part **list, - gl_shader_stage stage, bool prolog, union si_shader_part_key *key, + mesa_shader_stage stage, bool prolog, union si_shader_part_key *key, struct ac_llvm_compiler *compiler, struct util_debug_callback *debug, const char *name) { diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index c68a9d62215..6f5f5070a9a 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -470,7 +470,7 @@ struct si_shader_selector { struct si_screen *screen; struct util_queue_fence ready; struct si_compiler_ctx_state compiler_ctx_state; - gl_shader_stage stage; + mesa_shader_stage stage; simple_mtx_t mutex; union si_shader_key *keys; @@ -900,7 +900,7 @@ int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader, uint64_t scratch_va); int si_shader_binary_upload_at(struct si_screen *sscreen, struct si_shader *shader, uint64_t scratch_va, int64_t bo_offset); -bool si_can_dump_shader(struct si_screen *sscreen, gl_shader_stage stage, +bool si_can_dump_shader(struct si_screen *sscreen, mesa_shader_stage stage, enum si_shader_dump_type dump_type); void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader, struct util_debug_callback *debug, FILE *f, bool check_debug_option); diff --git a/src/gallium/drivers/radeonsi/si_shader_aco.c b/src/gallium/drivers/radeonsi/si_shader_aco.c index 3d0a9180482..3a8fd30fa45 100644 --- a/src/gallium/drivers/radeonsi/si_shader_aco.c +++ b/src/gallium/drivers/radeonsi/si_shader_aco.c @@ -38,8 +38,8 @@ si_aco_compiler_debug(void *private_data, enum aco_compiler_debug_level level, } static void -si_fill_aco_options(struct si_screen *screen, gl_shader_stage stage, - gl_shader_stage next_merged_stage, struct aco_compiler_options *options, +si_fill_aco_options(struct si_screen *screen, mesa_shader_stage stage, + mesa_shader_stage next_merged_stage, struct aco_compiler_options *options, struct util_debug_callback *debug) { options->dump_ir = si_can_dump_shader(screen, stage, SI_DUMP_ACO_IR); @@ -68,7 +68,7 @@ si_fill_aco_shader_info(struct si_shader *shader, struct aco_shader_info *info, const struct si_shader_selector *sel = shader->selector; const union si_shader_key *key = &shader->key; const enum amd_gfx_level gfx_level = sel->screen->info.gfx_level; - gl_shader_stage stage = shader->is_gs_copy_shader ? MESA_SHADER_VERTEX : sel->stage; + mesa_shader_stage stage = shader->is_gs_copy_shader ? MESA_SHADER_VERTEX : sel->stage; info->wave_size = shader->wave_size; info->workgroup_size = si_get_max_workgroup_size(shader); @@ -151,7 +151,7 @@ si_aco_compile_shader(struct si_shader *shader, struct si_linked_shaders *linked { const struct si_shader_selector *sel = shader->selector; nir_shader *nir = linked->consumer.nir; - gl_shader_stage next_merged_stage = MESA_SHADER_NONE; + mesa_shader_stage next_merged_stage = MESA_SHADER_NONE; if (nir->info.stage <= MESA_SHADER_GEOMETRY) { if (shader->key.ge.as_ls) @@ -331,7 +331,7 @@ si_aco_build_ps_epilog(struct aco_compiler_options *options, } bool -si_aco_build_shader_part(struct si_screen *screen, gl_shader_stage stage, bool prolog, +si_aco_build_shader_part(struct si_screen *screen, mesa_shader_stage stage, bool prolog, struct util_debug_callback *debug, const char *name, struct si_shader_part *result) { diff --git a/src/gallium/drivers/radeonsi/si_shader_info.c b/src/gallium/drivers/radeonsi/si_shader_info.c index 1ba550bec53..499807d8491 100644 --- a/src/gallium/drivers/radeonsi/si_shader_info.c +++ b/src/gallium/drivers/radeonsi/si_shader_info.c @@ -668,7 +668,7 @@ void si_nir_scan_shader(struct si_screen *sscreen, struct nir_shader *nir, } enum ac_hw_stage -si_select_hw_stage(const gl_shader_stage stage, const union si_shader_key *const key, +si_select_hw_stage(const mesa_shader_stage stage, const union si_shader_key *const key, const enum amd_gfx_level gfx_level) { switch (stage) { diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h index 3c876f10054..f16b82005b4 100644 --- a/src/gallium/drivers/radeonsi/si_shader_internal.h +++ b/src/gallium/drivers/radeonsi/si_shader_internal.h @@ -93,7 +93,7 @@ typedef struct nir_shader nir_shader; bool si_is_multi_part_shader(struct si_shader *shader); bool si_is_merged_shader(struct si_shader *shader); unsigned si_get_max_workgroup_size(const struct si_shader *shader); -enum ac_hw_stage si_select_hw_stage(const gl_shader_stage stage, const union si_shader_key *const key, +enum ac_hw_stage si_select_hw_stage(const mesa_shader_stage stage, const union si_shader_key *const key, const enum amd_gfx_level gfx_level); bool gfx10_ngg_export_prim_early(struct si_shader *shader); @@ -131,7 +131,7 @@ bool si_nir_mark_divergent_texture_non_uniform(struct nir_shader *nir); bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compiler, struct si_shader *shader, struct si_linked_shaders *linked, struct util_debug_callback *debug); -bool si_llvm_build_shader_part(struct si_screen *sscreen, gl_shader_stage stage, +bool si_llvm_build_shader_part(struct si_screen *sscreen, mesa_shader_stage stage, bool prolog, struct ac_llvm_compiler *compiler, struct util_debug_callback *debug, const char *name, struct si_shader_part *result); @@ -142,7 +142,7 @@ bool si_aco_compile_shader(struct si_shader *shader, struct si_linked_shaders *l void si_aco_resolve_symbols(struct si_shader *shader, uint32_t *code_for_write, const uint32_t *code_for_read, uint64_t scratch_va, uint32_t const_offset); -bool si_aco_build_shader_part(struct si_screen *screen, gl_shader_stage stage, bool prolog, +bool si_aco_build_shader_part(struct si_screen *screen, mesa_shader_stage stage, bool prolog, struct util_debug_callback *debug, const char *name, struct si_shader_part *result); diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c index cb183aaa018..3cbec83cdca 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c @@ -56,7 +56,7 @@ static void si_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context) static bool si_compile_llvm(struct si_screen *sscreen, struct si_shader_binary *binary, struct ac_shader_config *conf, struct ac_llvm_compiler *compiler, struct ac_llvm_context *ac, struct util_debug_callback *debug, - gl_shader_stage stage, const char *name) + mesa_shader_stage stage, const char *name) { unsigned count = p_atomic_inc_return(&sscreen->num_compilations); @@ -131,7 +131,7 @@ void si_llvm_create_func(struct si_shader_context *ctx, const char *name, LLVMTy else ret_type = ctx->ac.voidt; - gl_shader_stage real_stage = ctx->stage; + mesa_shader_stage real_stage = ctx->stage; /* LS is merged into HS (TCS), and ES is merged into GS. */ if (ctx->screen->info.gfx_level >= GFX9 && ctx->stage <= MESA_SHADER_GEOMETRY) { @@ -679,7 +679,7 @@ bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler * return true; } -bool si_llvm_build_shader_part(struct si_screen *sscreen, gl_shader_stage stage, +bool si_llvm_build_shader_part(struct si_screen *sscreen, mesa_shader_stage stage, bool prolog, struct ac_llvm_compiler *compiler, struct util_debug_callback *debug, const char *name, struct si_shader_part *result) diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.h b/src/gallium/drivers/radeonsi/si_shader_llvm.h index 019b71b6368..f87e520fa5a 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm.h +++ b/src/gallium/drivers/radeonsi/si_shader_llvm.h @@ -20,7 +20,7 @@ struct si_shader_context { struct si_shader *shader; struct si_screen *screen; - gl_shader_stage stage; + mesa_shader_stage stage; struct si_shader_args *args; struct ac_shader_abi abi; diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c index 31a795317f2..0229ca741de 100644 --- a/src/gallium/drivers/radeonsi/si_shader_nir.c +++ b/src/gallium/drivers/radeonsi/si_shader_nir.c @@ -237,8 +237,8 @@ static bool si_lower_intrinsics(nir_shader *nir) NULL); } -static bool can_lower_mediump_io(gl_shader_stage prev_stage, bool prev_stage_has_xfb, - gl_shader_stage next_stage, bool config_option) +static bool can_lower_mediump_io(mesa_shader_stage prev_stage, bool prev_stage_has_xfb, + mesa_shader_stage next_stage, bool config_option) { /* This is the filter that determines when mediump IO is lowered. * diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index 615a07df030..24463237010 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -652,7 +652,7 @@ void si_init_screen_live_shader_cache(struct si_screen *sscreen); void si_init_shader_functions(struct si_context *sctx); bool si_init_shader_cache(struct si_screen *sscreen); void si_destroy_shader_cache(struct si_screen *sscreen); -void si_schedule_initial_compile(struct si_context *sctx, gl_shader_stage stage, +void si_schedule_initial_compile(struct si_context *sctx, mesa_shader_stage stage, struct util_queue_fence *ready_fence, struct si_compiler_ctx_state *compiler_ctx_state, void *job, util_queue_execute_func execute); diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index 88bd7137d0e..86d84230ddd 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -27,7 +27,7 @@ static void si_update_tess_in_out_patch_vertices(struct si_context *sctx); unsigned si_determine_wave_size(struct si_screen *sscreen, struct si_shader *shader) { struct si_shader_info *info = &shader->selector->info; - gl_shader_stage stage = shader->selector->stage; + mesa_shader_stage stage = shader->selector->stage; struct si_shader_selector *prev_sel = NULL; if (stage == MESA_SHADER_TESS_CTRL) @@ -988,7 +988,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) if (sscreen->info.gfx_level >= GFX9) { unsigned input_prim = sel->info.base.gs.input_primitive; - gl_shader_stage es_stage = shader->key.ge.part.gs.es->stage; + mesa_shader_stage es_stage = shader->key.ge.part.gs.es->stage; unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt; if (es_stage == MESA_SHADER_VERTEX) { @@ -1397,11 +1397,11 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader { const struct si_shader_selector *gs_sel = shader->selector; const struct si_shader_info *gs_info = &gs_sel->info; - const gl_shader_stage gs_stage = shader->selector->stage; + const mesa_shader_stage gs_stage = shader->selector->stage; const struct si_shader_selector *es_sel = shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector; const struct si_shader_info *es_info = &es_sel->info; - const gl_shader_stage es_stage = es_sel->stage; + const mesa_shader_stage es_stage = es_sel->stage; unsigned num_user_sgprs; unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt; uint64_t va; @@ -3266,7 +3266,7 @@ int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state static void si_parse_next_shader_property(nir_shader *nir, union si_shader_key *key) { - gl_shader_stage next_shader = nir->info.next_stage; + mesa_shader_stage next_shader = nir->info.next_stage; bool writes_position = nir->info.outputs_written & VARYING_BIT_POS; assert(!nir->xfb_info || nir->xfb_info->buffers_written); @@ -3411,7 +3411,7 @@ static void si_init_shader_selector_async(void *job, void *gdata, int thread_ind sel->nir = NULL; } -void si_schedule_initial_compile(struct si_context *sctx, gl_shader_stage stage, +void si_schedule_initial_compile(struct si_context *sctx, mesa_shader_stage stage, struct util_queue_fence *ready_fence, struct si_compiler_ctx_state *compiler_ctx_state, void *job, util_queue_execute_func execute) diff --git a/src/gallium/drivers/v3d/v3d_disk_cache.c b/src/gallium/drivers/v3d/v3d_disk_cache.c index 51587b1abb3..b7eb1b7ab1e 100644 --- a/src/gallium/drivers/v3d/v3d_disk_cache.c +++ b/src/gallium/drivers/v3d/v3d_disk_cache.c @@ -34,7 +34,7 @@ #ifdef ENABLE_SHADER_CACHE static uint32_t -v3d_key_size(gl_shader_stage stage) +v3d_key_size(mesa_shader_stage stage) { static const int key_size[] = { [MESA_SHADER_VERTEX] = sizeof(struct v3d_vs_key), diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c index 6bec5105d40..674e19d6218 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c +++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c @@ -52,7 +52,7 @@ struct ntv_context { SpvId GLSL_std_450; - gl_shader_stage stage; + mesa_shader_stage stage; const struct zink_shader_info *sinfo; SpvId ubos[PIPE_MAX_CONSTANT_BUFFERS][5]; //8, 16, 32, unused, 64 diff --git a/src/gallium/drivers/zink/zink_compiler.c b/src/gallium/drivers/zink/zink_compiler.c index 98483f35a83..4512498a94e 100644 --- a/src/gallium/drivers/zink/zink_compiler.c +++ b/src/gallium/drivers/zink/zink_compiler.c @@ -2583,7 +2583,7 @@ assign_track_slot_mask(struct io_slot_map *io, nir_variable *var, unsigned slot, } static void -assign_slot_io(gl_shader_stage stage, struct io_slot_map *io, nir_variable *var, unsigned slot) +assign_slot_io(mesa_shader_stage stage, struct io_slot_map *io, nir_variable *var, unsigned slot) { unsigned num_slots; if (nir_is_arrayed_io(var, stage)) @@ -2602,7 +2602,7 @@ assign_slot_io(gl_shader_stage stage, struct io_slot_map *io, nir_variable *var, } static void -assign_producer_var_io(gl_shader_stage stage, nir_variable *var, struct io_slot_map *io) +assign_producer_var_io(mesa_shader_stage stage, nir_variable *var, struct io_slot_map *io) { unsigned slot = var->data.location; switch (slot) { @@ -2637,7 +2637,7 @@ assign_producer_var_io(gl_shader_stage stage, nir_variable *var, struct io_slot_ } ALWAYS_INLINE static bool -is_texcoord(gl_shader_stage stage, const nir_variable *var) +is_texcoord(mesa_shader_stage stage, const nir_variable *var) { if (stage != MESA_SHADER_FRAGMENT) return false; @@ -2646,7 +2646,7 @@ is_texcoord(gl_shader_stage stage, const nir_variable *var) } static bool -assign_consumer_var_io(gl_shader_stage stage, nir_variable *var, struct io_slot_map *io) +assign_consumer_var_io(mesa_shader_stage stage, nir_variable *var, struct io_slot_map *io) { unsigned slot = var->data.location; switch (slot) { @@ -3291,7 +3291,7 @@ zink_shader_dump(const struct zink_shader *zs, void *words, size_t size, const c } static VkShaderStageFlagBits -zink_get_next_stage(gl_shader_stage stage) +zink_get_next_stage(mesa_shader_stage stage) { switch (stage) { case MESA_SHADER_VERTEX: @@ -4513,7 +4513,7 @@ lower_bindless_io(nir_shader *shader) } static uint32_t -zink_binding(gl_shader_stage stage, VkDescriptorType type, int index, bool compact_descriptors) +zink_binding(mesa_shader_stage stage, VkDescriptorType type, int index, bool compact_descriptors) { if (stage == MESA_SHADER_NONE) { UNREACHABLE("not supported"); @@ -5144,7 +5144,7 @@ struct rework_io_state { bool indirect_only; unsigned location; nir_variable_mode mode; - gl_shader_stage stage; + mesa_shader_stage stage; nir_shader *nir; const char *name; @@ -6433,7 +6433,7 @@ gfx_shader_prune(struct zink_screen *screen, struct zink_shader *shader) simple_mtx_unlock(&shader->lock); if (!prog) return false; - gl_shader_stage stage = shader->info.stage; + mesa_shader_stage stage = shader->info.stage; assert(stage < ZINK_GFX_SHADER_COUNT); util_queue_fence_wait(&prog->base.cache_fence); unsigned stages_present = prog->stages_present; diff --git a/src/gallium/drivers/zink/zink_compiler.h b/src/gallium/drivers/zink/zink_compiler.h index 36f31309c65..5830046bef5 100644 --- a/src/gallium/drivers/zink/zink_compiler.h +++ b/src/gallium/drivers/zink/zink_compiler.h @@ -43,7 +43,7 @@ struct spirv_shader; struct tgsi_token; -static inline gl_shader_stage +static inline mesa_shader_stage clamp_stage(const shader_info *info) { return info->stage == MESA_SHADER_KERNEL ? MESA_SHADER_COMPUTE : info->stage; diff --git a/src/gallium/drivers/zink/zink_context.c b/src/gallium/drivers/zink/zink_context.c index 010555ce4d9..8a47f99e71e 100644 --- a/src/gallium/drivers/zink/zink_context.c +++ b/src/gallium/drivers/zink/zink_context.c @@ -619,7 +619,7 @@ get_layout_for_binding(const struct zink_context *ctx, struct zink_resource *res } ALWAYS_INLINE static struct zink_surface * -get_imageview_for_binding(struct zink_context *ctx, gl_shader_stage stage, enum zink_descriptor_type type, unsigned idx, enum pipe_format *format) +get_imageview_for_binding(struct zink_context *ctx, mesa_shader_stage stage, enum zink_descriptor_type type, unsigned idx, enum pipe_format *format) { switch (type) { case ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW: { @@ -651,7 +651,7 @@ get_imageview_for_binding(struct zink_context *ctx, gl_shader_stage stage, enum } ALWAYS_INLINE static struct zink_buffer_view * -get_bufferview_for_binding(struct zink_context *ctx, gl_shader_stage stage, enum zink_descriptor_type type, unsigned idx) +get_bufferview_for_binding(struct zink_context *ctx, mesa_shader_stage stage, enum zink_descriptor_type type, unsigned idx) { switch (type) { case ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW: { @@ -670,7 +670,7 @@ get_bufferview_for_binding(struct zink_context *ctx, gl_shader_stage stage, enum } ALWAYS_INLINE static struct zink_resource * -update_descriptor_state_ubo_db(struct zink_context *ctx, gl_shader_stage shader, unsigned slot, struct zink_resource *res) +update_descriptor_state_ubo_db(struct zink_context *ctx, mesa_shader_stage shader, unsigned slot, struct zink_resource *res) { struct zink_screen *screen = zink_screen(ctx->base.screen); ctx->di.descriptor_res[ZINK_DESCRIPTOR_TYPE_UBO][shader][slot] = res; @@ -692,7 +692,7 @@ update_descriptor_state_ubo_db(struct zink_context *ctx, gl_shader_stage shader, } ALWAYS_INLINE static struct zink_resource * -update_descriptor_state_ubo_lazy(struct zink_context *ctx, gl_shader_stage shader, unsigned slot, struct zink_resource *res) +update_descriptor_state_ubo_lazy(struct zink_context *ctx, mesa_shader_stage shader, unsigned slot, struct zink_resource *res) { struct zink_screen *screen = zink_screen(ctx->base.screen); ctx->di.t.ubos[shader][slot].offset = ctx->ubos[shader][slot].buffer_offset; @@ -715,7 +715,7 @@ update_descriptor_state_ubo_lazy(struct zink_context *ctx, gl_shader_stage shade } ALWAYS_INLINE static struct zink_resource * -update_descriptor_state_ssbo_db(struct zink_context *ctx, gl_shader_stage shader, unsigned slot, struct zink_resource *res) +update_descriptor_state_ssbo_db(struct zink_context *ctx, mesa_shader_stage shader, unsigned slot, struct zink_resource *res) { ctx->di.descriptor_res[ZINK_DESCRIPTOR_TYPE_SSBO][shader][slot] = res; if (res) { @@ -729,7 +729,7 @@ update_descriptor_state_ssbo_db(struct zink_context *ctx, gl_shader_stage shader } ALWAYS_INLINE static struct zink_resource * -update_descriptor_state_ssbo_lazy(struct zink_context *ctx, gl_shader_stage shader, unsigned slot, struct zink_resource *res) +update_descriptor_state_ssbo_lazy(struct zink_context *ctx, mesa_shader_stage shader, unsigned slot, struct zink_resource *res) { ctx->di.t.ssbos[shader][slot].offset = ctx->ssbos[shader][slot].buffer_offset; ctx->di.descriptor_res[ZINK_DESCRIPTOR_TYPE_SSBO][shader][slot] = res; @@ -751,7 +751,7 @@ sampler_surface_needs_clamped(enum pipe_format format) } ALWAYS_INLINE static struct zink_resource * -update_descriptor_state_sampler(struct zink_context *ctx, gl_shader_stage shader, unsigned slot, struct zink_resource *res) +update_descriptor_state_sampler(struct zink_context *ctx, mesa_shader_stage shader, unsigned slot, struct zink_resource *res) { struct zink_screen *screen = zink_screen(ctx->base.screen); const enum zink_descriptor_type type = ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW; @@ -804,7 +804,7 @@ zink_update_shadow_samplerviews(struct zink_context *ctx, unsigned mask) } ALWAYS_INLINE static struct zink_resource * -update_descriptor_state_image(struct zink_context *ctx, gl_shader_stage shader, unsigned slot, struct zink_resource *res) +update_descriptor_state_image(struct zink_context *ctx, mesa_shader_stage shader, unsigned slot, struct zink_resource *res) { struct zink_screen *screen = zink_screen(ctx->base.screen); const enum zink_descriptor_type type = ZINK_DESCRIPTOR_TYPE_IMAGE; @@ -838,7 +838,7 @@ update_descriptor_state_image(struct zink_context *ctx, gl_shader_stage shader, } static void -update_nonseamless_shader_key(struct zink_context *ctx, gl_shader_stage pstage) +update_nonseamless_shader_key(struct zink_context *ctx, mesa_shader_stage pstage) { const uint32_t new_mask = ctx->di.emulate_nonseamless[pstage] & ctx->di.cubes[pstage]; if (pstage == MESA_SHADER_COMPUTE) { @@ -853,7 +853,7 @@ update_nonseamless_shader_key(struct zink_context *ctx, gl_shader_stage pstage) static void zink_bind_sampler_states(struct pipe_context *pctx, - gl_shader_stage shader, + mesa_shader_stage shader, unsigned start_slot, unsigned num_samplers, void **samplers) @@ -883,7 +883,7 @@ zink_bind_sampler_states(struct pipe_context *pctx, static void zink_bind_sampler_states_nonseamless(struct pipe_context *pctx, - gl_shader_stage shader, + mesa_shader_stage shader, unsigned start_slot, unsigned num_samplers, void **samplers) @@ -1460,7 +1460,7 @@ zink_set_scissor_states(struct pipe_context *pctx, static void zink_set_inlinable_constants(struct pipe_context *pctx, - gl_shader_stage shader, + mesa_shader_stage shader, uint num_values, uint32_t *values) { struct zink_context *ctx = (struct zink_context *)pctx; @@ -1491,21 +1491,21 @@ zink_set_inlinable_constants(struct pipe_context *pctx, } ALWAYS_INLINE static void -unbind_descriptor_stage(struct zink_resource *res, gl_shader_stage pstage) +unbind_descriptor_stage(struct zink_resource *res, mesa_shader_stage pstage) { if (!res->sampler_binds[pstage] && !res->image_binds[pstage] && !res->all_bindless) res->gfx_barrier &= ~zink_pipeline_flags_from_pipe_stage(pstage); } ALWAYS_INLINE static void -unbind_buffer_descriptor_stage(struct zink_resource *res, gl_shader_stage pstage) +unbind_buffer_descriptor_stage(struct zink_resource *res, mesa_shader_stage pstage) { if (!res->ubo_bind_mask[pstage] && !res->ssbo_bind_mask[pstage]) unbind_descriptor_stage(res, pstage); } ALWAYS_INLINE static void -unbind_ubo(struct zink_context *ctx, struct zink_resource *res, gl_shader_stage pstage, unsigned slot) +unbind_ubo(struct zink_context *ctx, struct zink_resource *res, mesa_shader_stage pstage, unsigned slot) { if (!res) return; @@ -1518,7 +1518,7 @@ unbind_ubo(struct zink_context *ctx, struct zink_resource *res, gl_shader_stage } static void -invalidate_inlined_uniforms(struct zink_context *ctx, gl_shader_stage pstage) +invalidate_inlined_uniforms(struct zink_context *ctx, mesa_shader_stage pstage) { unsigned bit = BITFIELD_BIT(pstage); if (!(ctx->inlinable_uniforms_valid_mask & bit)) @@ -1536,7 +1536,7 @@ invalidate_inlined_uniforms(struct zink_context *ctx, gl_shader_stage pstage) ALWAYS_INLINE static void zink_set_constant_buffer_internal(struct pipe_context *pctx, - gl_shader_stage shader, uint index, + mesa_shader_stage shader, uint index, bool take_ownership, const struct pipe_constant_buffer *cb, bool use_db) @@ -1624,7 +1624,7 @@ zink_set_constant_buffer_internal(struct pipe_context *pctx, static void zink_set_constant_buffer_db(struct pipe_context *pctx, - gl_shader_stage shader, uint index, + mesa_shader_stage shader, uint index, bool take_ownership, const struct pipe_constant_buffer *cb) { @@ -1633,7 +1633,7 @@ zink_set_constant_buffer_db(struct pipe_context *pctx, static void zink_set_constant_buffer_lazy(struct pipe_context *pctx, - gl_shader_stage shader, uint index, + mesa_shader_stage shader, uint index, bool take_ownership, const struct pipe_constant_buffer *cb) { @@ -1655,7 +1655,7 @@ unbind_buffer_descriptor_reads(struct zink_resource *res, bool is_compute) } ALWAYS_INLINE static void -unbind_ssbo(struct zink_context *ctx, struct zink_resource *res, gl_shader_stage pstage, unsigned slot, bool writable) +unbind_ssbo(struct zink_context *ctx, struct zink_resource *res, mesa_shader_stage pstage, unsigned slot, bool writable) { if (!res) return; @@ -1672,7 +1672,7 @@ unbind_ssbo(struct zink_context *ctx, struct zink_resource *res, gl_shader_stage ALWAYS_INLINE static void zink_set_shader_buffers_internal(struct pipe_context *pctx, - gl_shader_stage p_stage, + mesa_shader_stage p_stage, unsigned start_slot, unsigned count, const struct pipe_shader_buffer *buffers, unsigned writable_bitmask, @@ -1751,7 +1751,7 @@ zink_set_shader_buffers_internal(struct pipe_context *pctx, static void zink_set_shader_buffers_db(struct pipe_context *pctx, - gl_shader_stage p_stage, + mesa_shader_stage p_stage, unsigned start_slot, unsigned count, const struct pipe_shader_buffer *buffers, unsigned writable_bitmask) @@ -1761,7 +1761,7 @@ zink_set_shader_buffers_db(struct pipe_context *pctx, static void zink_set_shader_buffers_lazy(struct pipe_context *pctx, - gl_shader_stage p_stage, + mesa_shader_stage p_stage, unsigned start_slot, unsigned count, const struct pipe_shader_buffer *buffers, unsigned writable_bitmask) @@ -1833,7 +1833,7 @@ check_for_layout_update(struct zink_context *ctx, struct zink_resource *res, boo } static void -unbind_shader_image(struct zink_context *ctx, gl_shader_stage stage, unsigned slot) +unbind_shader_image(struct zink_context *ctx, mesa_shader_stage stage, unsigned slot) { struct zink_image_view *image_view = &ctx->image_views[stage][slot]; bool is_compute = stage == MESA_SHADER_COMPUTE; @@ -1970,7 +1970,7 @@ bind_shaderimage_resource_stage(struct zink_context *ctx, const struct pipe_imag static void zink_set_shader_images(struct pipe_context *pctx, - gl_shader_stage shader_type, + mesa_shader_stage shader_type, unsigned start_slot, unsigned count, unsigned unbind_num_trailing_slots, const struct pipe_image_view *images) @@ -2147,7 +2147,7 @@ update_feedback_loop_state(struct zink_context *ctx, unsigned idx, unsigned feed } ALWAYS_INLINE static void -unbind_samplerview_res(struct zink_context *ctx, gl_shader_stage stage, unsigned slot, struct zink_resource *res) +unbind_samplerview_res(struct zink_context *ctx, mesa_shader_stage stage, unsigned slot, struct zink_resource *res) { bool general_layout = zink_screen(ctx->base.screen)->driver_workarounds.general_layout; res->sampler_bind_count[stage == MESA_SHADER_COMPUTE]--; @@ -2176,7 +2176,7 @@ unbind_samplerview_res(struct zink_context *ctx, gl_shader_stage stage, unsigned } ALWAYS_INLINE static void -unbind_samplerview(struct zink_context *ctx, gl_shader_stage stage, unsigned slot) +unbind_samplerview(struct zink_context *ctx, mesa_shader_stage stage, unsigned slot) { struct zink_sampler_view *sv = zink_sampler_view(ctx->sampler_views[stage][slot]); if (!sv || !sv->base.texture) @@ -2190,7 +2190,7 @@ unbind_samplerview(struct zink_context *ctx, gl_shader_stage stage, unsigned slo } static void -bind_samplerview_resource_stage(struct zink_context *ctx, struct zink_resource *res, gl_shader_stage shader_type) +bind_samplerview_resource_stage(struct zink_context *ctx, struct zink_resource *res, mesa_shader_stage shader_type) { update_res_bind_count(ctx, res, shader_type == MESA_SHADER_COMPUTE, false); res->sampler_bind_count[shader_type == MESA_SHADER_COMPUTE]++; @@ -2200,7 +2200,7 @@ bind_samplerview_resource_stage(struct zink_context *ctx, struct zink_resource * static void zink_set_sampler_views(struct pipe_context *pctx, - gl_shader_stage shader_type, + mesa_shader_stage shader_type, unsigned start_slot, unsigned num_views, unsigned unbind_num_trailing_slots, @@ -3442,7 +3442,7 @@ sync_flush(struct zink_context *ctx, struct zink_batch_state *bs) } static inline VkAccessFlags -get_access_flags_for_binding(struct zink_context *ctx, enum zink_descriptor_type type, gl_shader_stage stage, unsigned idx) +get_access_flags_for_binding(struct zink_context *ctx, enum zink_descriptor_type type, mesa_shader_stage stage, unsigned idx) { VkAccessFlags flags = 0; switch (type) { @@ -3472,7 +3472,7 @@ get_access_flags_for_binding(struct zink_context *ctx, enum zink_descriptor_type } static void -update_resource_refs_for_stage(struct zink_context *ctx, gl_shader_stage stage) +update_resource_refs_for_stage(struct zink_context *ctx, mesa_shader_stage stage) { unsigned max_slot[] = { [ZINK_DESCRIPTOR_TYPE_UBO] = ctx->di.num_ubos[stage], @@ -4419,7 +4419,7 @@ zink_set_stream_output_targets(struct pipe_context *pctx, } ALWAYS_INLINE static struct zink_resource * -rebind_ubo(struct zink_context *ctx, gl_shader_stage shader, unsigned slot) +rebind_ubo(struct zink_context *ctx, mesa_shader_stage shader, unsigned slot) { struct zink_resource *res; if (zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_DB) { @@ -4437,7 +4437,7 @@ rebind_ubo(struct zink_context *ctx, gl_shader_stage shader, unsigned slot) } ALWAYS_INLINE static struct zink_resource * -rebind_ssbo(struct zink_context *ctx, gl_shader_stage shader, unsigned slot) +rebind_ssbo(struct zink_context *ctx, mesa_shader_stage shader, unsigned slot) { const struct pipe_shader_buffer *ssbo = &ctx->ssbos[shader][slot]; struct zink_resource *res = zink_resource(ssbo->buffer); @@ -4464,7 +4464,7 @@ rebind_ssbo(struct zink_context *ctx, gl_shader_stage shader, unsigned slot) } ALWAYS_INLINE static struct zink_resource * -rebind_tbo(struct zink_context *ctx, gl_shader_stage shader, unsigned slot) +rebind_tbo(struct zink_context *ctx, mesa_shader_stage shader, unsigned slot) { struct zink_sampler_view *sampler_view = zink_sampler_view(ctx->sampler_views[shader][slot]); if (!sampler_view || sampler_view->base.texture->target != PIPE_BUFFER) @@ -4484,7 +4484,7 @@ rebind_tbo(struct zink_context *ctx, gl_shader_stage shader, unsigned slot) } ALWAYS_INLINE static struct zink_resource * -rebind_ibo(struct zink_context *ctx, gl_shader_stage shader, unsigned slot) +rebind_ibo(struct zink_context *ctx, mesa_shader_stage shader, unsigned slot) { struct zink_image_view *image_view = &ctx->image_views[shader][slot]; struct zink_resource *res = zink_resource(image_view->base.resource); @@ -5479,7 +5479,7 @@ zink_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags) if (is_robust && screen->driver_compiler_workarounds.lower_robustImageAccess2) { ctx->compute_pipeline_state.key.key.cs.robust_access = true; - for (gl_shader_stage pstage = MESA_SHADER_VERTEX; pstage < MESA_SHADER_FRAGMENT; pstage++) + for (mesa_shader_stage pstage = MESA_SHADER_VERTEX; pstage < MESA_SHADER_FRAGMENT; pstage++) ctx->gfx_pipeline_state.shader_keys.key[pstage].key.vs_base.robust_access = true; ctx->gfx_pipeline_state.shader_keys.key[MESA_SHADER_FRAGMENT].key.fs.robust_access = true; } @@ -5755,7 +5755,7 @@ add_implicit_feedback_loop(struct zink_context *ctx, struct zink_resource *res) continue; /* in-range VkPipelineStageFlagBits can be converted to VkShaderStageFlags with a bitshift */ - gl_shader_stage stage = vk_to_mesa_shader_stage((VkShaderStageFlagBits)(vkstagebit >> 3)); + mesa_shader_stage stage = vk_to_mesa_shader_stage((VkShaderStageFlagBits)(vkstagebit >> 3)); /* check against bound stages */ if (!ctx->gfx_stages[stage]) continue; diff --git a/src/gallium/drivers/zink/zink_context.h b/src/gallium/drivers/zink/zink_context.h index 5c664790dca..e7de56188d9 100644 --- a/src/gallium/drivers/zink/zink_context.h +++ b/src/gallium/drivers/zink/zink_context.h @@ -145,7 +145,7 @@ void zink_update_vk_sample_locations(struct zink_context *ctx); static inline VkPipelineStageFlags -zink_pipeline_flags_from_pipe_stage(gl_shader_stage pstage) +zink_pipeline_flags_from_pipe_stage(mesa_shader_stage pstage) { switch (pstage) { case MESA_SHADER_VERTEX: diff --git a/src/gallium/drivers/zink/zink_descriptors.c b/src/gallium/drivers/zink/zink_descriptors.c index d061ab74e50..968ea7d580e 100644 --- a/src/gallium/drivers/zink/zink_descriptors.c +++ b/src/gallium/drivers/zink/zink_descriptors.c @@ -324,7 +324,7 @@ init_db_template_entry(struct zink_screen *screen, struct zink_shader *shader, e unsigned idx, struct zink_descriptor_template *entry, unsigned *entry_idx) { int index = shader->bindings[type][idx].index; - gl_shader_stage stage = clamp_stage(&shader->info); + mesa_shader_stage stage = clamp_stage(&shader->info); entry->count = shader->bindings[type][idx].size; switch (shader->bindings[type][idx].type) { @@ -379,7 +379,7 @@ init_template_entry(struct zink_shader *shader, enum zink_descriptor_type type, unsigned idx, VkDescriptorUpdateTemplateEntry *entry, unsigned *entry_idx) { int index = shader->bindings[type][idx].index; - gl_shader_stage stage = clamp_stage(&shader->info); + mesa_shader_stage stage = clamp_stage(&shader->info); entry->dstArrayElement = 0; entry->dstBinding = shader->bindings[type][idx].binding; entry->descriptorCount = shader->bindings[type][idx].size; @@ -526,7 +526,7 @@ zink_descriptor_program_init(struct zink_context *ctx, struct zink_program *pg) if (!shader) continue; - gl_shader_stage stage = clamp_stage(&shader->info); + mesa_shader_stage stage = clamp_stage(&shader->info); VkShaderStageFlagBits stage_flags = mesa_to_vk_shader_stage(stage); /* uniform ubos handled in push */ if (shader->has_uniforms) { @@ -1466,7 +1466,7 @@ zink_descriptors_update(struct zink_context *ctx, bool is_compute) /* called from gallium descriptor change hooks, e.g., set_sampler_views */ void -zink_context_invalidate_descriptor_state(struct zink_context *ctx, gl_shader_stage shader, enum zink_descriptor_type type, unsigned start, unsigned count) +zink_context_invalidate_descriptor_state(struct zink_context *ctx, mesa_shader_stage shader, enum zink_descriptor_type type, unsigned start, unsigned count) { if (type == ZINK_DESCRIPTOR_TYPE_UBO && !start) ctx->dd.push_state_changed[shader == MESA_SHADER_COMPUTE] = true; @@ -1474,7 +1474,7 @@ zink_context_invalidate_descriptor_state(struct zink_context *ctx, gl_shader_sta ctx->dd.state_changed[shader == MESA_SHADER_COMPUTE] |= BITFIELD_BIT(type); } void -zink_context_invalidate_descriptor_state_compact(struct zink_context *ctx, gl_shader_stage shader, enum zink_descriptor_type type, unsigned start, unsigned count) +zink_context_invalidate_descriptor_state_compact(struct zink_context *ctx, mesa_shader_stage shader, enum zink_descriptor_type type, unsigned start, unsigned count) { if (type == ZINK_DESCRIPTOR_TYPE_UBO && !start) ctx->dd.push_state_changed[shader == MESA_SHADER_COMPUTE] = true; diff --git a/src/gallium/drivers/zink/zink_descriptors.h b/src/gallium/drivers/zink/zink_descriptors.h index ea3982bf014..1cb9d20d593 100644 --- a/src/gallium/drivers/zink/zink_descriptors.h +++ b/src/gallium/drivers/zink/zink_descriptors.h @@ -172,9 +172,9 @@ zink_descriptors_update(struct zink_context *ctx, bool is_compute); void -zink_context_invalidate_descriptor_state(struct zink_context *ctx, gl_shader_stage shader, enum zink_descriptor_type type, unsigned, unsigned); +zink_context_invalidate_descriptor_state(struct zink_context *ctx, mesa_shader_stage shader, enum zink_descriptor_type type, unsigned, unsigned); void -zink_context_invalidate_descriptor_state_compact(struct zink_context *ctx, gl_shader_stage shader, enum zink_descriptor_type type, unsigned, unsigned); +zink_context_invalidate_descriptor_state_compact(struct zink_context *ctx, mesa_shader_stage shader, enum zink_descriptor_type type, unsigned, unsigned); void zink_batch_descriptor_deinit(struct zink_screen *screen, struct zink_batch_state *bs); diff --git a/src/gallium/drivers/zink/zink_pipeline.c b/src/gallium/drivers/zink/zink_pipeline.c index 4af0f234003..d7af77109c6 100644 --- a/src/gallium/drivers/zink/zink_pipeline.c +++ b/src/gallium/drivers/zink/zink_pipeline.c @@ -837,7 +837,7 @@ zink_create_gfx_pipeline_library(struct zink_screen *screen, struct zink_gfx_pro } VkPipeline -zink_create_gfx_pipeline_separate(struct zink_screen *screen, struct zink_shader_object *objs, VkPipelineLayout layout, gl_shader_stage stage) +zink_create_gfx_pipeline_separate(struct zink_screen *screen, struct zink_shader_object *objs, VkPipelineLayout layout, mesa_shader_stage stage) { return create_gfx_pipeline_library(screen, objs, BITFIELD_BIT(stage), layout, VK_NULL_HANDLE); } diff --git a/src/gallium/drivers/zink/zink_pipeline.h b/src/gallium/drivers/zink/zink_pipeline.h index 92f34316271..7b050f15efb 100644 --- a/src/gallium/drivers/zink/zink_pipeline.h +++ b/src/gallium/drivers/zink/zink_pipeline.h @@ -64,7 +64,7 @@ zink_create_gfx_pipeline_output(struct zink_screen *screen, struct zink_gfx_pipe VkPipeline zink_create_gfx_pipeline_combined(struct zink_screen *screen, struct zink_gfx_program *prog, VkPipeline input, VkPipeline *library, unsigned libcount, VkPipeline output, bool optimized, bool testonly); VkPipeline -zink_create_gfx_pipeline_separate(struct zink_screen *screen, struct zink_shader_object *objs, VkPipelineLayout layout, gl_shader_stage stage); +zink_create_gfx_pipeline_separate(struct zink_screen *screen, struct zink_shader_object *objs, VkPipelineLayout layout, mesa_shader_stage stage); #ifdef __cplusplus } #endif diff --git a/src/gallium/drivers/zink/zink_program.c b/src/gallium/drivers/zink/zink_program.c index 65191c75575..4e39dd462e5 100644 --- a/src/gallium/drivers/zink/zink_program.c +++ b/src/gallium/drivers/zink/zink_program.c @@ -114,7 +114,7 @@ gather_shader_module_info(struct zink_context *ctx, struct zink_screen *screen, bool has_nonseamless, //is nonseamless ext present? unsigned *inline_size, unsigned *nonseamless_size) { - gl_shader_stage stage = zs->info.stage; + mesa_shader_stage stage = zs->info.stage; struct zink_shader_key *key = &state->shader_keys.key[stage]; if (has_inline && ctx && zs->info.num_inlinable_uniforms && ctx->inlinable_uniforms_valid_mask & BITFIELD64_BIT(stage)) { @@ -130,7 +130,7 @@ gather_shader_module_info(struct zink_context *ctx, struct zink_screen *screen, ALWAYS_INLINE static struct zink_shader_module * create_shader_module_for_stage(struct zink_context *ctx, struct zink_screen *screen, struct zink_shader *zs, struct zink_gfx_program *prog, - gl_shader_stage stage, + mesa_shader_stage stage, struct zink_gfx_pipeline_state *state, unsigned inline_size, unsigned nonseamless_size, bool has_inline, //is inlining enabled? @@ -194,7 +194,7 @@ create_shader_module_for_stage(struct zink_context *ctx, struct zink_screen *scr ALWAYS_INLINE static struct zink_shader_module * get_shader_module_for_stage(struct zink_context *ctx, struct zink_screen *screen, struct zink_shader *zs, struct zink_gfx_program *prog, - gl_shader_stage stage, + mesa_shader_stage stage, struct zink_gfx_pipeline_state *state, unsigned inline_size, unsigned nonseamless_size, bool has_inline, //is inlining enabled? @@ -240,7 +240,7 @@ get_shader_module_for_stage(struct zink_context *ctx, struct zink_screen *screen ALWAYS_INLINE static struct zink_shader_module * create_shader_module_for_stage_optimal(struct zink_context *ctx, struct zink_screen *screen, struct zink_shader *zs, struct zink_gfx_program *prog, - gl_shader_stage stage, + mesa_shader_stage stage, struct zink_gfx_pipeline_state *state) { struct zink_shader_module *zm; @@ -297,7 +297,7 @@ create_shader_module_for_stage_optimal(struct zink_context *ctx, struct zink_scr ALWAYS_INLINE static struct zink_shader_module * get_shader_module_for_stage_optimal(struct zink_context *ctx, struct zink_screen *screen, struct zink_shader *zs, struct zink_gfx_program *prog, - gl_shader_stage stage, + mesa_shader_stage stage, struct zink_gfx_pipeline_state *state) { /* non-generated tcs won't use the shader key */ @@ -601,7 +601,7 @@ zink_gfx_program_update(struct zink_context *ctx) { assert(!ctx->gfx_stages[MESA_SHADER_TESS_CTRL] || !ctx->gfx_stages[MESA_SHADER_TESS_CTRL]->non_fs.is_generated); if (ctx->last_vertex_stage_dirty) { - gl_shader_stage pstage = ctx->last_vertex_stage->info.stage; + mesa_shader_stage pstage = ctx->last_vertex_stage->info.stage; ctx->dirty_gfx_stages |= BITFIELD_BIT(pstage); memcpy(&ctx->gfx_pipeline_state.shader_keys.key[pstage].key.vs_base, &ctx->gfx_pipeline_state.shader_keys.last_vertex.key.vs_base, @@ -652,7 +652,7 @@ zink_gfx_program_update(struct zink_context *ctx) } ALWAYS_INLINE static bool -update_gfx_shader_module_optimal(struct zink_context *ctx, struct zink_gfx_program *prog, gl_shader_stage pstage) +update_gfx_shader_module_optimal(struct zink_context *ctx, struct zink_gfx_program *prog, mesa_shader_stage pstage) { struct zink_screen *screen = zink_screen(ctx->base.screen); if (screen->info.have_EXT_graphics_pipeline_library) @@ -1556,7 +1556,7 @@ create_compute_program(struct zink_context *ctx, nir_shader *nir) } bool -zink_program_descriptor_is_buffer(struct zink_context *ctx, gl_shader_stage stage, enum zink_descriptor_type type, unsigned i) +zink_program_descriptor_is_buffer(struct zink_context *ctx, mesa_shader_stage stage, enum zink_descriptor_type type, unsigned i) { struct zink_shader *zs = NULL; switch (stage) { @@ -1789,7 +1789,7 @@ out: } static void -bind_gfx_stage(struct zink_context *ctx, gl_shader_stage stage, struct zink_shader *shader) +bind_gfx_stage(struct zink_context *ctx, mesa_shader_stage stage, struct zink_shader *shader) { if (shader && shader->info.num_inlinable_uniforms) ctx->shader_has_inlinable_uniforms_mask |= 1 << stage; @@ -1870,7 +1870,7 @@ update_rast_prim(struct zink_shader *shader) } static void -unbind_generated_gs(struct zink_context *ctx, gl_shader_stage stage, struct zink_shader *prev_shader) +unbind_generated_gs(struct zink_context *ctx, mesa_shader_stage stage, struct zink_shader *prev_shader) { if (prev_shader->non_fs.is_generated) ctx->inlinable_uniforms_valid_mask &= ~BITFIELD64_BIT(MESA_SHADER_GEOMETRY); @@ -1883,19 +1883,19 @@ unbind_generated_gs(struct zink_context *ctx, gl_shader_stage stage, struct zink } static void -bind_last_vertex_stage(struct zink_context *ctx, gl_shader_stage stage, struct zink_shader *prev_shader) +bind_last_vertex_stage(struct zink_context *ctx, mesa_shader_stage stage, struct zink_shader *prev_shader) { if (prev_shader && stage < MESA_SHADER_GEOMETRY) unbind_generated_gs(ctx, stage, prev_shader); - gl_shader_stage old = ctx->last_vertex_stage ? ctx->last_vertex_stage->info.stage : MESA_SHADER_STAGES; + mesa_shader_stage old = ctx->last_vertex_stage ? ctx->last_vertex_stage->info.stage : MESA_SHADER_STAGES; if (ctx->gfx_stages[MESA_SHADER_GEOMETRY]) ctx->last_vertex_stage = ctx->gfx_stages[MESA_SHADER_GEOMETRY]; else if (ctx->gfx_stages[MESA_SHADER_TESS_EVAL]) ctx->last_vertex_stage = ctx->gfx_stages[MESA_SHADER_TESS_EVAL]; else ctx->last_vertex_stage = ctx->gfx_stages[MESA_SHADER_VERTEX]; - gl_shader_stage current = ctx->last_vertex_stage ? ctx->last_vertex_stage->info.stage : MESA_SHADER_VERTEX; + mesa_shader_stage current = ctx->last_vertex_stage ? ctx->last_vertex_stage->info.stage : MESA_SHADER_VERTEX; /* update rast_prim */ ctx->gfx_pipeline_state.shader_rast_prim = diff --git a/src/gallium/drivers/zink/zink_program.h b/src/gallium/drivers/zink/zink_program.h index 6dd52331899..8ad7003da3d 100644 --- a/src/gallium/drivers/zink/zink_program.h +++ b/src/gallium/drivers/zink/zink_program.h @@ -116,7 +116,7 @@ unsigned zink_program_num_bindings(const struct zink_program *pg); bool -zink_program_descriptor_is_buffer(struct zink_context *ctx, gl_shader_stage stage, enum zink_descriptor_type type, unsigned i); +zink_program_descriptor_is_buffer(struct zink_context *ctx, mesa_shader_stage stage, enum zink_descriptor_type type, unsigned i); void zink_gfx_program_update(struct zink_context *ctx); @@ -369,14 +369,14 @@ void zink_create_primitive_emulation_gs(struct zink_context *ctx); static inline const struct zink_shader_key_base * -zink_get_shader_key_base(const struct zink_context *ctx, gl_shader_stage pstage) +zink_get_shader_key_base(const struct zink_context *ctx, mesa_shader_stage pstage) { assert(!zink_screen(ctx->base.screen)->optimal_keys); return &ctx->gfx_pipeline_state.shader_keys.key[pstage].base; } static inline struct zink_shader_key_base * -zink_set_shader_key_base(struct zink_context *ctx, gl_shader_stage pstage) +zink_set_shader_key_base(struct zink_context *ctx, mesa_shader_stage pstage) { ctx->dirty_gfx_stages |= BITFIELD_BIT(pstage); assert(!zink_screen(ctx->base.screen)->optimal_keys); @@ -384,7 +384,7 @@ zink_set_shader_key_base(struct zink_context *ctx, gl_shader_stage pstage) } static inline void -zink_set_zs_needs_shader_swizzle_key(struct zink_context *ctx, gl_shader_stage pstage, bool swizzle_update) +zink_set_zs_needs_shader_swizzle_key(struct zink_context *ctx, mesa_shader_stage pstage, bool swizzle_update) { if (!zink_screen(ctx->base.screen)->driver_compiler_workarounds.needs_zs_shader_swizzle) { if (pstage != MESA_SHADER_FRAGMENT) diff --git a/src/gallium/drivers/zink/zink_types.h b/src/gallium/drivers/zink/zink_types.h index 0cced91545c..5d6ea86a347 100644 --- a/src/gallium/drivers/zink/zink_types.h +++ b/src/gallium/drivers/zink/zink_types.h @@ -1910,7 +1910,7 @@ struct zink_context { bool bindless_refs_dirty; bool null_fbfetch_init; } di; - void (*invalidate_descriptor_state)(struct zink_context *ctx, gl_shader_stage shader, enum zink_descriptor_type type, unsigned, unsigned); + void (*invalidate_descriptor_state)(struct zink_context *ctx, mesa_shader_stage shader, enum zink_descriptor_type type, unsigned, unsigned); struct set *need_barriers[2]; //gfx, compute struct set update_barriers[2][2]; //[gfx, compute][current, next] uint8_t barrier_set_idx[2]; diff --git a/src/gallium/frontends/lavapipe/lvp_execute.c b/src/gallium/frontends/lavapipe/lvp_execute.c index 0d5c780bbed..dcbebe99333 100644 --- a/src/gallium/frontends/lavapipe/lvp_execute.c +++ b/src/gallium/frontends/lavapipe/lvp_execute.c @@ -613,7 +613,7 @@ handle_graphics_stages(struct rendering_state *state, VkShaderStageFlagBits shad { u_foreach_bit(b, shader_stages) { VkShaderStageFlagBits vk_stage = (1 << b); - gl_shader_stage stage = vk_to_mesa_shader_stage(vk_stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(vk_stage); state->has_pcbuf[stage] = false; @@ -662,7 +662,7 @@ static void unbind_graphics_stages(struct rendering_state *state, VkShaderStageFlagBits shader_stages) { u_foreach_bit(vkstage, shader_stages) { - gl_shader_stage stage = vk_to_mesa_shader_stage(1<has_pcbuf[stage] = false; switch (stage) { case MESA_SHADER_FRAGMENT: @@ -702,7 +702,7 @@ unbind_graphics_stages(struct rendering_state *state, VkShaderStageFlagBits shad } static void -handle_graphics_pushconsts(struct rendering_state *state, gl_shader_stage stage, struct lvp_shader *shader) +handle_graphics_pushconsts(struct rendering_state *state, mesa_shader_stage stage, struct lvp_shader *shader) { state->has_pcbuf[stage] = shader->push_constant_size > 0; if (!state->has_pcbuf[stage]) @@ -1096,7 +1096,7 @@ static void handle_set_stage_buffer(struct rendering_state *state, struct pipe_resource *bo, size_t offset, - gl_shader_stage stage, + mesa_shader_stage stage, uint32_t index) { state->const_buffer[stage][index].buffer = bo; @@ -1113,7 +1113,7 @@ handle_set_stage_buffer(struct rendering_state *state, static void handle_set_stage(struct rendering_state *state, struct lvp_descriptor_set *set, enum lvp_pipeline_type pipeline_type, - gl_shader_stage stage, + mesa_shader_stage stage, uint32_t index) { state->desc_sets[pipeline_type][index] = set; @@ -3825,7 +3825,7 @@ handle_shaders(struct vk_cmd_queue_entry *cmd, struct rendering_state *state) unsigned new_stages = 0; unsigned null_stages = 0; for (unsigned i = 0; i < bind->stage_count; i++) { - gl_shader_stage stage = vk_to_mesa_shader_stage(bind->stages[i]); + mesa_shader_stage stage = vk_to_mesa_shader_stage(bind->stages[i]); assert(stage != MESA_SHADER_NONE && stage <= MESA_SHADER_MESH); LVP_FROM_HANDLE(lvp_shader, shader, bind->shaders ? bind->shaders[i] : VK_NULL_HANDLE); if (stage == MESA_SHADER_FRAGMENT) { @@ -4345,7 +4345,7 @@ handle_descriptor_buffer_offsets(struct vk_cmd_queue_entry *cmd, struct renderin } else { /* set for all stages */ u_foreach_bit(stage, set_layout->shader_stages) { - gl_shader_stage pstage = vk_to_mesa_shader_stage(1<desc_buffers[dbo->pBufferIndices[i]], dbo->pOffsets[i], pstage, idx); } } @@ -4355,7 +4355,7 @@ handle_descriptor_buffer_offsets(struct vk_cmd_queue_entry *cmd, struct renderin } static void * -lvp_push_internal_buffer(struct rendering_state *state, gl_shader_stage stage, uint32_t size) +lvp_push_internal_buffer(struct rendering_state *state, mesa_shader_stage stage, uint32_t size) { if (!size) return NULL; diff --git a/src/gallium/frontends/lavapipe/lvp_pipeline.c b/src/gallium/frontends/lavapipe/lvp_pipeline.c index f1493e4cb71..04f79688368 100644 --- a/src/gallium/frontends/lavapipe/lvp_pipeline.c +++ b/src/gallium/frontends/lavapipe/lvp_pipeline.c @@ -49,7 +49,7 @@ shader_destroy(struct lvp_device *device, struct lvp_shader *shader, bool locked { if (!shader->pipeline_nir) return; - gl_shader_stage stage = shader->pipeline_nir->nir->info.stage; + mesa_shader_stage stage = shader->pipeline_nir->nir->info.stage; cso_destroy_func destroy[] = { device->queue.ctx->delete_vs_state, device->queue.ctx->delete_tcs_state, @@ -279,7 +279,7 @@ compile_spirv(struct lvp_device *pdevice, const VkPipelineShaderStageCreateInfo *sinfo, nir_shader **nir) { - gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage); assert(stage <= LVP_SHADER_STAGES && stage != MESA_SHADER_NONE); VkResult result; @@ -476,7 +476,7 @@ static VkResult lvp_shader_compile_to_ir(struct lvp_pipeline *pipeline, const void *pipeline_pNext, const VkPipelineShaderStageCreateInfo *sinfo) { - gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage); assert(stage <= LVP_SHADER_STAGES && stage != MESA_SHADER_NONE); nir_shader *nir; VkResult result = lvp_spirv_to_nir(pipeline, pipeline_pNext, sinfo, &nir); @@ -562,7 +562,7 @@ lvp_shader_xfb_init(struct lvp_shader *shader) static void lvp_pipeline_xfb_init(struct lvp_pipeline *pipeline) { - gl_shader_stage stage = MESA_SHADER_VERTEX; + mesa_shader_stage stage = MESA_SHADER_VERTEX; if (pipeline->shaders[MESA_SHADER_GEOMETRY].pipeline_nir) stage = MESA_SHADER_GEOMETRY; else if (pipeline->shaders[MESA_SHADER_TESS_EVAL].pipeline_nir) @@ -834,7 +834,7 @@ lvp_graphics_pipeline_init(struct lvp_pipeline *pipeline, for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) { const VkPipelineShaderStageCreateInfo *sinfo = &pCreateInfo->pStages[i]; - gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage); if (stage == MESA_SHADER_FRAGMENT) { if (!(pipeline->stages & VK_GRAPHICS_PIPELINE_LIBRARY_FRAGMENT_SHADER_BIT_EXT)) continue; @@ -919,7 +919,7 @@ lvp_pipeline_shaders_compile(struct lvp_pipeline *pipeline, bool locked) if (!pipeline->shaders[i].pipeline_nir) continue; - gl_shader_stage stage = i; + mesa_shader_stage stage = i; assert(stage == pipeline->shaders[i].pipeline_nir->nir->info.stage); pipeline->shaders[stage].shader_cso = lvp_shader_compile(pipeline->device, &pipeline->shaders[stage], @@ -1137,7 +1137,7 @@ static VkShaderEXT create_shader_object(struct lvp_device *device, const VkShaderCreateInfoEXT *pCreateInfo, const VkAllocationCallbacks *pAllocator) { nir_shader *nir = NULL; - gl_shader_stage stage = vk_to_mesa_shader_stage(pCreateInfo->stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(pCreateInfo->stage); assert(stage <= LVP_SHADER_STAGES && stage != MESA_SHADER_NONE); if (pCreateInfo->codeType == VK_SHADER_CODE_TYPE_SPIRV_EXT) { VkShaderModuleCreateInfo minfo = { diff --git a/src/gallium/frontends/lavapipe/lvp_private.h b/src/gallium/frontends/lavapipe/lvp_private.h index cb13a084392..c896d8ae497 100644 --- a/src/gallium/frontends/lavapipe/lvp_private.h +++ b/src/gallium/frontends/lavapipe/lvp_private.h @@ -138,17 +138,17 @@ void __lvp_finishme(const char *file, int line, const char *format, ...) #define LVP_STAGE_MASK_GFX (BITFIELD_MASK(MESA_SHADER_MESH_STAGES) & ~BITFIELD_BIT(MESA_SHADER_COMPUTE)) #define lvp_foreach_stage(stage, stage_bits) \ - for (gl_shader_stage stage, \ - __tmp = (gl_shader_stage)((stage_bits) & LVP_STAGE_MASK); \ + for (mesa_shader_stage stage, \ + __tmp = (mesa_shader_stage)((stage_bits) & LVP_STAGE_MASK); \ stage = ffs(__tmp) - 1, __tmp; \ __tmp &= ~(1 << (stage))) #define lvp_forall_stage(stage) \ - for (gl_shader_stage stage = MESA_SHADER_VERTEX; stage < LVP_SHADER_STAGES; stage++) + for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < LVP_SHADER_STAGES; stage++) #define lvp_forall_gfx_stage(stage) \ - for (gl_shader_stage stage, \ - __tmp = (gl_shader_stage)(LVP_STAGE_MASK_GFX); \ + for (mesa_shader_stage stage, \ + __tmp = (mesa_shader_stage)(LVP_STAGE_MASK_GFX); \ stage = ffs(__tmp) - 1, __tmp; \ __tmp &= ~(1 << (stage))) @@ -513,7 +513,7 @@ struct lvp_pipeline { void *state_data; bool force_min_sample; struct lvp_shader shaders[LVP_SHADER_STAGES]; - gl_shader_stage last_vertex; + mesa_shader_stage last_vertex; struct vk_graphics_pipeline_state graphics_state; VkGraphicsPipelineLibraryFlagsEXT stages; bool line_smooth; diff --git a/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs b/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs index 71aec1effa5..8e54b391a8d 100644 --- a/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs +++ b/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs @@ -339,7 +339,7 @@ impl SPIRVBin { self.spirv.size / 4, spec_constants.as_mut_ptr(), spec_constants.len() as u32, - gl_shader_stage::MESA_SHADER_KERNEL, + mesa_shader_stage::MESA_SHADER_KERNEL, c_entry.as_ptr(), &spirv_options, nir_options, diff --git a/src/imagination/pco/pco_internal.h b/src/imagination/pco/pco_internal.h index 181540ed2cd..95ba0f22d0a 100644 --- a/src/imagination/pco/pco_internal.h +++ b/src/imagination/pco/pco_internal.h @@ -337,7 +337,7 @@ typedef struct _pco_shader { pco_ctx *ctx; /** Compiler context. */ nir_shader *nir; /** Source NIR shader. */ - gl_shader_stage stage; /** Shader stage. */ + mesa_shader_stage stage; /** Shader stage. */ const char *name; /** Shader name. */ bool is_internal; /** Whether this is an internal shader. */ bool is_grouped; /** Whether the shader uses igrps. */ diff --git a/src/imagination/pco/pco_trans_nir.c b/src/imagination/pco/pco_trans_nir.c index c3351bac1d1..febf70e2238 100644 --- a/src/imagination/pco/pco_trans_nir.c +++ b/src/imagination/pco/pco_trans_nir.c @@ -30,7 +30,7 @@ typedef struct _trans_ctx { pco_shader *shader; /** Current shader. */ pco_func *func; /** Current function. */ pco_builder b; /** Builder. */ - gl_shader_stage stage; /** Shader stage. */ + mesa_shader_stage stage; /** Shader stage. */ BITSET_WORD *float_types; /** NIR SSA float vars. */ BITSET_WORD *int_types; /** NIR SSA int vars. */ diff --git a/src/imagination/rogue/rogue.c b/src/imagination/rogue/rogue.c index c19b25aabec..81bb366fa6d 100644 --- a/src/imagination/rogue/rogue.c +++ b/src/imagination/rogue/rogue.c @@ -200,7 +200,7 @@ static void rogue_shader_destructor(void *ptr) * \return The new shader. */ PUBLIC -rogue_shader *rogue_shader_create(void *mem_ctx, gl_shader_stage stage) +rogue_shader *rogue_shader_create(void *mem_ctx, mesa_shader_stage stage) { rogue_debug_init(); diff --git a/src/imagination/rogue/rogue.h b/src/imagination/rogue/rogue.h index 5da334ffba2..10878c206b5 100644 --- a/src/imagination/rogue/rogue.h +++ b/src/imagination/rogue/rogue.h @@ -1814,7 +1814,7 @@ typedef struct rogue_build_ctx rogue_build_ctx; /** Rogue shader object. */ typedef struct rogue_shader { - gl_shader_stage stage; /** Shader stage. */ + mesa_shader_stage stage; /** Shader stage. */ rogue_build_ctx *ctx; /** Build context. */ @@ -1874,7 +1874,7 @@ static inline void rogue_clear_reg_use(rogue_shader *shader, * \param[in] stage The shader stage. * \return The new shader. */ -rogue_shader *rogue_shader_create(void *mem_ctx, gl_shader_stage stage); +rogue_shader *rogue_shader_create(void *mem_ctx, mesa_shader_stage stage); rogue_reg *rogue_ssa_reg(rogue_shader *shader, unsigned index); @@ -2933,7 +2933,7 @@ unsigned rogue_ubo_reg(rogue_ubo_data *ubo_data, unsigned offset_bytes); nir_shader *rogue_spirv_to_nir(rogue_build_ctx *ctx, - gl_shader_stage stage, + mesa_shader_stage stage, const char *entry, unsigned spirv_size, const uint32_t *spirv_data, diff --git a/src/imagination/rogue/rogue_build_data.c b/src/imagination/rogue/rogue_build_data.c index 4f7b1b9f390..e25a1efdc2f 100644 --- a/src/imagination/rogue/rogue_build_data.c +++ b/src/imagination/rogue/rogue_build_data.c @@ -333,7 +333,7 @@ static void collect_io_data_vs(struct rogue_common_build_data *common_data, PUBLIC void rogue_collect_io_data(struct rogue_build_ctx *ctx, nir_shader *nir) { - gl_shader_stage stage = nir->info.stage; + mesa_shader_stage stage = nir->info.stage; struct rogue_common_build_data *common_data = &ctx->common_data[stage]; /* Collect stage-specific data. */ diff --git a/src/imagination/rogue/rogue_compile.c b/src/imagination/rogue/rogue_compile.c index 899161cef90..0d89283cdaf 100644 --- a/src/imagination/rogue/rogue_compile.c +++ b/src/imagination/rogue/rogue_compile.c @@ -308,7 +308,7 @@ static void trans_nir_intrinsic_store_output(rogue_builder *b, UNREACHABLE("Unimplemented NIR store_output variant."); } -static inline gl_shader_stage +static inline mesa_shader_stage pvr_stage_to_mesa(enum pvr_stage_allocation pvr_stage) { switch (pvr_stage) { @@ -329,7 +329,7 @@ pvr_stage_to_mesa(enum pvr_stage_allocation pvr_stage) } static inline enum pvr_stage_allocation -mesa_stage_to_pvr(gl_shader_stage mesa_stage) +mesa_stage_to_pvr(mesa_shader_stage mesa_stage) { switch (mesa_stage) { case MESA_SHADER_VERTEX: @@ -345,7 +345,7 @@ mesa_stage_to_pvr(gl_shader_stage mesa_stage) break; } - UNREACHABLE("Unsupported gl_shader_stage."); + UNREACHABLE("Unsupported mesa_shader_stage."); } static bool descriptor_is_dynamic(VkDescriptorType type) { @@ -571,7 +571,7 @@ static bool ssa_def_cb(nir_def *ssa, void *state) PUBLIC rogue_shader *rogue_nir_to_rogue(rogue_build_ctx *ctx, const nir_shader *nir) { - gl_shader_stage stage = nir->info.stage; + mesa_shader_stage stage = nir->info.stage; rogue_shader *shader = rogue_shader_create(ctx, stage); if (!shader) return NULL; diff --git a/src/imagination/rogue/rogue_nir.c b/src/imagination/rogue/rogue_nir.c index 256c7416af8..c0fa5bfba48 100644 --- a/src/imagination/rogue/rogue_nir.c +++ b/src/imagination/rogue/rogue_nir.c @@ -63,7 +63,7 @@ static int rogue_glsl_type_size(const struct glsl_type *type, bool bindless) */ static void rogue_nir_passes(struct rogue_build_ctx *ctx, nir_shader *nir, - gl_shader_stage stage) + mesa_shader_stage stage) { bool progress; @@ -207,7 +207,7 @@ static void rogue_nir_passes(struct rogue_build_ctx *ctx, */ PUBLIC nir_shader *rogue_spirv_to_nir(rogue_build_ctx *ctx, - gl_shader_stage stage, + mesa_shader_stage stage, const char *entry, unsigned spirv_size, const uint32_t *spirv_data, diff --git a/src/imagination/rogue/tools/vk_compiler.c b/src/imagination/rogue/tools/vk_compiler.c index 2fde1682023..1cbcee37325 100644 --- a/src/imagination/rogue/tools/vk_compiler.c +++ b/src/imagination/rogue/tools/vk_compiler.c @@ -58,7 +58,7 @@ static const struct option cmdline_opts[] = { }; typedef struct compiler_opts { - gl_shader_stage stage; + mesa_shader_stage stage; char *file; char *entry; char *out_file; diff --git a/src/imagination/vulkan/pvr_hardcode.c b/src/imagination/vulkan/pvr_hardcode.c index 987a217ec01..c06729ef604 100644 --- a/src/imagination/vulkan/pvr_hardcode.c +++ b/src/imagination/vulkan/pvr_hardcode.c @@ -73,7 +73,7 @@ static const struct pvr_hard_coding_data { } compute; struct { - /* Mask of MESA_SHADER_* (gl_shader_stage). */ + /* Mask of MESA_SHADER_* (mesa_shader_stage). */ uint32_t flags; uint8_t *const *const vert_shaders; @@ -211,7 +211,7 @@ pvr_hard_code_graphics_get_flags(const struct pvr_device_info *const dev_info) void pvr_hard_code_graphics_shader(const struct pvr_device_info *const dev_info, uint32_t pipeline_n, - gl_shader_stage stage, + mesa_shader_stage stage, struct util_dynarray *shader_out) { const struct pvr_hard_coding_data *const data = @@ -276,7 +276,7 @@ void pvr_hard_code_graphics_fragment_state( void pvr_hard_code_graphics_get_build_info( const struct pvr_device_info *const dev_info, uint32_t pipeline_n, - gl_shader_stage stage, + mesa_shader_stage stage, struct rogue_common_build_data *const common_build_data, struct rogue_build_data *const build_data, struct pvr_explicit_constant_usage *const explicit_const_usage) diff --git a/src/imagination/vulkan/pvr_hardcode.h b/src/imagination/vulkan/pvr_hardcode.h index 024b12061fe..a46db2cfbf4 100644 --- a/src/imagination/vulkan/pvr_hardcode.h +++ b/src/imagination/vulkan/pvr_hardcode.h @@ -84,7 +84,7 @@ VkResult pvr_hard_code_compute_pipeline( struct pvr_compute_shader_state *const shader_state_out, struct pvr_hard_code_compute_build_info *const build_info_out); -/* Returns a mask of MESA_SHADER_* (gl_shader_stage) indicating which stage +/* Returns a mask of MESA_SHADER_* (mesa_shader_stage) indicating which stage * needs to be hard coded. */ uint32_t @@ -98,7 +98,7 @@ pvr_hard_code_graphics_get_flags(const struct pvr_device_info *const dev_info); */ void pvr_hard_code_graphics_shader(const struct pvr_device_info *const dev_info, uint32_t pipeline_n, - gl_shader_stage stage, + mesa_shader_stage stage, struct util_dynarray *shader_out); void pvr_hard_code_graphics_vertex_state( @@ -114,7 +114,7 @@ void pvr_hard_code_graphics_fragment_state( void pvr_hard_code_graphics_get_build_info( const struct pvr_device_info *const dev_info, uint32_t pipeline_n, - gl_shader_stage stage, + mesa_shader_stage stage, rogue_common_build_data *const common_build_data, rogue_build_data *const build_data, struct pvr_explicit_constant_usage *const explicit_const_usage); diff --git a/src/imagination/vulkan/pvr_pipeline.c b/src/imagination/vulkan/pvr_pipeline.c index edb4a7fd4df..b4b85eeb506 100644 --- a/src/imagination/vulkan/pvr_pipeline.c +++ b/src/imagination/vulkan/pvr_pipeline.c @@ -527,7 +527,7 @@ static VkResult pvr_pds_descriptor_program_create_and_upload( struct pvr_device *const device, const VkAllocationCallbacks *const allocator, const struct vk_pipeline_layout *const layout, - gl_shader_stage stage, + mesa_shader_stage stage, pco_data *data, struct pvr_stage_allocation_descriptor_state *const descriptor_state) { @@ -1942,7 +1942,7 @@ static void pvr_setup_descriptors(pco_data *data, nir_shader *nir, struct vk_pipeline_layout *layout) { - gl_shader_stage stage = nir->info.stage; + mesa_shader_stage stage = nir->info.stage; for (unsigned desc_set = 0; desc_set < layout->set_count; ++desc_set) { const struct pvr_descriptor_set_layout *set_layout = @@ -2103,7 +2103,7 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device, struct pvr_pds_coeff_loading_program frag_coeff_program = { 0 }; - for (gl_shader_stage stage = 0; stage < MESA_SHADER_STAGES; ++stage) { + for (mesa_shader_stage stage = 0; stage < MESA_SHADER_STAGES; ++stage) { size_t stage_index = gfx_pipeline->stage_indices[stage]; /* Skip unused/inactive stages. */ @@ -2124,7 +2124,7 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device, pco_preprocess_nir(pco_ctx, nir_shaders[stage]); } - for (gl_shader_stage stage = 0; stage < MESA_SHADER_STAGES; ++stage) { + for (mesa_shader_stage stage = 0; stage < MESA_SHADER_STAGES; ++stage) { if (!nir_shaders[stage]) continue; @@ -2134,7 +2134,7 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device, producer = nir_shaders[stage]; } - for (gl_shader_stage stage = MESA_SHADER_STAGES; stage-- > 0;) { + for (mesa_shader_stage stage = MESA_SHADER_STAGES; stage-- > 0;) { if (!nir_shaders[stage]) continue; @@ -2144,7 +2144,7 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device, consumer = nir_shaders[stage]; } - for (gl_shader_stage stage = 0; stage < MESA_SHADER_STAGES; ++stage) { + for (mesa_shader_stage stage = 0; stage < MESA_SHADER_STAGES; ++stage) { if (!nir_shaders[stage]) continue; @@ -2163,7 +2163,7 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device, layout); } - for (gl_shader_stage stage = 0; stage < MESA_SHADER_STAGES; ++stage) { + for (mesa_shader_stage stage = 0; stage < MESA_SHADER_STAGES; ++stage) { pco_shader **pco = &pco_shaders[stage]; /* Skip unused/inactive stages. */ @@ -2385,7 +2385,7 @@ pvr_graphics_pipeline_init(struct pvr_device *device, for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) { VkShaderStageFlagBits vk_stage = pCreateInfo->pStages[i].stage; - gl_shader_stage gl_stage = vk_to_mesa_shader_stage(vk_stage); + mesa_shader_stage gl_stage = vk_to_mesa_shader_stage(vk_stage); /* From the Vulkan 1.2.192 spec for VkPipelineShaderStageCreateInfo: * * "stage must not be VK_SHADER_STAGE_ALL_GRAPHICS, diff --git a/src/imagination/vulkan/pvr_shader.c b/src/imagination/vulkan/pvr_shader.c index 6539f5c8e79..711c7e94e89 100644 --- a/src/imagination/vulkan/pvr_shader.c +++ b/src/imagination/vulkan/pvr_shader.c @@ -52,7 +52,7 @@ * \return A nir_shader* if successful, or NULL if unsuccessful. */ nir_shader *pvr_spirv_to_nir(rogue_build_ctx *ctx, - gl_shader_stage stage, + mesa_shader_stage stage, const VkPipelineShaderStageCreateInfo *create_info) { VK_FROM_HANDLE(vk_shader_module, module, create_info->module); diff --git a/src/imagination/vulkan/pvr_shader.h b/src/imagination/vulkan/pvr_shader.h index 5d82a5e06fa..b2bfef82920 100644 --- a/src/imagination/vulkan/pvr_shader.h +++ b/src/imagination/vulkan/pvr_shader.h @@ -34,7 +34,7 @@ nir_shader * pvr_spirv_to_nir(rogue_build_ctx *ctx, - gl_shader_stage stage, + mesa_shader_stage stage, const VkPipelineShaderStageCreateInfo *create_info); rogue_shader *pvr_nir_to_rogue(rogue_build_ctx *ctx, nir_shader *nir); diff --git a/src/imagination/vulkan/pvr_uscgen.c b/src/imagination/vulkan/pvr_uscgen.c index 9c9e85ba843..6b7f31c7f73 100644 --- a/src/imagination/vulkan/pvr_uscgen.c +++ b/src/imagination/vulkan/pvr_uscgen.c @@ -46,7 +46,7 @@ static void build_shader(pco_ctx *ctx, nir_shader *nir, pco_binary **binary) * \param stage Shader stage. * \param binary Output shader binary. */ -void pvr_uscgen_nop(pco_ctx *ctx, gl_shader_stage stage, pco_binary **binary) +void pvr_uscgen_nop(pco_ctx *ctx, mesa_shader_stage stage, pco_binary **binary) { UNREACHABLE("finishme: pvr_uscgen_nop"); } diff --git a/src/imagination/vulkan/pvr_uscgen.h b/src/imagination/vulkan/pvr_uscgen.h index 38e147853e8..6773e93021d 100644 --- a/src/imagination/vulkan/pvr_uscgen.h +++ b/src/imagination/vulkan/pvr_uscgen.h @@ -17,7 +17,7 @@ #include "pco/pco.h" /* NOP shader generation. */ -void pvr_uscgen_nop(pco_ctx *ctx, gl_shader_stage stage, pco_binary **binary); +void pvr_uscgen_nop(pco_ctx *ctx, mesa_shader_stage stage, pco_binary **binary); /* EOT shader generation. */ struct pvr_eot_props { diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index 7bd2ec49db2..c3c5de92ab9 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -1207,7 +1207,7 @@ blorp_build_nir_shader(struct blorp_context *blorp, nir_builder b; const bool compute = key->base.shader_pipeline == BLORP_SHADER_PIPELINE_COMPUTE; - gl_shader_stage stage = + mesa_shader_stage stage = compute ? MESA_SHADER_COMPUTE : MESA_SHADER_FRAGMENT; blorp_nir_init_shader(&b, blorp, mem_ctx, stage, NULL); diff --git a/src/intel/blorp/blorp_brw.c b/src/intel/blorp/blorp_brw.c index 7a7222a264b..94b1a009b16 100644 --- a/src/intel/blorp/blorp_brw.c +++ b/src/intel/blorp/blorp_brw.c @@ -11,7 +11,7 @@ static const nir_shader_compiler_options * blorp_nir_options_brw(struct blorp_context *blorp, - gl_shader_stage stage) + mesa_shader_stage stage) { const struct brw_compiler *compiler = blorp->compiler->brw; return compiler->nir_options[stage]; diff --git a/src/intel/blorp/blorp_elk.c b/src/intel/blorp/blorp_elk.c index b58033d6316..6fec1d7fdd5 100644 --- a/src/intel/blorp/blorp_elk.c +++ b/src/intel/blorp/blorp_elk.c @@ -12,7 +12,7 @@ static const nir_shader_compiler_options * blorp_nir_options_elk(struct blorp_context *blorp, - gl_shader_stage stage) + mesa_shader_stage stage) { const struct elk_compiler *compiler = blorp->compiler->elk; return compiler->nir_options[stage]; diff --git a/src/intel/blorp/blorp_nir_builder.h b/src/intel/blorp/blorp_nir_builder.h index bf5ce426686..2b308b46797 100644 --- a/src/intel/blorp/blorp_nir_builder.h +++ b/src/intel/blorp/blorp_nir_builder.h @@ -28,7 +28,7 @@ static inline void blorp_nir_init_shader(nir_builder *b, struct blorp_context *blorp, void *mem_ctx, - gl_shader_stage stage, + mesa_shader_stage stage, const char *name) { const nir_shader_compiler_options *nir_options = diff --git a/src/intel/blorp/blorp_priv.h b/src/intel/blorp/blorp_priv.h index 4b563494681..3c74cfa6bca 100644 --- a/src/intel/blorp/blorp_priv.h +++ b/src/intel/blorp/blorp_priv.h @@ -43,7 +43,7 @@ struct blorp_compiler { const struct elk_compiler *elk; const nir_shader_compiler_options *(*nir_options)(struct blorp_context *blorp, - gl_shader_stage stage); + mesa_shader_stage stage); struct blorp_program (*compile_fs)(struct blorp_context *blorp, void *mem_ctx, struct nir_shader *nir, diff --git a/src/intel/common/intel_l3_config.h b/src/intel/common/intel_l3_config.h index 88d320649e8..f44131e41c3 100644 --- a/src/intel/common/intel_l3_config.h +++ b/src/intel/common/intel_l3_config.h @@ -124,7 +124,7 @@ void intel_get_urb_config(const struct intel_device_info *devinfo, static inline bool intel_urb_setup_changed(const struct intel_urb_config *a, const struct intel_urb_config *b, - gl_shader_stage stage) + mesa_shader_stage stage) { if (a->size[stage] != b->size[stage] || a->entries[stage] != b->entries[stage] || diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 95746ba0d61..821c9087265 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -286,7 +286,7 @@ brw_device_sha1(char *hex, } unsigned -brw_prog_data_size(gl_shader_stage stage) +brw_prog_data_size(mesa_shader_stage stage) { static const size_t stage_sizes[] = { [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_data), @@ -310,7 +310,7 @@ brw_prog_data_size(gl_shader_stage stage) } unsigned -brw_prog_key_size(gl_shader_stage stage) +brw_prog_key_size(mesa_shader_stage stage) { static const size_t stage_sizes[] = { [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_key), diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 4bfaaf97f9c..90139ee12b7 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -162,21 +162,21 @@ struct brw_compiler { #define BRW_SUBGROUP_SIZE 32 static inline bool -brw_shader_stage_is_bindless(gl_shader_stage stage) +brw_shader_stage_is_bindless(mesa_shader_stage stage) { return stage >= MESA_SHADER_RAYGEN && stage <= MESA_SHADER_CALLABLE; } static inline bool -brw_shader_stage_requires_bindless_resources(gl_shader_stage stage) +brw_shader_stage_requires_bindless_resources(mesa_shader_stage stage) { return brw_shader_stage_is_bindless(stage) || gl_shader_stage_is_mesh(stage); } static inline bool brw_shader_stage_has_inline_data(const struct intel_device_info *devinfo, - gl_shader_stage stage) + mesa_shader_stage stage) { return stage == MESA_SHADER_MESH || stage == MESA_SHADER_TASK || (stage == MESA_SHADER_COMPUTE && devinfo->verx10 >= 125); @@ -586,7 +586,7 @@ struct brw_stage_prog_data { unsigned nr_params; /**< number of float params/constants */ - gl_shader_stage stage; + mesa_shader_stage stage; /* zero_push_reg is a bitfield which indicates what push registers (if any) * should be zeroed by SW at the start of the shader. The corresponding @@ -1096,7 +1096,7 @@ typedef enum ~VARYING_BIT_POS & ~VARYING_BIT_FACE) void brw_print_vue_map(FILE *fp, const struct intel_vue_map *vue_map, - gl_shader_stage stage); + mesa_shader_stage stage); /** * Convert a VUE slot number into a byte offset within the VUE. @@ -1414,10 +1414,10 @@ brw_device_sha1_update(struct mesa_sha1 *sha1_ctx, const struct intel_device_info *devinfo); unsigned -brw_prog_data_size(gl_shader_stage stage); +brw_prog_data_size(mesa_shader_stage stage); unsigned -brw_prog_key_size(gl_shader_stage stage); +brw_prog_key_size(mesa_shader_stage stage); struct brw_compile_params { void *mem_ctx; @@ -1624,7 +1624,7 @@ brw_compile_bs(const struct brw_compiler *compiler, struct brw_compile_bs_params *params); void brw_debug_key_recompile(const struct brw_compiler *c, void *log, - gl_shader_stage stage, + mesa_shader_stage stage, const struct brw_base_prog_key *old_key, const struct brw_base_prog_key *key); @@ -1661,7 +1661,7 @@ brw_cs_get_dispatch_info(const struct intel_device_info *devinfo, */ static inline bool brw_stage_has_packed_dispatch(ASSERTED const struct intel_device_info *devinfo, - gl_shader_stage stage, unsigned max_polygons, + mesa_shader_stage stage, unsigned max_polygons, const struct brw_stage_prog_data *prog_data) { /* The code below makes assumptions about the hardware's thread dispatch diff --git a/src/intel/compiler/brw_debug_recompile.c b/src/intel/compiler/brw_debug_recompile.c index bc83a4fdc90..dd66f05f17f 100644 --- a/src/intel/compiler/brw_debug_recompile.c +++ b/src/intel/compiler/brw_debug_recompile.c @@ -167,7 +167,7 @@ debug_cs_recompile(const struct brw_compiler *c, void *log, void brw_debug_key_recompile(const struct brw_compiler *c, void *log, - gl_shader_stage stage, + mesa_shader_stage stage, const struct brw_base_prog_key *old_key, const struct brw_base_prog_key *key) { diff --git a/src/intel/compiler/brw_from_nir.cpp b/src/intel/compiler/brw_from_nir.cpp index d7d8e681e40..3e3c439e9ab 100644 --- a/src/intel/compiler/brw_from_nir.cpp +++ b/src/intel/compiler/brw_from_nir.cpp @@ -8011,7 +8011,7 @@ static UNUSED void brw_test_dispatch_packing(const brw_builder &bld) { const brw_shader *shader = bld.shader; - const gl_shader_stage stage = shader->stage; + const mesa_shader_stage stage = shader->stage; const bool uses_vmask = stage == MESA_SHADER_FRAGMENT && brw_wm_prog_data(shader->prog_data)->uses_vmask; diff --git a/src/intel/compiler/brw_generator.cpp b/src/intel/compiler/brw_generator.cpp index 24ad4d6650e..0818b63ee98 100644 --- a/src/intel/compiler/brw_generator.cpp +++ b/src/intel/compiler/brw_generator.cpp @@ -94,7 +94,7 @@ normalize_brw_reg_for_encoding(brw_reg *reg) brw_generator::brw_generator(const struct brw_compiler *compiler, const struct brw_compile_params *params, struct brw_stage_prog_data *prog_data, - gl_shader_stage stage) + mesa_shader_stage stage) : compiler(compiler), params(params), devinfo(compiler->devinfo), diff --git a/src/intel/compiler/brw_generator.h b/src/intel/compiler/brw_generator.h index 1e87747bb83..c95eddb3828 100644 --- a/src/intel/compiler/brw_generator.h +++ b/src/intel/compiler/brw_generator.h @@ -14,7 +14,7 @@ public: brw_generator(const struct brw_compiler *compiler, const struct brw_compile_params *params, struct brw_stage_prog_data *prog_data, - gl_shader_stage stage); + mesa_shader_stage stage); ~brw_generator(); void enable_debug(const char *shader_name); @@ -73,7 +73,7 @@ private: brw_exec_list discard_halt_patches; bool debug_flag; const char *shader_name; - gl_shader_stage stage; + mesa_shader_stage stage; void *mem_ctx; }; diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h index ec21c56eaf7..58c81f246e2 100644 --- a/src/intel/compiler/brw_nir.h +++ b/src/intel/compiler/brw_nir.h @@ -288,7 +288,7 @@ void brw_nir_adjust_payload(nir_shader *shader); static inline nir_variable_mode brw_nir_no_indirect_mask(const struct brw_compiler *compiler, - gl_shader_stage stage) + mesa_shader_stage stage) { nir_variable_mode indirect_mask = (nir_variable_mode) 0; diff --git a/src/intel/compiler/brw_nir_lower_rt_intrinsics.c b/src/intel/compiler/brw_nir_lower_rt_intrinsics.c index b4c1c5fefa2..1291290acac 100644 --- a/src/intel/compiler/brw_nir_lower_rt_intrinsics.c +++ b/src/intel/compiler/brw_nir_lower_rt_intrinsics.c @@ -78,7 +78,7 @@ lower_rt_intrinsics_impl(nir_function_impl *impl, nir_def *hotzone_addr = brw_nir_rt_sw_hotzone_addr(b, devinfo); nir_def *hotzone = nir_load_global(b, hotzone_addr, 16, 4, 32); - gl_shader_stage stage = b->shader->info.stage; + mesa_shader_stage stage = b->shader->info.stage; struct brw_nir_rt_mem_ray_defs world_ray_in = {}; struct brw_nir_rt_mem_ray_defs object_ray_in = {}; struct brw_nir_rt_mem_hit_defs hit_in = {}; diff --git a/src/intel/compiler/brw_nir_rt.c b/src/intel/compiler/brw_nir_rt.c index 3fcf6e8d1bc..a1edcf91596 100644 --- a/src/intel/compiler/brw_nir_rt.c +++ b/src/intel/compiler/brw_nir_rt.c @@ -88,7 +88,7 @@ lower_rt_io_derefs(nir_shader *shader, const struct intel_device_info *devinfo) metadata &= nir_metadata_control_flow; } - gl_shader_stage stage = shader->info.stage; + mesa_shader_stage stage = shader->info.stage; nir_def *hit_attrib_addr = NULL; if (num_ray_hit_attrib_vars > 0) { assert(stage == MESA_SHADER_ANY_HIT || diff --git a/src/intel/compiler/brw_shader.h b/src/intel/compiler/brw_shader.h index aad57780e1e..8fe8e6d270b 100644 --- a/src/intel/compiler/brw_shader.h +++ b/src/intel/compiler/brw_shader.h @@ -117,7 +117,7 @@ public: cfg_t *cfg; - gl_shader_stage stage; + mesa_shader_stage stage; bool debug_enabled; /* VGRF allocation. */ diff --git a/src/intel/compiler/brw_vue_map.c b/src/intel/compiler/brw_vue_map.c index 646080b2150..9b79f029010 100644 --- a/src/intel/compiler/brw_vue_map.c +++ b/src/intel/compiler/brw_vue_map.c @@ -45,7 +45,7 @@ #include "brw_nir.h" static unsigned -get_var_slots(gl_shader_stage stage, const nir_variable *var) +get_var_slots(mesa_shader_stage stage, const nir_variable *var) { const struct glsl_type *type = var->type; @@ -369,7 +369,7 @@ brw_compute_tess_vue_map(struct intel_vue_map *vue_map, } static const char * -varying_name(brw_varying_slot slot, gl_shader_stage stage) +varying_name(brw_varying_slot slot, mesa_shader_stage stage) { assume(slot < BRW_VARYING_SLOT_COUNT); @@ -385,7 +385,7 @@ varying_name(brw_varying_slot slot, gl_shader_stage stage) void brw_print_vue_map(FILE *fp, const struct intel_vue_map *vue_map, - gl_shader_stage stage) + mesa_shader_stage stage) { const char *layout_name = vue_map->layout == INTEL_VUE_LAYOUT_FIXED ? "fixed" : diff --git a/src/intel/compiler/elk/elk_compiler.c b/src/intel/compiler/elk/elk_compiler.c index b67449183c9..f837c622ccb 100644 --- a/src/intel/compiler/elk/elk_compiler.c +++ b/src/intel/compiler/elk/elk_compiler.c @@ -186,7 +186,7 @@ elk_get_compiler_config_value(const struct elk_compiler *compiler) } unsigned -elk_prog_data_size(gl_shader_stage stage) +elk_prog_data_size(mesa_shader_stage stage) { static const size_t stage_sizes[] = { [MESA_SHADER_VERTEX] = sizeof(struct elk_vs_prog_data), @@ -201,7 +201,7 @@ elk_prog_data_size(gl_shader_stage stage) } unsigned -elk_prog_key_size(gl_shader_stage stage) +elk_prog_key_size(mesa_shader_stage stage) { static const size_t stage_sizes[] = { [MESA_SHADER_VERTEX] = sizeof(struct elk_vs_prog_key), diff --git a/src/intel/compiler/elk/elk_compiler.h b/src/intel/compiler/elk/elk_compiler.h index fbe44a7b0da..3bec57946dd 100644 --- a/src/intel/compiler/elk/elk_compiler.h +++ b/src/intel/compiler/elk/elk_compiler.h @@ -709,7 +709,7 @@ struct elk_stage_prog_data { unsigned nr_params; /**< number of float params/constants */ - gl_shader_stage stage; + mesa_shader_stage stage; /* zero_push_reg is a bitfield which indicates what push registers (if any) * should be zeroed by SW at the start of the shader. The corresponding @@ -1192,7 +1192,7 @@ typedef enum ~VARYING_BIT_POS & ~VARYING_BIT_FACE) void elk_print_vue_map(FILE *fp, const struct intel_vue_map *vue_map, - gl_shader_stage stage); + mesa_shader_stage stage); /** * Convert a VUE slot number into a byte offset within the VUE. @@ -1449,10 +1449,10 @@ uint64_t elk_get_compiler_config_value(const struct elk_compiler *compiler); unsigned -elk_prog_data_size(gl_shader_stage stage); +elk_prog_data_size(mesa_shader_stage stage); unsigned -elk_prog_key_size(gl_shader_stage stage); +elk_prog_key_size(mesa_shader_stage stage); struct elk_compile_params { void *mem_ctx; @@ -1652,7 +1652,7 @@ elk_compile_ff_gs_prog(struct elk_compiler *compiler, unsigned *final_assembly_size); void elk_debug_key_recompile(const struct elk_compiler *c, void *log, - gl_shader_stage stage, + mesa_shader_stage stage, const struct elk_base_prog_key *old_key, const struct elk_base_prog_key *key); @@ -1689,7 +1689,7 @@ elk_cs_get_dispatch_info(const struct intel_device_info *devinfo, */ static inline bool elk_stage_has_packed_dispatch(ASSERTED const struct intel_device_info *devinfo, - gl_shader_stage stage, + mesa_shader_stage stage, const struct elk_stage_prog_data *prog_data) { /* The code below makes assumptions about the hardware's thread dispatch diff --git a/src/intel/compiler/elk/elk_debug_recompile.c b/src/intel/compiler/elk/elk_debug_recompile.c index 17441ccc724..4c0404f9702 100644 --- a/src/intel/compiler/elk/elk_debug_recompile.c +++ b/src/intel/compiler/elk/elk_debug_recompile.c @@ -197,7 +197,7 @@ debug_cs_recompile(const struct elk_compiler *c, void *log, void elk_debug_key_recompile(const struct elk_compiler *c, void *log, - gl_shader_stage stage, + mesa_shader_stage stage, const struct elk_base_prog_key *old_key, const struct elk_base_prog_key *key) { diff --git a/src/intel/compiler/elk/elk_fs.cpp b/src/intel/compiler/elk/elk_fs.cpp index f7c15a166bb..0fd594d9afe 100644 --- a/src/intel/compiler/elk/elk_fs.cpp +++ b/src/intel/compiler/elk/elk_fs.cpp @@ -7178,7 +7178,7 @@ static UNUSED void elk_fs_test_dispatch_packing(const fs_builder &bld) { const elk_fs_visitor *shader = static_cast(bld.shader); - const gl_shader_stage stage = shader->stage; + const mesa_shader_stage stage = shader->stage; const bool uses_vmask = stage == MESA_SHADER_FRAGMENT && elk_wm_prog_data(shader->stage_prog_data)->uses_vmask; diff --git a/src/intel/compiler/elk/elk_fs.h b/src/intel/compiler/elk/elk_fs.h index a6b096825b4..333cb85aaad 100644 --- a/src/intel/compiler/elk/elk_fs.h +++ b/src/intel/compiler/elk/elk_fs.h @@ -445,7 +445,7 @@ public: const struct elk_compile_params *params, struct elk_stage_prog_data *prog_data, bool runtime_check_aads_emit, - gl_shader_stage stage); + mesa_shader_stage stage); ~elk_fs_generator(); void enable_debug(const char *shader_name); @@ -525,7 +525,7 @@ private: bool runtime_check_aads_emit; bool debug_flag; const char *shader_name; - gl_shader_stage stage; + mesa_shader_stage stage; void *mem_ctx; }; diff --git a/src/intel/compiler/elk/elk_fs_generator.cpp b/src/intel/compiler/elk/elk_fs_generator.cpp index 0f150fec67e..dc7a79e88c5 100644 --- a/src/intel/compiler/elk/elk_fs_generator.cpp +++ b/src/intel/compiler/elk/elk_fs_generator.cpp @@ -190,7 +190,7 @@ elk_fs_generator::elk_fs_generator(const struct elk_compiler *compiler, const struct elk_compile_params *params, struct elk_stage_prog_data *prog_data, bool runtime_check_aads_emit, - gl_shader_stage stage) + mesa_shader_stage stage) : compiler(compiler), params(params), devinfo(compiler->devinfo), diff --git a/src/intel/compiler/elk/elk_nir.c b/src/intel/compiler/elk/elk_nir.c index 3b7e7d69231..bca79d8fab5 100644 --- a/src/intel/compiler/elk/elk_nir.c +++ b/src/intel/compiler/elk/elk_nir.c @@ -193,7 +193,7 @@ remap_patch_urb_offsets(nir_block *block, nir_builder *b, nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - gl_shader_stage stage = b->shader->info.stage; + mesa_shader_stage stage = b->shader->info.stage; if ((stage == MESA_SHADER_TESS_CTRL && is_output(intrin)) || (stage == MESA_SHADER_TESS_EVAL && is_input(intrin))) { diff --git a/src/intel/compiler/elk/elk_shader.h b/src/intel/compiler/elk/elk_shader.h index add712559b8..b307d6d3fba 100644 --- a/src/intel/compiler/elk/elk_shader.h +++ b/src/intel/compiler/elk/elk_shader.h @@ -73,7 +73,7 @@ public: elk_cfg_t *cfg; elk_analysis idom_analysis; - gl_shader_stage stage; + mesa_shader_stage stage; bool debug_enabled; elk::simple_allocator alloc; @@ -130,7 +130,7 @@ elk_get_scratch_size(int size) static inline nir_variable_mode elk_nir_no_indirect_mask(const struct elk_compiler *compiler, - gl_shader_stage stage) + mesa_shader_stage stage) { const struct intel_device_info *devinfo = compiler->devinfo; const bool is_scalar = compiler->scalar_stage[stage]; diff --git a/src/intel/compiler/elk/elk_vec4_generator.cpp b/src/intel/compiler/elk/elk_vec4_generator.cpp index cde5726f9b8..c7dc89126f7 100644 --- a/src/intel/compiler/elk/elk_vec4_generator.cpp +++ b/src/intel/compiler/elk/elk_vec4_generator.cpp @@ -109,7 +109,7 @@ generate_math2_gfx4(struct elk_codegen *p, static void generate_tex(struct elk_codegen *p, struct elk_vue_prog_data *prog_data, - gl_shader_stage stage, + mesa_shader_stage stage, vec4_instruction *inst, struct elk_reg dst, struct elk_reg src, diff --git a/src/intel/compiler/elk/elk_vue_map.c b/src/intel/compiler/elk/elk_vue_map.c index 2d0a9e7da8e..d922ca3427b 100644 --- a/src/intel/compiler/elk/elk_vue_map.c +++ b/src/intel/compiler/elk/elk_vue_map.c @@ -284,7 +284,7 @@ elk_compute_tess_vue_map(struct intel_vue_map *vue_map, } static const char * -varying_name(elk_varying_slot slot, gl_shader_stage stage) +varying_name(elk_varying_slot slot, mesa_shader_stage stage) { assume(slot < ELK_VARYING_SLOT_COUNT); @@ -302,7 +302,7 @@ varying_name(elk_varying_slot slot, gl_shader_stage stage) void elk_print_vue_map(FILE *fp, const struct intel_vue_map *vue_map, - gl_shader_stage stage) + mesa_shader_stage stage) { const char *layout_name = vue_map->layout == INTEL_VUE_LAYOUT_FIXED ? "non-SSO" : "SSO"; diff --git a/src/intel/compiler/test_helpers.h b/src/intel/compiler/test_helpers.h index 05f5546ce4b..3c7f774ea2f 100644 --- a/src/intel/compiler/test_helpers.h +++ b/src/intel/compiler/test_helpers.h @@ -129,7 +129,7 @@ protected: } brw_builder - make_shader(gl_shader_stage stage = MESA_SHADER_FRAGMENT, + make_shader(mesa_shader_stage stage = MESA_SHADER_FRAGMENT, unsigned dispatch_width = 0) { if (dispatch_width == 0) diff --git a/src/intel/dev/intel_debug.c b/src/intel/dev/intel_debug.c index f9a50b9b451..ed2afdcd975 100644 --- a/src/intel/dev/intel_debug.c +++ b/src/intel/dev/intel_debug.c @@ -153,7 +153,7 @@ static const struct debug_control simd_control[] = { }; uint64_t -intel_debug_flag_for_shader_stage(gl_shader_stage stage) +intel_debug_flag_for_shader_stage(mesa_shader_stage stage) { uint64_t flags[] = { [MESA_SHADER_VERTEX] = DEBUG_VS, diff --git a/src/intel/dev/intel_debug.h b/src/intel/dev/intel_debug.h index 3d2b6133ba5..19ccfe1a880 100644 --- a/src/intel/dev/intel_debug.h +++ b/src/intel/dev/intel_debug.h @@ -190,7 +190,7 @@ extern uint32_t intel_shader_dump_filter; dbg_printf(__VA_ARGS__); \ } while(0) -extern uint64_t intel_debug_flag_for_shader_stage(gl_shader_stage stage); +extern uint64_t intel_debug_flag_for_shader_stage(mesa_shader_stage stage); extern void process_intel_debug_variable(void); diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c index ce7987160bd..1876e12e0cf 100644 --- a/src/intel/vulkan/anv_allocator.c +++ b/src/intel/vulkan/anv_allocator.c @@ -1376,7 +1376,7 @@ anv_scratch_pool_finish(struct anv_device *device, struct anv_scratch_pool *pool struct anv_bo * anv_scratch_pool_alloc(struct anv_device *device, struct anv_scratch_pool *pool, - gl_shader_stage stage, unsigned per_thread_scratch) + mesa_shader_stage stage, unsigned per_thread_scratch) { if (per_thread_scratch == 0) return NULL; diff --git a/src/intel/vulkan/anv_cmd_buffer.c b/src/intel/vulkan/anv_cmd_buffer.c index 9d4b1a026ed..12a2d39310c 100644 --- a/src/intel/vulkan/anv_cmd_buffer.c +++ b/src/intel/vulkan/anv_cmd_buffer.c @@ -416,7 +416,7 @@ mem_update(void *dst, const void *src, size_t size) static void set_dirty_for_bind_map(struct anv_cmd_buffer *cmd_buffer, - gl_shader_stage stage, + mesa_shader_stage stage, const struct anv_pipeline_bind_map *map) { assert(stage < ARRAY_SIZE(cmd_buffer->state.surface_sha1s)); diff --git a/src/intel/vulkan/anv_internal_kernels.c b/src/intel/vulkan/anv_internal_kernels.c index 1596700ae5e..4c123a3f8f7 100644 --- a/src/intel/vulkan/anv_internal_kernels.c +++ b/src/intel/vulkan/anv_internal_kernels.c @@ -51,7 +51,7 @@ lower_base_workgroup_id(nir_builder *b, nir_intrinsic_instr *intrin, static struct anv_shader_bin * compile_shader(struct anv_device *device, enum anv_internal_kernel_name shader_name, - gl_shader_stage stage, + mesa_shader_stage stage, const char *name, const void *hash_key, uint32_t hash_key_size, @@ -250,7 +250,7 @@ anv_device_get_internal_shader(struct anv_device *device, char name[40]; } key; - gl_shader_stage stage; + mesa_shader_stage stage; uint32_t send_count; } internal_kernels[] = { diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index cd5edd4243a..3d21fed5dd1 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -57,7 +57,7 @@ anv_shader_stage_to_nir(struct anv_device *device, { const struct anv_physical_device *pdevice = device->physical; const struct brw_compiler *compiler = pdevice->compiler; - gl_shader_stage stage = vk_to_mesa_shader_stage(stage_info->stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(stage_info->stage); const nir_shader_compiler_options *nir_options = compiler->nir_options[stage]; @@ -228,7 +228,7 @@ void anv_DestroyPipeline( } struct anv_pipeline_stage { - gl_shader_stage stage; + mesa_shader_stage stage; VkPipelineCreateFlags2KHR pipeline_flags; struct vk_pipeline_robustness_state rstate; @@ -245,7 +245,7 @@ struct anv_pipeline_stage { union brw_any_prog_key key; struct { - gl_shader_stage stage; + mesa_shader_stage stage; unsigned char sha1[20]; } cache_key; @@ -1798,7 +1798,7 @@ static bool anv_graphics_pipeline_skip_shader_compile(struct anv_graphics_base_pipeline *pipeline, struct anv_pipeline_stage *stages, bool link_optimize, - gl_shader_stage stage) + mesa_shader_stage stage) { /* Always skip non active stages */ if (!anv_pipeline_base_has_stage(pipeline, stage)) @@ -2046,7 +2046,7 @@ anv_graphics_pipeline_load_cached_shaders(struct anv_graphics_base_pipeline *pip return false; } -static const gl_shader_stage graphics_shader_order[] = { +static const mesa_shader_stage graphics_shader_order[] = { MESA_SHADER_VERTEX, MESA_SHADER_TESS_CTRL, MESA_SHADER_TESS_EVAL, @@ -2210,7 +2210,7 @@ anv_graphics_pipeline_compile(struct anv_graphics_base_pipeline *pipeline, */ uint32_t shader_count = anv_graphics_pipeline_imported_shader_count(stages); for (uint32_t i = 0; i < info->stageCount; i++) { - gl_shader_stage stage = vk_to_mesa_shader_stage(info->pStages[i].stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(info->pStages[i].stage); /* If a pipeline library is loaded in this stage, we should ignore the * pStages[] entry of the same stage. @@ -2347,7 +2347,7 @@ anv_graphics_pipeline_compile(struct anv_graphics_base_pipeline *pipeline, /* Walk backwards to link */ struct anv_pipeline_stage *next_stage = NULL; for (int i = ARRAY_SIZE(graphics_shader_order) - 1; i >= 0; i--) { - gl_shader_stage s = graphics_shader_order[i]; + mesa_shader_stage s = graphics_shader_order[i]; if (anv_graphics_pipeline_skip_shader_compile(pipeline, stages, link_optimize, s)) continue; @@ -2402,7 +2402,7 @@ anv_graphics_pipeline_compile(struct anv_graphics_base_pipeline *pipeline, struct anv_pipeline_stage *prev_stage = NULL; for (unsigned i = 0; i < ARRAY_SIZE(graphics_shader_order); i++) { - gl_shader_stage s = graphics_shader_order[i]; + mesa_shader_stage s = graphics_shader_order[i]; if (anv_graphics_pipeline_skip_shader_compile(pipeline, stages, link_optimize, s)) continue; @@ -2458,7 +2458,7 @@ anv_graphics_pipeline_compile(struct anv_graphics_base_pipeline *pipeline, struct anv_pipeline_stage *last_psr = NULL; for (unsigned i = 0; i < ARRAY_SIZE(graphics_shader_order); i++) { - gl_shader_stage s = + mesa_shader_stage s = graphics_shader_order[ARRAY_SIZE(graphics_shader_order) - i - 1]; if (anv_graphics_pipeline_skip_shader_compile(pipeline, stages, @@ -2479,7 +2479,7 @@ anv_graphics_pipeline_compile(struct anv_graphics_base_pipeline *pipeline, prev_stage = NULL; for (unsigned i = 0; i < ARRAY_SIZE(graphics_shader_order); i++) { - gl_shader_stage s = graphics_shader_order[i]; + mesa_shader_stage s = graphics_shader_order[i]; struct anv_pipeline_stage *stage = &stages[s]; if (anv_graphics_pipeline_skip_shader_compile(pipeline, stages, link_optimize, s)) @@ -3850,7 +3850,7 @@ anv_pipeline_compile_ray_tracing(struct anv_ray_tracing_pipeline *pipeline, uint32_t stage_count = create_feedback->pipelineStageCreationFeedbackCount; assert(stage_count == 0 || info->stageCount == stage_count); for (uint32_t i = 0; i < stage_count; i++) { - gl_shader_stage s = vk_to_mesa_shader_stage(info->pStages[i].stage); + mesa_shader_stage s = vk_to_mesa_shader_stage(info->pStages[i].stage); create_feedback->pPipelineStageCreationFeedbacks[i] = stages[s].feedback; } } @@ -4304,7 +4304,7 @@ VkResult anv_GetPipelineExecutablePropertiesKHR( util_dynarray_foreach (&pipeline->executables, struct anv_pipeline_executable, exe) { vk_outarray_append_typed(VkPipelineExecutablePropertiesKHR, &out, props) { - gl_shader_stage stage = exe->stage; + mesa_shader_stage stage = exe->stage; props->stages = mesa_to_vk_shader_stage(stage); unsigned simd_width = exe->stats.dispatch_width; diff --git a/src/intel/vulkan/anv_pipeline_cache.c b/src/intel/vulkan/anv_pipeline_cache.c index d063cfa923d..cb8f25fc00f 100644 --- a/src/intel/vulkan/anv_pipeline_cache.c +++ b/src/intel/vulkan/anv_pipeline_cache.c @@ -98,7 +98,7 @@ anv_shader_bin_rewrite_embedded_samplers(struct anv_device *device, static struct anv_shader_bin * anv_shader_bin_create(struct anv_device *device, - gl_shader_stage stage, + mesa_shader_stage stage, const void *key_data, uint32_t key_size, const void *kernel_data, uint32_t kernel_size, const struct brw_stage_prog_data *prog_data_in, @@ -362,7 +362,7 @@ anv_shader_bin_deserialize(struct vk_pipeline_cache *cache, struct anv_device *device = container_of(cache->base.device, struct anv_device, vk); - gl_shader_stage stage = blob_read_uint32(blob); + mesa_shader_stage stage = blob_read_uint32(blob); uint32_t kernel_size = blob_read_uint32(blob); const void *kernel_data = blob_read_bytes(blob, kernel_size); diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index a8eed0cec2b..52b914d3a43 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -992,7 +992,7 @@ void anv_scratch_pool_finish(struct anv_device *device, struct anv_scratch_pool *pool); struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device, struct anv_scratch_pool *pool, - gl_shader_stage stage, + mesa_shader_stage stage, unsigned per_thread_scratch); uint32_t anv_scratch_pool_get_surf(struct anv_device *device, struct anv_scratch_pool *pool, @@ -4623,7 +4623,7 @@ anv_cmd_buffer_descriptor_buffer_address(struct anv_cmd_buffer *cmd_buffer, static inline bool anv_cmd_buffer_has_gfx_stage(struct anv_cmd_buffer *cmd_buffer, - gl_shader_stage stage) + mesa_shader_stage stage) { return cmd_buffer->state.gfx.shaders[stage] != NULL; } @@ -4827,8 +4827,8 @@ struct anv_event { #define ANV_STAGE_MASK ((1 << MESA_VULKAN_SHADER_STAGES) - 1) #define anv_foreach_stage(stage, stage_bits) \ - for (gl_shader_stage stage, \ - __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \ + for (mesa_shader_stage stage, \ + __tmp = (mesa_shader_stage)((stage_bits) & ANV_STAGE_MASK); \ stage = __builtin_ffs(__tmp) - 1, __tmp; \ __tmp &= ~(1 << (stage))) @@ -4864,7 +4864,7 @@ struct anv_push_descriptor_info { }; struct anv_shader_upload_params { - gl_shader_stage stage; + mesa_shader_stage stage; const void *key_data; uint32_t key_size; @@ -4915,7 +4915,7 @@ anv_device_get_embedded_samplers(struct anv_device *device, struct anv_shader_bin { struct vk_pipeline_cache_object base; - gl_shader_stage stage; + mesa_shader_stage stage; struct anv_state kernel; uint32_t kernel_size; @@ -4954,7 +4954,7 @@ anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader) } struct anv_pipeline_executable { - gl_shader_stage stage; + mesa_shader_stage stage; struct brw_compile_stats stats; @@ -5283,14 +5283,14 @@ anv_pipeline_to_graphics_base(struct anv_pipeline *pipeline) static inline bool anv_pipeline_has_stage(const struct anv_graphics_pipeline *pipeline, - gl_shader_stage stage) + mesa_shader_stage stage) { return (pipeline->base.base.active_stages & mesa_to_vk_shader_stage(stage)) != 0; } static inline bool anv_pipeline_base_has_stage(const struct anv_graphics_base_pipeline *pipeline, - gl_shader_stage stage) + mesa_shader_stage stage) { return (pipeline->base.active_stages & mesa_to_vk_shader_stage(stage)) != 0; } @@ -5309,7 +5309,7 @@ anv_pipeline_is_mesh(const struct anv_graphics_pipeline *pipeline) static inline bool anv_gfx_has_stage(const struct anv_cmd_graphics_state *gfx, - gl_shader_stage stage) + mesa_shader_stage stage) { return (gfx->active_stages & mesa_to_vk_shader_stage(stage)) != 0; } diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index afb0cd967c4..1ad3aaaf553 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2321,7 +2321,7 @@ genX(cmd_buffer_flush_descriptor_sets)(struct anv_cmd_buffer *cmd_buffer, if (!shaders[i]) continue; - gl_shader_stage stage = shaders[i]->stage; + mesa_shader_stage stage = shaders[i]->stage; VkShaderStageFlags vk_stage = mesa_to_vk_shader_stage(stage); if ((vk_stage & dirty) == 0) continue; @@ -2360,7 +2360,7 @@ genX(cmd_buffer_flush_descriptor_sets)(struct anv_cmd_buffer *cmd_buffer, if (!shaders[i]) continue; - gl_shader_stage stage = shaders[i]->stage; + mesa_shader_stage stage = shaders[i]->stage; result = emit_samplers(cmd_buffer, pipe_state, shaders[i], &cmd_buffer->state.samplers[stage]); diff --git a/src/intel/vulkan/genX_cmd_compute.c b/src/intel/vulkan/genX_cmd_compute.c index 8807c6d0fbd..5894e77a9fe 100644 --- a/src/intel/vulkan/genX_cmd_compute.c +++ b/src/intel/vulkan/genX_cmd_compute.c @@ -1341,7 +1341,7 @@ cmd_buffer_trace_rays(struct anv_cmd_buffer *cmd_buffer, struct intel_cs_dispatch_info dispatch = brw_cs_get_dispatch_info(device->info, cs_prog_data, NULL); - const gl_shader_stage s = MESA_SHADER_RAYGEN; + const mesa_shader_stage s = MESA_SHADER_RAYGEN; struct anv_state *surfaces = &cmd_buffer->state.binding_tables[s]; struct anv_state *samplers = &cmd_buffer->state.samplers[s]; struct brw_rt_raygen_trampoline_params trampoline_params = { diff --git a/src/intel/vulkan/genX_cmd_draw.c b/src/intel/vulkan/genX_cmd_draw.c index 792e6d9ab55..698df9c7231 100644 --- a/src/intel/vulkan/genX_cmd_draw.c +++ b/src/intel/vulkan/genX_cmd_draw.c @@ -311,7 +311,7 @@ get_push_range_bound_size(struct anv_cmd_buffer *cmd_buffer, static void cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer, - gl_shader_stage stage, + mesa_shader_stage stage, struct anv_address *buffers, unsigned buffer_count) { @@ -395,7 +395,7 @@ cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer *cmd_buffer, const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx; - gl_shader_stage stage = vk_to_mesa_shader_stage(shader_mask); + mesa_shader_stage stage = vk_to_mesa_shader_stage(shader_mask); const struct anv_pipeline_bind_map *bind_map = &gfx->shaders[stage]->bind_map; @@ -584,7 +584,7 @@ cmd_buffer_flush_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer, static inline uint64_t get_mesh_task_push_addr64(struct anv_cmd_buffer *cmd_buffer, struct anv_cmd_graphics_state *gfx, - gl_shader_stage stage) + mesa_shader_stage stage) { const struct anv_shader_bin *shader = gfx->shaders[stage]; const struct anv_pipeline_bind_map *bind_map = &shader->bind_map; diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index af63244e872..7d6dfbd2f30 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -864,7 +864,7 @@ get_sampler_count(const struct anv_shader_bin *bin) static UNUSED struct anv_address get_scratch_address(struct anv_pipeline *pipeline, - gl_shader_stage stage, + mesa_shader_stage stage, const struct anv_shader_bin *bin) { return (struct anv_address) { @@ -883,7 +883,7 @@ get_scratch_space(const struct anv_shader_bin *bin) static UNUSED uint32_t get_scratch_surf(struct anv_pipeline *pipeline, - gl_shader_stage stage, + mesa_shader_stage stage, const struct anv_shader_bin *bin, bool protected) { diff --git a/src/intel/vulkan_hasvk/anv_allocator.c b/src/intel/vulkan_hasvk/anv_allocator.c index 15a62623420..94403f385fd 100644 --- a/src/intel/vulkan_hasvk/anv_allocator.c +++ b/src/intel/vulkan_hasvk/anv_allocator.c @@ -1426,7 +1426,7 @@ anv_scratch_pool_finish(struct anv_device *device, struct anv_scratch_pool *pool struct anv_bo * anv_scratch_pool_alloc(struct anv_device *device, struct anv_scratch_pool *pool, - gl_shader_stage stage, unsigned per_thread_scratch) + mesa_shader_stage stage, unsigned per_thread_scratch) { if (per_thread_scratch == 0) return NULL; diff --git a/src/intel/vulkan_hasvk/anv_cmd_buffer.c b/src/intel/vulkan_hasvk/anv_cmd_buffer.c index 6b7198f6af8..b5af8364248 100644 --- a/src/intel/vulkan_hasvk/anv_cmd_buffer.c +++ b/src/intel/vulkan_hasvk/anv_cmd_buffer.c @@ -248,7 +248,7 @@ mem_update(void *dst, const void *src, size_t size) static void set_dirty_for_bind_map(struct anv_cmd_buffer *cmd_buffer, - gl_shader_stage stage, + mesa_shader_stage stage, const struct anv_pipeline_bind_map *map) { assert(stage < ARRAY_SIZE(cmd_buffer->state.surface_sha1s)); diff --git a/src/intel/vulkan_hasvk/anv_pipeline.c b/src/intel/vulkan_hasvk/anv_pipeline.c index c94ed3c15b7..6e4d6bc16ea 100644 --- a/src/intel/vulkan_hasvk/anv_pipeline.c +++ b/src/intel/vulkan_hasvk/anv_pipeline.c @@ -55,7 +55,7 @@ anv_shader_stage_to_nir(struct anv_device *device, { const struct anv_physical_device *pdevice = device->physical; const struct elk_compiler *compiler = pdevice->compiler; - gl_shader_stage stage = vk_to_mesa_shader_stage(stage_info->stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(stage_info->stage); const nir_shader_compiler_options *nir_options = compiler->nir_options[stage]; @@ -335,7 +335,7 @@ populate_cs_prog_key(const struct anv_device *device, } struct anv_pipeline_stage { - gl_shader_stage stage; + mesa_shader_stage stage; VkPipelineCreateFlags2KHR pipeline_flags; const VkPipelineShaderStageCreateInfo *info; @@ -345,7 +345,7 @@ struct anv_pipeline_stage { union elk_any_prog_key key; struct { - gl_shader_stage stage; + mesa_shader_stage stage; unsigned char sha1[20]; } cache_key; @@ -1166,7 +1166,7 @@ anv_graphics_pipeline_load_cached_shaders(struct anv_graphics_pipeline *pipeline return false; } -static const gl_shader_stage graphics_shader_order[] = { +static const mesa_shader_stage graphics_shader_order[] = { MESA_SHADER_VERTEX, MESA_SHADER_TESS_CTRL, MESA_SHADER_TESS_EVAL, @@ -1182,7 +1182,7 @@ anv_graphics_pipeline_load_nir(struct anv_graphics_pipeline *pipeline, void *pipeline_ctx) { for (unsigned i = 0; i < ARRAY_SIZE(graphics_shader_order); i++) { - gl_shader_stage s = graphics_shader_order[i]; + mesa_shader_stage s = graphics_shader_order[i]; if (!stages[s].info) continue; @@ -1229,7 +1229,7 @@ anv_graphics_pipeline_compile(struct anv_graphics_pipeline *pipeline, const struct elk_compiler *compiler = pipeline->base.device->physical->compiler; struct anv_pipeline_stage stages[ANV_GRAPHICS_SHADER_STAGE_COUNT] = {}; for (uint32_t i = 0; i < info->stageCount; i++) { - gl_shader_stage stage = vk_to_mesa_shader_stage(info->pStages[i].stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(info->pStages[i].stage); stages[stage].stage = stage; stages[stage].pipeline_flags = pipeline_flags; stages[stage].info = &info->pStages[i]; @@ -1271,7 +1271,7 @@ anv_graphics_pipeline_compile(struct anv_graphics_pipeline *pipeline, /* Walk backwards to link */ struct anv_pipeline_stage *next_stage = NULL; for (int i = ARRAY_SIZE(graphics_shader_order) - 1; i >= 0; i--) { - gl_shader_stage s = graphics_shader_order[i]; + mesa_shader_stage s = graphics_shader_order[i]; if (!stages[s].info) continue; @@ -1300,7 +1300,7 @@ anv_graphics_pipeline_compile(struct anv_graphics_pipeline *pipeline, struct anv_pipeline_stage *prev_stage = NULL; for (unsigned i = 0; i < ARRAY_SIZE(graphics_shader_order); i++) { - gl_shader_stage s = graphics_shader_order[i]; + mesa_shader_stage s = graphics_shader_order[i]; if (!stages[s].info) continue; @@ -1328,7 +1328,7 @@ anv_graphics_pipeline_compile(struct anv_graphics_pipeline *pipeline, prev_stage = NULL; for (unsigned i = 0; i < ARRAY_SIZE(graphics_shader_order); i++) { - gl_shader_stage s = graphics_shader_order[i]; + mesa_shader_stage s = graphics_shader_order[i]; if (!stages[s].info) continue; @@ -1410,7 +1410,7 @@ done: uint32_t stage_count = create_feedback->pipelineStageCreationFeedbackCount; assert(stage_count == 0 || info->stageCount == stage_count); for (uint32_t i = 0; i < stage_count; i++) { - gl_shader_stage s = vk_to_mesa_shader_stage(info->pStages[i].stage); + mesa_shader_stage s = vk_to_mesa_shader_stage(info->pStages[i].stage); create_feedback->pPipelineStageCreationFeedbacks[i] = stages[s].feedback; } } @@ -1911,7 +1911,7 @@ VkResult anv_GetPipelineExecutablePropertiesKHR( util_dynarray_foreach (&pipeline->executables, struct anv_pipeline_executable, exe) { vk_outarray_append_typed(VkPipelineExecutablePropertiesKHR, &out, props) { - gl_shader_stage stage = exe->stage; + mesa_shader_stage stage = exe->stage; props->stages = mesa_to_vk_shader_stage(stage); unsigned simd_width = exe->stats.dispatch_width; diff --git a/src/intel/vulkan_hasvk/anv_pipeline_cache.c b/src/intel/vulkan_hasvk/anv_pipeline_cache.c index 4106d829426..8c30c42c346 100644 --- a/src/intel/vulkan_hasvk/anv_pipeline_cache.c +++ b/src/intel/vulkan_hasvk/anv_pipeline_cache.c @@ -67,7 +67,7 @@ const struct vk_pipeline_cache_object_ops *const anv_cache_import_ops[2] = { struct anv_shader_bin * anv_shader_bin_create(struct anv_device *device, - gl_shader_stage stage, + mesa_shader_stage stage, const void *key_data, uint32_t key_size, const void *kernel_data, uint32_t kernel_size, const struct elk_stage_prog_data *prog_data_in, @@ -224,7 +224,7 @@ anv_shader_bin_deserialize(struct vk_pipeline_cache *cache, struct anv_device *device = container_of(cache->base.device, struct anv_device, vk); - gl_shader_stage stage = blob_read_uint32(blob); + mesa_shader_stage stage = blob_read_uint32(blob); uint32_t kernel_size = blob_read_uint32(blob); const void *kernel_data = blob_read_bytes(blob, kernel_size); @@ -306,7 +306,7 @@ anv_device_search_for_kernel(struct anv_device *device, struct anv_shader_bin * anv_device_upload_kernel(struct anv_device *device, struct vk_pipeline_cache *cache, - gl_shader_stage stage, + mesa_shader_stage stage, const void *key_data, uint32_t key_size, const void *kernel_data, uint32_t kernel_size, const struct elk_stage_prog_data *prog_data, diff --git a/src/intel/vulkan_hasvk/anv_private.h b/src/intel/vulkan_hasvk/anv_private.h index d8a7b437036..4bea281117b 100644 --- a/src/intel/vulkan_hasvk/anv_private.h +++ b/src/intel/vulkan_hasvk/anv_private.h @@ -785,7 +785,7 @@ void anv_scratch_pool_finish(struct anv_device *device, struct anv_scratch_pool *pool); struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device, struct anv_scratch_pool *pool, - gl_shader_stage stage, + mesa_shader_stage stage, unsigned per_thread_scratch); /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */ @@ -978,7 +978,7 @@ anv_device_search_for_kernel(struct anv_device *device, struct anv_shader_bin * anv_device_upload_kernel(struct anv_device *device, struct vk_pipeline_cache *cache, - gl_shader_stage stage, + mesa_shader_stage stage, const void *key_data, uint32_t key_size, const void *kernel_data, uint32_t kernel_size, const struct elk_stage_prog_data *prog_data, @@ -2743,8 +2743,8 @@ struct anv_event { #define ANV_STAGE_MASK ((1 << MESA_VULKAN_SHADER_STAGES) - 1) #define anv_foreach_stage(stage, stage_bits) \ - for (gl_shader_stage stage, \ - __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \ + for (mesa_shader_stage stage, \ + __tmp = (mesa_shader_stage)((stage_bits) & ANV_STAGE_MASK); \ stage = __builtin_ffs(__tmp) - 1, __tmp; \ __tmp &= ~(1 << (stage))) @@ -2765,7 +2765,7 @@ struct anv_pipeline_bind_map { struct anv_shader_bin { struct vk_pipeline_cache_object base; - gl_shader_stage stage; + mesa_shader_stage stage; struct anv_state kernel; uint32_t kernel_size; @@ -2783,7 +2783,7 @@ struct anv_shader_bin { struct anv_shader_bin * anv_shader_bin_create(struct anv_device *device, - gl_shader_stage stage, + mesa_shader_stage stage, const void *key, uint32_t key_size, const void *kernel, uint32_t kernel_size, const struct elk_stage_prog_data *prog_data, @@ -2805,7 +2805,7 @@ anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader) } struct anv_pipeline_executable { - gl_shader_stage stage; + mesa_shader_stage stage; struct elk_compile_stats stats; @@ -2921,7 +2921,7 @@ ANV_DECL_PIPELINE_DOWNCAST(compute, ANV_PIPELINE_COMPUTE) static inline bool anv_pipeline_has_stage(const struct anv_graphics_pipeline *pipeline, - gl_shader_stage stage) + mesa_shader_stage stage) { return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0; } diff --git a/src/intel/vulkan_hasvk/genX_cmd_buffer.c b/src/intel/vulkan_hasvk/genX_cmd_buffer.c index 079e598d04c..108b6358ed3 100644 --- a/src/intel/vulkan_hasvk/genX_cmd_buffer.c +++ b/src/intel/vulkan_hasvk/genX_cmd_buffer.c @@ -2465,7 +2465,7 @@ flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer, if (!shaders[i]) continue; - gl_shader_stage stage = shaders[i]->stage; + mesa_shader_stage stage = shaders[i]->stage; VkShaderStageFlags vk_stage = mesa_to_vk_shader_stage(stage); if ((vk_stage & dirty) == 0) continue; @@ -2504,7 +2504,7 @@ flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer, if (!shaders[i]) continue; - gl_shader_stage stage = shaders[i]->stage; + mesa_shader_stage stage = shaders[i]->stage; result = emit_samplers(cmd_buffer, pipe_state, shaders[i], &cmd_buffer->state.samplers[stage]); @@ -2712,7 +2712,7 @@ get_push_range_bound_size(struct anv_cmd_buffer *cmd_buffer, static void cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer, - gl_shader_stage stage, + mesa_shader_stage stage, struct anv_address *buffers, unsigned buffer_count) { diff --git a/src/intel/vulkan_hasvk/genX_pipeline.c b/src/intel/vulkan_hasvk/genX_pipeline.c index deb0467d58c..fa8dc44023d 100644 --- a/src/intel/vulkan_hasvk/genX_pipeline.c +++ b/src/intel/vulkan_hasvk/genX_pipeline.c @@ -1303,7 +1303,7 @@ get_sampler_count(const struct anv_shader_bin *bin) static UNUSED struct anv_address get_scratch_address(struct anv_pipeline *pipeline, - gl_shader_stage stage, + mesa_shader_stage stage, const struct anv_shader_bin *bin) { return (struct anv_address) { diff --git a/src/mesa/main/arbprogram.c b/src/mesa/main/arbprogram.c index 0afae5ceeb7..b8aadcdeeba 100644 --- a/src/mesa/main/arbprogram.c +++ b/src/mesa/main/arbprogram.c @@ -391,7 +391,7 @@ set_program_string(struct gl_program *prog, GLenum target, GLenum format, GLsize #ifdef ENABLE_SHADER_CACHE GLcharARB *replacement; - gl_shader_stage stage = _mesa_program_enum_to_shader_stage(target); + mesa_shader_stage stage = _mesa_program_enum_to_shader_stage(target); blake3_hash blake3; _mesa_blake3_compute(string, len, blake3); diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index f329f4da4e7..8e77c8a82b8 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -274,7 +274,7 @@ _mesa_init_current(struct gl_context *ctx) * Important: drivers should override these with actual limits. */ static void -init_program_limits(struct gl_constants *consts, gl_shader_stage stage, +init_program_limits(struct gl_constants *consts, mesa_shader_stage stage, struct gl_program_constants *prog) { prog->MaxInstructions = MAX_PROGRAM_INSTRUCTIONS; diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h index eee9f8786f2..5d1bf43c2fa 100644 --- a/src/mesa/main/dd.h +++ b/src/mesa/main/dd.h @@ -115,7 +115,7 @@ struct dd_function_table { */ /** Allocate a new program */ struct gl_program * (*NewProgram)(struct gl_context *ctx, - gl_shader_stage stage, + mesa_shader_stage stage, GLuint id, bool is_arb_asm); /** * \name Draw functions. diff --git a/src/mesa/main/glspirv.c b/src/mesa/main/glspirv.c index ac68881c67b..3213e9a04b6 100644 --- a/src/mesa/main/glspirv.c +++ b/src/mesa/main/glspirv.c @@ -140,7 +140,7 @@ _mesa_spirv_link_shaders(struct gl_context *ctx, struct gl_shader_program *prog) for (unsigned i = 0; i < prog->NumShaders; i++) { struct gl_shader *shader = prog->Shaders[i]; - gl_shader_stage shader_type = shader->Stage; + mesa_shader_stage shader_type = shader->Stage; /* We only support one shader per stage. The gl_spirv spec doesn't seem * to prevent this, but the way the API is designed, requiring all shaders @@ -196,7 +196,7 @@ _mesa_spirv_link_shaders(struct gl_context *ctx, struct gl_shader_program *prog) /* Some shaders have to be linked with some other shaders present. */ if (!prog->SeparateShader) { static const struct { - gl_shader_stage a, b; + mesa_shader_stage a, b; } stage_pairs[] = { { MESA_SHADER_GEOMETRY, MESA_SHADER_VERTEX }, { MESA_SHADER_TESS_EVAL, MESA_SHADER_VERTEX }, @@ -205,8 +205,8 @@ _mesa_spirv_link_shaders(struct gl_context *ctx, struct gl_shader_program *prog) }; for (unsigned i = 0; i < ARRAY_SIZE(stage_pairs); i++) { - gl_shader_stage a = stage_pairs[i].a; - gl_shader_stage b = stage_pairs[i].b; + mesa_shader_stage a = stage_pairs[i].a; + mesa_shader_stage b = stage_pairs[i].b; if ((prog->data->linked_stages & ((1 << a) | (1 << b))) == (1 << a)) { ralloc_asprintf_append(&prog->data->InfoLog, "%s shader must be linked with %s shader\n", @@ -232,7 +232,7 @@ _mesa_spirv_link_shaders(struct gl_context *ctx, struct gl_shader_program *prog) nir_shader * _mesa_spirv_to_nir(struct gl_context *ctx, const struct gl_shader_program *prog, - gl_shader_stage stage, + mesa_shader_stage stage, const nir_shader_compiler_options *options) { struct gl_linked_shader *linked_shader = prog->_LinkedShaders[stage]; diff --git a/src/mesa/main/glspirv.h b/src/mesa/main/glspirv.h index 58248dc7661..734f3b3c34d 100644 --- a/src/mesa/main/glspirv.h +++ b/src/mesa/main/glspirv.h @@ -88,7 +88,7 @@ _mesa_spirv_link_shaders(struct gl_context *ctx, nir_shader * _mesa_spirv_to_nir(struct gl_context *ctx, const struct gl_shader_program *prog, - gl_shader_stage stage, + mesa_shader_stage stage, const nir_shader_compiler_options *options); #ifdef __cplusplus diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c index 8ab83fc72f1..2f572db7da8 100644 --- a/src/mesa/main/pipelineobj.c +++ b/src/mesa/main/pipelineobj.c @@ -207,7 +207,7 @@ static void use_program_stage(struct gl_context *ctx, GLenum type, struct gl_shader_program *shProg, struct gl_pipeline_object *pipe) { - gl_shader_stage stage = _mesa_shader_enum_to_shader_stage(type); + mesa_shader_stage stage = _mesa_shader_enum_to_shader_stage(type); struct gl_program *prog = NULL; if (shProg && shProg->_LinkedShaders[stage]) prog = shProg->_LinkedShaders[stage]->Program; diff --git a/src/mesa/main/shader_types.h b/src/mesa/main/shader_types.h index 4f8a6cc3cf7..2e21ba52709 100644 --- a/src/mesa/main/shader_types.h +++ b/src/mesa/main/shader_types.h @@ -155,7 +155,7 @@ struct gl_shader * Must be the first field. */ GLenum16 Type; - gl_shader_stage Stage; + mesa_shader_stage Stage; GLuint Name; /**< AKA the handle */ GLint RefCount; /**< Reference count */ GLchar *Label; /**< GL_KHR_debug */ @@ -248,7 +248,7 @@ struct gl_shader */ struct gl_linked_shader { - gl_shader_stage Stage; + mesa_shader_stage Stage; struct gl_program *Program; /**< Post-compile assembly code */ diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c index 06c705d961a..78b97827fd3 100644 --- a/src/mesa/main/shaderapi.c +++ b/src/mesa/main/shaderapi.c @@ -82,7 +82,7 @@ // original glsl shader blake3 const char *blake3; // shader stage - gl_shader_stage stage; + mesa_shader_stage stage; ... any other information ... }; struct _shader_replacement shader_replacements[...]; @@ -103,7 +103,7 @@ struct _shader_replacement { const char *app; const char *blake3; - gl_shader_stage stage; + mesa_shader_stage stage; }; struct _shader_replacement shader_replacements[0]; @@ -202,7 +202,7 @@ _mesa_init_shader_state(struct gl_context *ctx) * are generated by the GLSL compiler. */ struct gl_shader_compiler_options options; - gl_shader_stage sh; + mesa_shader_stage sh; int i; memset(&options, 0, sizeof(options)); @@ -1932,7 +1932,7 @@ _mesa_LinkProgram(GLuint programObj) * /_.arb */ static char * -construct_name(const gl_shader_stage stage, const char *blake3_str, +construct_name(const mesa_shader_stage stage, const char *blake3_str, const char *source, const char *path) { static const char *types[] = { @@ -1948,7 +1948,7 @@ construct_name(const gl_shader_stage stage, const char *blake3_str, * Write given shader source to a file in MESA_SHADER_DUMP_PATH. */ void -_mesa_dump_shader_source(const gl_shader_stage stage, const char *source, +_mesa_dump_shader_source(const mesa_shader_stage stage, const char *source, const blake3_hash blake3) { #ifndef CUSTOM_SHADER_REPLACEMENT @@ -1987,7 +1987,7 @@ _mesa_dump_shader_source(const gl_shader_stage stage, const char *source, * Useful for debugging to override an app's shader. */ GLcharARB * -_mesa_read_shader_source(const gl_shader_stage stage, const char *source, +_mesa_read_shader_source(const mesa_shader_stage stage, const char *source, const blake3_hash blake3) { char *read_path; @@ -2602,7 +2602,7 @@ _mesa_ProgramParameteri(GLuint program, GLenum pname, GLint value) void -_mesa_use_program(struct gl_context *ctx, gl_shader_stage stage, +_mesa_use_program(struct gl_context *ctx, mesa_shader_stage stage, struct gl_shader_program *shProg, struct gl_program *prog, struct gl_pipeline_object *shTarget) { @@ -2790,7 +2790,7 @@ _mesa_GetSubroutineUniformLocation(GLuint program, GLenum shadertype, const char *api_name = "glGetSubroutineUniformLocation"; struct gl_shader_program *shProg; GLenum resource_type; - gl_shader_stage stage; + mesa_shader_stage stage; if (!_mesa_validate_shader_target(ctx, shadertype)) { _mesa_error(ctx, GL_INVALID_OPERATION, "%s", api_name); @@ -2820,7 +2820,7 @@ _mesa_GetSubroutineIndex(GLuint program, GLenum shadertype, struct gl_shader_program *shProg; struct gl_program_resource *res; GLenum resource_type; - gl_shader_stage stage; + mesa_shader_stage stage; if (!_mesa_validate_shader_target(ctx, shadertype)) { _mesa_error(ctx, GL_INVALID_OPERATION, "%s", api_name); @@ -2855,7 +2855,7 @@ _mesa_GetActiveSubroutineUniformiv(GLuint program, GLenum shadertype, const char *api_name = "glGetActiveSubroutineUniformiv"; struct gl_shader_program *shProg; struct gl_linked_shader *sh; - gl_shader_stage stage; + mesa_shader_stage stage; struct gl_program_resource *res; const struct gl_uniform_storage *uni; GLenum resource_type; @@ -2941,7 +2941,7 @@ _mesa_GetActiveSubroutineUniformName(GLuint program, GLenum shadertype, const char *api_name = "glGetActiveSubroutineUniformName"; struct gl_shader_program *shProg; GLenum resource_type; - gl_shader_stage stage; + mesa_shader_stage stage; if (!_mesa_validate_shader_target(ctx, shadertype)) { _mesa_error(ctx, GL_INVALID_OPERATION, "%s", api_name); @@ -2975,7 +2975,7 @@ _mesa_GetActiveSubroutineName(GLuint program, GLenum shadertype, const char *api_name = "glGetActiveSubroutineName"; struct gl_shader_program *shProg; GLenum resource_type; - gl_shader_stage stage; + mesa_shader_stage stage; if (!_mesa_validate_shader_target(ctx, shadertype)) { _mesa_error(ctx, GL_INVALID_OPERATION, "%s", api_name); @@ -3003,7 +3003,7 @@ _mesa_UniformSubroutinesuiv(GLenum shadertype, GLsizei count, { GET_CURRENT_CONTEXT(ctx); const char *api_name = "glUniformSubroutinesuiv"; - gl_shader_stage stage; + mesa_shader_stage stage; int i; if (!_mesa_validate_shader_target(ctx, shadertype)) { @@ -3078,7 +3078,7 @@ _mesa_GetUniformSubroutineuiv(GLenum shadertype, GLint location, { GET_CURRENT_CONTEXT(ctx); const char *api_name = "glGetUniformSubroutineuiv"; - gl_shader_stage stage; + mesa_shader_stage stage; if (!_mesa_validate_shader_target(ctx, shadertype)) { _mesa_error(ctx, GL_INVALID_OPERATION, "%s", api_name); @@ -3109,7 +3109,7 @@ _mesa_GetProgramStageiv(GLuint program, GLenum shadertype, const char *api_name = "glGetProgramStageiv"; struct gl_shader_program *shProg; struct gl_linked_shader *sh; - gl_shader_stage stage; + mesa_shader_stage stage; if (!_mesa_validate_shader_target(ctx, shadertype)) { _mesa_error(ctx, GL_INVALID_OPERATION, "%s", api_name); @@ -3777,7 +3777,7 @@ _mesa_shader_write_subroutine_index(struct gl_context *ctx, void _mesa_shader_write_subroutine_indices(struct gl_context *ctx, - gl_shader_stage stage) + mesa_shader_stage stage) { if (ctx->_Shader->CurrentProgram[stage]) _mesa_shader_write_subroutine_index(ctx, diff --git a/src/mesa/main/shaderapi.h b/src/mesa/main/shaderapi.h index 334b4c477ab..76e9d4ad55f 100644 --- a/src/mesa/main/shaderapi.h +++ b/src/mesa/main/shaderapi.h @@ -81,10 +81,10 @@ _mesa_longest_attribute_name_length(struct gl_shader_program *shProg); extern void _mesa_shader_write_subroutine_indices(struct gl_context *ctx, - gl_shader_stage stage); + mesa_shader_stage stage); void -_mesa_use_program(struct gl_context *ctx, gl_shader_stage stage, +_mesa_use_program(struct gl_context *ctx, mesa_shader_stage stage, struct gl_shader_program *shProg, struct gl_program *prog, struct gl_pipeline_object *shTarget); @@ -173,11 +173,11 @@ _mesa_program_init_subroutine_defaults(struct gl_context *ctx, struct gl_program *prog); GLcharARB * -_mesa_read_shader_source(const gl_shader_stage stage, const char *source, +_mesa_read_shader_source(const mesa_shader_stage stage, const char *source, const blake3_hash blake3); void -_mesa_dump_shader_source(const gl_shader_stage stage, const char *source, +_mesa_dump_shader_source(const mesa_shader_stage stage, const char *source, const blake3_hash blake3); void diff --git a/src/mesa/main/shaderobj.c b/src/mesa/main/shaderobj.c index a51c4efdd9c..c68d86cd6f2 100644 --- a/src/mesa/main/shaderobj.c +++ b/src/mesa/main/shaderobj.c @@ -102,7 +102,7 @@ _mesa_reference_shader(struct gl_context *ctx, struct gl_shader **ptr, * Allocate a new gl_shader object, initialize it. */ struct gl_shader * -_mesa_new_shader(GLuint name, gl_shader_stage stage) +_mesa_new_shader(GLuint name, mesa_shader_stage stage) { struct gl_shader *shader; shader = rzalloc(NULL, struct gl_shader); @@ -323,7 +323,7 @@ void _mesa_clear_shader_program_data(struct gl_context *ctx, struct gl_shader_program *shProg) { - for (gl_shader_stage sh = 0; sh < MESA_SHADER_STAGES; sh++) { + for (mesa_shader_stage sh = 0; sh < MESA_SHADER_STAGES; sh++) { if (shProg->_LinkedShaders[sh] != NULL) { _mesa_delete_linked_shader(ctx, shProg->_LinkedShaders[sh]); shProg->_LinkedShaders[sh] = NULL; diff --git a/src/mesa/main/shaderobj.h b/src/mesa/main/shaderobj.h index 7209b29122c..e8c58446298 100644 --- a/src/mesa/main/shaderobj.h +++ b/src/mesa/main/shaderobj.h @@ -83,7 +83,7 @@ _mesa_reference_shader_program(struct gl_context *ctx, } extern struct gl_shader * -_mesa_new_shader(GLuint name, gl_shader_stage type); +_mesa_new_shader(GLuint name, mesa_shader_stage type); extern void _mesa_delete_shader(struct gl_context *ctx, struct gl_shader *sh); @@ -121,7 +121,7 @@ extern void _mesa_delete_shader_program(struct gl_context *ctx, struct gl_shader_program *shProg); -static inline gl_shader_stage +static inline mesa_shader_stage _mesa_shader_enum_to_shader_stage(GLenum v) { switch (v) { @@ -145,7 +145,7 @@ _mesa_shader_enum_to_shader_stage(GLenum v) /* 8 bytes + another underscore */ #define MESA_SUBROUTINE_PREFIX_LEN 9 static inline const char * -_mesa_shader_stage_to_subroutine_prefix(gl_shader_stage stage) +_mesa_shader_stage_to_subroutine_prefix(mesa_shader_stage stage) { switch (stage) { case MESA_SHADER_VERTEX: @@ -165,7 +165,7 @@ _mesa_shader_stage_to_subroutine_prefix(gl_shader_stage stage) } } -static inline gl_shader_stage +static inline mesa_shader_stage _mesa_shader_stage_from_subroutine_uniform(GLenum subuniform) { switch (subuniform) { @@ -185,7 +185,7 @@ _mesa_shader_stage_from_subroutine_uniform(GLenum subuniform) UNREACHABLE("not reached"); } -static inline gl_shader_stage +static inline mesa_shader_stage _mesa_shader_stage_from_subroutine(GLenum subroutine) { switch (subroutine) { @@ -207,7 +207,7 @@ _mesa_shader_stage_from_subroutine(GLenum subroutine) } static inline GLenum -_mesa_shader_stage_to_subroutine(gl_shader_stage stage) +_mesa_shader_stage_to_subroutine(mesa_shader_stage stage) { switch (stage) { case MESA_SHADER_VERTEX: @@ -228,7 +228,7 @@ _mesa_shader_stage_to_subroutine(gl_shader_stage stage) } static inline GLenum -_mesa_shader_stage_to_subroutine_uniform(gl_shader_stage stage) +_mesa_shader_stage_to_subroutine_uniform(mesa_shader_stage stage) { switch (stage) { case MESA_SHADER_VERTEX: diff --git a/src/mesa/main/state.c b/src/mesa/main/state.c index 784dafd07ff..0537021b6ba 100644 --- a/src/mesa/main/state.c +++ b/src/mesa/main/state.c @@ -410,7 +410,7 @@ update_program(struct gl_context *ctx) static GLbitfield update_single_program_constants(struct gl_context *ctx, struct gl_program *prog, - gl_shader_stage stage) + mesa_shader_stage stage) { if (prog) { const struct gl_program_parameter_list *params = prog->Parameters; diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp index 5a24e2484af..c8c31d2b3a0 100644 --- a/src/mesa/main/uniform_query.cpp +++ b/src/mesa/main/uniform_query.cpp @@ -927,7 +927,7 @@ associate_uniform_storage(struct gl_context *ctx, struct gl_program *prog) { struct gl_program_parameter_list *params = prog->Parameters; - gl_shader_stage shader_type = prog->info.stage; + mesa_shader_stage shader_type = prog->info.stage; _mesa_disallow_parameter_storage_realloc(params); diff --git a/src/mesa/main/uniforms.c b/src/mesa/main/uniforms.c index d9f453ce10e..112cdf8605a 100644 --- a/src/mesa/main/uniforms.c +++ b/src/mesa/main/uniforms.c @@ -69,7 +69,7 @@ update_single_shader_texture_used(struct gl_shader_program *shProg, struct gl_program *prog, GLuint unit, GLuint target) { - gl_shader_stage prog_stage = prog->info.stage; + mesa_shader_stage prog_stage = prog->info.stage; assert(unit < ARRAY_SIZE(prog->TexturesUsed)); assert(target < NUM_TEXTURE_TARGETS); @@ -102,7 +102,7 @@ _mesa_update_shader_textures_used(struct gl_shader_program *shProg, struct gl_program *prog) { GLbitfield mask = prog->SamplersUsed; - ASSERTED gl_shader_stage prog_stage = prog->info.stage; + ASSERTED mesa_shader_stage prog_stage = prog->info.stage; GLuint s; assert(shProg->_LinkedShaders[prog_stage]); diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c index 450dd635de0..6b80acf2cff 100644 --- a/src/mesa/program/prog_to_nir.c +++ b/src/mesa/program/prog_to_nir.c @@ -807,7 +807,7 @@ prog_to_nir(const struct gl_context *ctx, const struct gl_program *prog) ctx->screen->nir_options[prog->info.stage]; struct ptn_compile *c; struct nir_shader *s; - gl_shader_stage stage = prog->info.stage; + mesa_shader_stage stage = prog->info.stage; c = rzalloc(NULL, struct ptn_compile); if (!c) diff --git a/src/mesa/program/program.c b/src/mesa/program/program.c index 8e2b250d2b0..c7821b1241d 100644 --- a/src/mesa/program/program.c +++ b/src/mesa/program/program.c @@ -185,7 +185,7 @@ _mesa_set_program_error(struct gl_context *ctx, GLint pos, const char *string) * Initialize a new gl_program object. */ struct gl_program * -_mesa_init_gl_program(struct gl_program *prog, gl_shader_stage stage, +_mesa_init_gl_program(struct gl_program *prog, mesa_shader_stage stage, GLuint id, bool is_arb_asm) { if (!prog) @@ -219,7 +219,7 @@ _mesa_init_gl_program(struct gl_program *prog, gl_shader_stage stage, } struct gl_program * -_mesa_new_program(struct gl_context *ctx, gl_shader_stage stage, GLuint id, +_mesa_new_program(struct gl_context *ctx, mesa_shader_stage stage, GLuint id, bool is_arb_asm) { struct gl_program *prog; diff --git a/src/mesa/program/program.h b/src/mesa/program/program.h index 0593248746c..d52e6d3beb5 100644 --- a/src/mesa/program/program.h +++ b/src/mesa/program/program.h @@ -63,11 +63,11 @@ extern void _mesa_set_program_error(struct gl_context *ctx, GLint pos, const char *string); extern struct gl_program * -_mesa_init_gl_program(struct gl_program *prog, gl_shader_stage stage, +_mesa_init_gl_program(struct gl_program *prog, mesa_shader_stage stage, GLuint id, bool is_arb_asm); extern struct gl_program * -_mesa_new_program(struct gl_context *ctx, gl_shader_stage stage, GLuint id, +_mesa_new_program(struct gl_context *ctx, mesa_shader_stage stage, GLuint id, bool is_arb_asm); extern void diff --git a/src/mesa/state_tracker/st_atom_atomicbuf.c b/src/mesa/state_tracker/st_atom_atomicbuf.c index d80344484b9..97a8b368f26 100644 --- a/src/mesa/state_tracker/st_atom_atomicbuf.c +++ b/src/mesa/state_tracker/st_atom_atomicbuf.c @@ -66,7 +66,7 @@ st_binding_to_sb(struct gl_buffer_binding *binding, static void st_bind_atomics(struct st_context *st, struct gl_program *prog, - gl_shader_stage stage) + mesa_shader_stage stage) { unsigned i; enum pipe_shader_type shader_type = pipe_shader_type_from_mesa(stage); diff --git a/src/mesa/state_tracker/st_atom_constbuf.c b/src/mesa/state_tracker/st_atom_constbuf.c index 880d4c2da9b..65ab497b53b 100644 --- a/src/mesa/state_tracker/st_atom_constbuf.c +++ b/src/mesa/state_tracker/st_atom_constbuf.c @@ -67,7 +67,7 @@ st_unbind_unused_cb0(struct st_context *st, enum pipe_shader_type shader_type) * constant buffer. */ void -st_upload_constants(struct st_context *st, struct gl_program *prog, gl_shader_stage stage) +st_upload_constants(struct st_context *st, struct gl_program *prog, mesa_shader_stage stage) { enum pipe_shader_type shader_type = pipe_shader_type_from_mesa(stage); if (!prog) { diff --git a/src/mesa/state_tracker/st_atom_constbuf.h b/src/mesa/state_tracker/st_atom_constbuf.h index 7fd275c2138..6b338d96d8c 100644 --- a/src/mesa/state_tracker/st_atom_constbuf.h +++ b/src/mesa/state_tracker/st_atom_constbuf.h @@ -35,7 +35,7 @@ struct gl_program_parameter_list; struct st_context; -void st_upload_constants(struct st_context *st, struct gl_program *prog, gl_shader_stage stage); +void st_upload_constants(struct st_context *st, struct gl_program *prog, mesa_shader_stage stage); #endif /* ST_ATOM_CONSTBUF_H */ diff --git a/src/mesa/state_tracker/st_extensions.c b/src/mesa/state_tracker/st_extensions.c index aea602f0560..9888e904ab8 100644 --- a/src/mesa/state_tracker/st_extensions.c +++ b/src/mesa/state_tracker/st_extensions.c @@ -200,7 +200,7 @@ void st_init_limits(struct pipe_screen *screen, c->PointSizeFixed = screen->caps.point_size_fixed != PIPE_POINT_SIZE_LOWER_ALWAYS; for (sh = 0; sh < MESA_SHADER_STAGES; ++sh) { - const gl_shader_stage stage = tgsi_processor_to_shader_stage(sh); + const mesa_shader_stage stage = tgsi_processor_to_shader_stage(sh); struct gl_shader_compiler_options *options = &c->ShaderCompilerOptions[stage]; struct gl_program_constants *pc = &c->Program[stage]; diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp b/src/mesa/state_tracker/st_glsl_to_nir.cpp index c8f81fbfdab..ddfa5786cde 100644 --- a/src/mesa/state_tracker/st_glsl_to_nir.cpp +++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp @@ -466,7 +466,7 @@ st_link_glsl_to_nir(struct gl_context *ctx, for (unsigned i = 0; i < num_shaders; i++) { struct gl_linked_shader *shader = linked_shader[i]; nir_shader *nir = shader->Program->nir; - gl_shader_stage stage = shader->Stage; + mesa_shader_stage stage = shader->Stage; const struct gl_shader_compiler_options *options = &ctx->Const.ShaderCompilerOptions[stage]; diff --git a/src/mesa/state_tracker/st_nir_builtins.c b/src/mesa/state_tracker/st_nir_builtins.c index d2b3549d1d2..60d8930b9fd 100644 --- a/src/mesa/state_tracker/st_nir_builtins.c +++ b/src/mesa/state_tracker/st_nir_builtins.c @@ -31,7 +31,7 @@ void st_nir_finish_builtin_nir(struct st_context *st, nir_shader *nir) { struct pipe_screen *screen = st->screen; - gl_shader_stage stage = nir->info.stage; + mesa_shader_stage stage = nir->info.stage; MESA_TRACE_FUNC(); diff --git a/src/mesa/state_tracker/st_nir_unlower_io_to_vars.c b/src/mesa/state_tracker/st_nir_unlower_io_to_vars.c index 1d548ade787..c769728ff14 100644 --- a/src/mesa/state_tracker/st_nir_unlower_io_to_vars.c +++ b/src/mesa/state_tracker/st_nir_unlower_io_to_vars.c @@ -24,7 +24,7 @@ struct io_desc { #define VAR_INDEX_INTERP_AT_PIXEL 1 #define VAR_INTERP_UNDEF INTERP_MODE_COUNT -static bool var_is_per_vertex(gl_shader_stage stage, nir_variable *var) +static bool var_is_per_vertex(mesa_shader_stage stage, nir_variable *var) { return ((stage == MESA_SHADER_TESS_CTRL || stage == MESA_SHADER_GEOMETRY) && @@ -38,7 +38,7 @@ static bool var_is_per_vertex(gl_shader_stage stage, nir_variable *var) } static const struct glsl_type * -get_var_slot_type(gl_shader_stage stage, nir_variable *var) +get_var_slot_type(mesa_shader_stage stage, nir_variable *var) { if (var_is_per_vertex(stage, var)) { assert(glsl_type_is_array(var->type)); @@ -49,7 +49,7 @@ get_var_slot_type(gl_shader_stage stage, nir_variable *var) } static unsigned -get_var_num_slots(gl_shader_stage stage, nir_variable *var, +get_var_num_slots(mesa_shader_stage stage, nir_variable *var, bool is_driver_location) { const struct glsl_type *type = get_var_slot_type(stage, var); diff --git a/src/mesa/state_tracker/st_program.c b/src/mesa/state_tracker/st_program.c index fae306c7d9d..ffb085309f6 100644 --- a/src/mesa/state_tracker/st_program.c +++ b/src/mesa/state_tracker/st_program.c @@ -464,7 +464,7 @@ st_create_nir_shader(struct st_context *st, struct pipe_shader_state *state) assert(state->type == PIPE_SHADER_IR_NIR); nir_shader *nir = state->ir.nir; - gl_shader_stage stage = nir->info.stage; + mesa_shader_stage stage = nir->info.stage; /* Renumber SSA defs to make it easier to run diff on printed NIR. */ nir_foreach_function_impl(impl, nir) { diff --git a/src/microsoft/compiler/dxil_signature.c b/src/microsoft/compiler/dxil_signature.c index 134ec635c1f..0219e545133 100644 --- a/src/microsoft/compiler/dxil_signature.c +++ b/src/microsoft/compiler/dxil_signature.c @@ -181,10 +181,10 @@ get_additional_semantic_info(nir_shader *s, nir_variable *var, struct semantic_i return next_row; } -typedef void (*semantic_info_proc)(nir_variable *var, struct semantic_info *info, gl_shader_stage stage); +typedef void (*semantic_info_proc)(nir_variable *var, struct semantic_info *info, mesa_shader_stage stage); static void -get_semantic_vs_in_name(nir_variable *var, struct semantic_info *info, gl_shader_stage stage) +get_semantic_vs_in_name(nir_variable *var, struct semantic_info *info, mesa_shader_stage stage) { strcpy(info->name, "TEXCOORD"); info->index = var->data.driver_location; @@ -192,7 +192,7 @@ get_semantic_vs_in_name(nir_variable *var, struct semantic_info *info, gl_shader } static void -get_semantic_sv_name(nir_variable *var, struct semantic_info *info, gl_shader_stage stage) +get_semantic_sv_name(nir_variable *var, struct semantic_info *info, mesa_shader_stage stage) { if (stage != MESA_SHADER_VERTEX) info->interpolation = get_interpolation(var); @@ -327,7 +327,7 @@ get_semantic_name(nir_variable *var, struct semantic_info *info, } static void -get_semantic_in_name(nir_variable *var, struct semantic_info *info, gl_shader_stage stage) +get_semantic_in_name(nir_variable *var, struct semantic_info *info, mesa_shader_stage stage) { const struct glsl_type *type = var->type; if (nir_is_arrayed_io(var, stage) && diff --git a/src/microsoft/compiler/nir_to_dxil.c b/src/microsoft/compiler/nir_to_dxil.c index 525f8819261..8d7e797c543 100644 --- a/src/microsoft/compiler/nir_to_dxil.c +++ b/src/microsoft/compiler/nir_to_dxil.c @@ -6477,7 +6477,7 @@ struct sysvalue_name { gl_system_value value; int slot; char *name; - gl_shader_stage only_in_shader; + mesa_shader_stage only_in_shader; } possible_sysvalues[] = { {SYSTEM_VALUE_VERTEX_ID_ZERO_BASE, -1, "SV_VertexID", MESA_SHADER_NONE}, {SYSTEM_VALUE_INSTANCE_ID, -1, "SV_InstanceID", MESA_SHADER_NONE}, diff --git a/src/microsoft/spirv_to_dxil/spirv2dxil.c b/src/microsoft/spirv_to_dxil/spirv2dxil.c index e5f26fc7390..dca67e5fd4c 100644 --- a/src/microsoft/spirv_to_dxil/spirv2dxil.c +++ b/src/microsoft/spirv_to_dxil/spirv2dxil.c @@ -42,7 +42,7 @@ #define WORD_SIZE 4 -static gl_shader_stage +static mesa_shader_stage stage_to_enum(char *stage) { if (!strcmp(stage, "vertex")) @@ -79,7 +79,7 @@ enum dxil_validator_version val_ver = DXIL_VALIDATOR_1_4; struct nir_shader_compiler_options nir_options; static bool -compile_shader(const char *filename, gl_shader_stage shader_stage, struct shader *shader, +compile_shader(const char *filename, mesa_shader_stage shader_stage, struct shader *shader, struct dxil_spirv_runtime_conf *conf) { size_t file_size; @@ -102,7 +102,7 @@ compile_shader(const char *filename, gl_shader_stage shader_stage, struct shader shader->nir = spirv_to_nir( (const uint32_t *)file_contents, word_count, NULL, - 0, (gl_shader_stage)shader_stage, shader->entry_point, + 0, (mesa_shader_stage)shader_stage, shader->entry_point, spirv_opts, &nir_options); free(file_contents); if (!shader->nir) { @@ -174,7 +174,7 @@ main(int argc, char **argv) .entry_point = "main", .output_file = NULL, }; - gl_shader_stage shader_stage = MESA_SHADER_FRAGMENT; + mesa_shader_stage shader_stage = MESA_SHADER_FRAGMENT; struct dxil_spirv_runtime_conf conf; memset(&conf, 0, sizeof(conf)); diff --git a/src/microsoft/spirv_to_dxil/spirv_to_dxil.c b/src/microsoft/spirv_to_dxil/spirv_to_dxil.c index a5369531a3c..1a8e6e2dee3 100644 --- a/src/microsoft/spirv_to_dxil/spirv_to_dxil.c +++ b/src/microsoft/spirv_to_dxil/spirv_to_dxil.c @@ -32,14 +32,14 @@ #include "git_sha1.h" #include "vulkan/vulkan.h" -static_assert((gl_shader_stage)DXIL_SPIRV_SHADER_NONE == MESA_SHADER_NONE, "must match"); -static_assert((gl_shader_stage)DXIL_SPIRV_SHADER_VERTEX == MESA_SHADER_VERTEX, "must match"); -static_assert((gl_shader_stage)DXIL_SPIRV_SHADER_TESS_CTRL == MESA_SHADER_TESS_CTRL, "must match"); -static_assert((gl_shader_stage)DXIL_SPIRV_SHADER_TESS_EVAL == MESA_SHADER_TESS_EVAL, "must match"); -static_assert((gl_shader_stage)DXIL_SPIRV_SHADER_GEOMETRY == MESA_SHADER_GEOMETRY, "must match"); -static_assert((gl_shader_stage)DXIL_SPIRV_SHADER_FRAGMENT == MESA_SHADER_FRAGMENT, "must match"); -static_assert((gl_shader_stage)DXIL_SPIRV_SHADER_COMPUTE == MESA_SHADER_COMPUTE, "must match"); -static_assert((gl_shader_stage)DXIL_SPIRV_SHADER_KERNEL == MESA_SHADER_KERNEL, "must match"); +static_assert((mesa_shader_stage)DXIL_SPIRV_SHADER_NONE == MESA_SHADER_NONE, "must match"); +static_assert((mesa_shader_stage)DXIL_SPIRV_SHADER_VERTEX == MESA_SHADER_VERTEX, "must match"); +static_assert((mesa_shader_stage)DXIL_SPIRV_SHADER_TESS_CTRL == MESA_SHADER_TESS_CTRL, "must match"); +static_assert((mesa_shader_stage)DXIL_SPIRV_SHADER_TESS_EVAL == MESA_SHADER_TESS_EVAL, "must match"); +static_assert((mesa_shader_stage)DXIL_SPIRV_SHADER_GEOMETRY == MESA_SHADER_GEOMETRY, "must match"); +static_assert((mesa_shader_stage)DXIL_SPIRV_SHADER_FRAGMENT == MESA_SHADER_FRAGMENT, "must match"); +static_assert((mesa_shader_stage)DXIL_SPIRV_SHADER_COMPUTE == MESA_SHADER_COMPUTE, "must match"); +static_assert((mesa_shader_stage)DXIL_SPIRV_SHADER_KERNEL == MESA_SHADER_KERNEL, "must match"); bool spirv_to_dxil(const uint32_t *words, size_t word_count, @@ -73,7 +73,7 @@ spirv_to_dxil(const uint32_t *words, size_t word_count, nir_shader *nir = spirv_to_nir( words, word_count, (struct nir_spirv_specialization *)specializations, - num_specializations, (gl_shader_stage)stage, entry_point_name, + num_specializations, (mesa_shader_stage)stage, entry_point_name, spirv_opts, &nir_options); if (!nir) { glsl_type_singleton_decref(); diff --git a/src/microsoft/spirv_to_dxil/spirv_to_dxil.h b/src/microsoft/spirv_to_dxil/spirv_to_dxil.h index bbeff9fa4b6..00b18849e41 100644 --- a/src/microsoft/spirv_to_dxil/spirv_to_dxil.h +++ b/src/microsoft/spirv_to_dxil/spirv_to_dxil.h @@ -37,7 +37,7 @@ extern "C" { // NB: I've copy and pasted some types into this header so we don't have to // include other headers. This will surely break if any of these types change. -// Copy of gl_shader_stage +// Copy of mesa_shader_stage typedef enum { DXIL_SPIRV_SHADER_NONE = -1, DXIL_SPIRV_SHADER_VERTEX = 0, diff --git a/src/microsoft/vulkan/dzn_pipeline.c b/src/microsoft/vulkan/dzn_pipeline.c index e18fcd77e16..638d3883a67 100644 --- a/src/microsoft/vulkan/dzn_pipeline.c +++ b/src/microsoft/vulkan/dzn_pipeline.c @@ -218,7 +218,7 @@ dzn_pipeline_get_nir_shader(struct dzn_device *device, const uint8_t *hash, VkPipelineCreateFlags2KHR pipeline_flags, const VkPipelineShaderStageCreateInfo *stage_info, - gl_shader_stage stage, + mesa_shader_stage stage, const struct dzn_nir_options *options, struct dxil_spirv_metadata *metadata, nir_shader **nir) @@ -490,7 +490,7 @@ dzn_pipeline_compile_shader(struct dzn_device *device, static D3D12_SHADER_BYTECODE * dzn_pipeline_get_gfx_shader_slot(D3D12_PIPELINE_STATE_STREAM_DESC *stream, - gl_shader_stage in) + mesa_shader_stage in) { switch (in) { case MESA_SHADER_VERTEX: { @@ -518,7 +518,7 @@ dzn_pipeline_get_gfx_shader_slot(D3D12_PIPELINE_STATE_STREAM_DESC *stream, } struct dzn_cached_dxil_shader_header { - gl_shader_stage stage; + mesa_shader_stage stage; size_t size; uint8_t data[0]; }; @@ -526,7 +526,7 @@ struct dzn_cached_dxil_shader_header { static VkResult dzn_pipeline_cache_lookup_dxil_shader(struct vk_pipeline_cache *cache, const uint8_t *dxil_hash, - gl_shader_stage *stage, + mesa_shader_stage *stage, D3D12_SHADER_BYTECODE *bc) { *stage = MESA_SHADER_NONE; @@ -576,7 +576,7 @@ out: static void dzn_pipeline_cache_add_dxil_shader(struct vk_pipeline_cache *cache, const uint8_t *dxil_hash, - gl_shader_stage stage, + mesa_shader_stage stage, const D3D12_SHADER_BYTECODE *bc) { size_t size = sizeof(struct dzn_cached_dxil_shader_header) + @@ -655,7 +655,7 @@ dzn_pipeline_cache_lookup_gfx_pipeline(struct dzn_graphics_pipeline *pipeline, u_foreach_bit(s, info->stages) { uint8_t *dxil_hash = (uint8_t *)cached_blob->data + offset; - gl_shader_stage stage; + mesa_shader_stage stage; D3D12_SHADER_BYTECODE *slot = dzn_pipeline_get_gfx_shader_slot(stream_desc, s); @@ -771,16 +771,16 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device, const uint8_t *dxil_hashes[MESA_VULKAN_SHADER_STAGES] = { 0 }; uint8_t attribs_hash[SHA1_DIGEST_LENGTH]; uint8_t pipeline_hash[SHA1_DIGEST_LENGTH]; - gl_shader_stage last_raster_stage = MESA_SHADER_NONE; + mesa_shader_stage last_raster_stage = MESA_SHADER_NONE; uint32_t active_stage_mask = 0; VkResult ret; - /* First step: collect stage info in a table indexed by gl_shader_stage + /* First step: collect stage info in a table indexed by mesa_shader_stage * so we can iterate over stages in pipeline order or reverse pipeline * order. */ for (uint32_t i = 0; i < info->stageCount; i++) { - gl_shader_stage stage = + mesa_shader_stage stage = vk_to_mesa_shader_stage(info->pStages[i].stage); assert(stage <= MESA_SHADER_FRAGMENT); @@ -982,9 +982,9 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device, */ uint32_t link_mask = active_stage_mask; while (link_mask != 0) { - gl_shader_stage stage = util_last_bit(link_mask) - 1; + mesa_shader_stage stage = util_last_bit(link_mask) - 1; link_mask &= ~BITFIELD_BIT(stage); - gl_shader_stage prev_stage = util_last_bit(link_mask) - 1; + mesa_shader_stage prev_stage = util_last_bit(link_mask) - 1; struct dxil_spirv_runtime_conf conf = { .runtime_data_cbv = { @@ -1023,7 +1023,7 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device, _mesa_sha1_final(&dxil_hash_ctx, stages[stage].dxil_hash); dxil_hashes[stage] = stages[stage].dxil_hash; - gl_shader_stage cached_stage; + mesa_shader_stage cached_stage; D3D12_SHADER_BYTECODE bc; ret = dzn_pipeline_cache_lookup_dxil_shader(cache, stages[stage].dxil_hash, &cached_stage, &bc); if (ret != VK_SUCCESS) @@ -1064,7 +1064,7 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device, /* Last step: translate NIR shaders into DXIL modules */ u_foreach_bit(stage, active_stage_mask) { - gl_shader_stage prev_stage = + mesa_shader_stage prev_stage = util_last_bit(active_stage_mask & BITFIELD_MASK(stage)) - 1; uint32_t prev_stage_output_clip_size = 0; if (stage == MESA_SHADER_FRAGMENT) { @@ -2443,7 +2443,7 @@ dzn_pipeline_cache_lookup_compute_pipeline(struct vk_pipeline_cache *cache, assert(cached_blob->size == SHA1_DIGEST_LENGTH); const uint8_t *dxil_hash = cached_blob->data; - gl_shader_stage stage; + mesa_shader_stage stage; VkResult ret = dzn_pipeline_cache_lookup_dxil_shader(cache, dxil_hash, &stage, dxil); @@ -2549,7 +2549,7 @@ dzn_compute_pipeline_compile_shader(struct dzn_device *device, _mesa_sha1_update(&dxil_hash_ctx, bindings_hash, sizeof(bindings_hash)); _mesa_sha1_final(&dxil_hash_ctx, dxil_hash); - gl_shader_stage stage; + mesa_shader_stage stage; ret = dzn_pipeline_cache_lookup_dxil_shader(cache, dxil_hash, &stage, shader); if (ret != VK_SUCCESS) diff --git a/src/nouveau/compiler/nak.h b/src/nouveau/compiler/nak.h index aa2c8628791..d6ca04096b3 100644 --- a/src/nouveau/compiler/nak.h +++ b/src/nouveau/compiler/nak.h @@ -120,7 +120,7 @@ struct nak_xfb_info { #pragma GCC diagnostic push #pragma GCC diagnostic error "-Wpadded" struct nak_shader_info { - gl_shader_stage stage; + mesa_shader_stage stage; /** Shader model */ uint8_t sm; diff --git a/src/nouveau/vulkan/nvk_cmd_buffer.c b/src/nouveau/vulkan/nvk_cmd_buffer.c index e6bd690aed8..8751a19fb73 100644 --- a/src/nouveau/vulkan/nvk_cmd_buffer.c +++ b/src/nouveau/vulkan/nvk_cmd_buffer.c @@ -665,7 +665,7 @@ nvk_CmdPipelineBarrier2(VkCommandBuffer commandBuffer, void nvk_cmd_bind_shaders(struct vk_command_buffer *vk_cmd, uint32_t stage_count, - const gl_shader_stage *stages, + const mesa_shader_stage *stages, struct vk_shader ** const shaders) { struct nvk_cmd_buffer *cmd = container_of(vk_cmd, struct nvk_cmd_buffer, vk); @@ -700,7 +700,7 @@ nvk_cmd_dirty_cbufs_for_descriptors(struct nvk_cmd_buffer *cmd, uint32_t groups = 0; u_foreach_bit(i, stages & NVK_VK_GRAPHICS_STAGE_BITS) { - gl_shader_stage stage = vk_to_mesa_shader_stage(1 << i); + mesa_shader_stage stage = vk_to_mesa_shader_stage(1 << i); uint32_t g = nvk_cbuf_binding_for_stage(stage); groups |= BITFIELD_BIT(g); } diff --git a/src/nouveau/vulkan/nvk_cmd_buffer.h b/src/nouveau/vulkan/nvk_cmd_buffer.h index 71c06ad0efa..25f9bf48c71 100644 --- a/src/nouveau/vulkan/nvk_cmd_buffer.h +++ b/src/nouveau/vulkan/nvk_cmd_buffer.h @@ -288,11 +288,11 @@ void nvk_cmd_invalidate_compute_state(struct nvk_cmd_buffer *cmd); void nvk_cmd_bind_shaders(struct vk_command_buffer *vk_cmd, uint32_t stage_count, - const gl_shader_stage *stages, + const mesa_shader_stage *stages, struct vk_shader ** const shaders); void nvk_cmd_bind_graphics_shader(struct nvk_cmd_buffer *cmd, - const gl_shader_stage stage, + const mesa_shader_stage stage, struct nvk_shader *shader); void nvk_cmd_bind_compute_shader(struct nvk_cmd_buffer *cmd, diff --git a/src/nouveau/vulkan/nvk_cmd_draw.c b/src/nouveau/vulkan/nvk_cmd_draw.c index c1d12a4e279..e534c3db3a3 100644 --- a/src/nouveau/vulkan/nvk_cmd_draw.c +++ b/src/nouveau/vulkan/nvk_cmd_draw.c @@ -1562,7 +1562,7 @@ nvk_CmdEndRendering(VkCommandBuffer commandBuffer) void nvk_cmd_bind_graphics_shader(struct nvk_cmd_buffer *cmd, - const gl_shader_stage stage, + const mesa_shader_stage stage, struct nvk_shader *shader) { assert(stage < ARRAY_SIZE(cmd->state.gfx.shaders)); @@ -1693,7 +1693,7 @@ nvk_cmd_flush_gfx_shaders(struct nvk_cmd_buffer *cmd) u_foreach_bit(s, cmd->state.gfx.shaders_dirty & NVK_SHADER_STAGE_GRAPHICS_BITS) { - gl_shader_stage stage = vk_to_mesa_shader_stage(1 << s); + mesa_shader_stage stage = vk_to_mesa_shader_stage(1 << s); uint32_t type = mesa_to_nv9097_shader_type(stage); types_dirty |= BITFIELD_BIT(type); @@ -1736,7 +1736,7 @@ nvk_cmd_flush_gfx_shaders(struct nvk_cmd_buffer *cmd) if (cmd->state.gfx.shaders_dirty & NVK_SHADER_STAGE_VTGM_BITS) { struct nvk_shader *last_vtgm = NULL; u_foreach_bit(s, NVK_SHADER_STAGE_VTGM_BITS) { - gl_shader_stage stage = vk_to_mesa_shader_stage(1 << s); + mesa_shader_stage stage = vk_to_mesa_shader_stage(1 << s); if (cmd->state.gfx.shaders[stage] != NULL) last_vtgm = cmd->state.gfx.shaders[stage]; } @@ -3519,7 +3519,7 @@ nvk_cmd_flush_gfx_cbufs(struct nvk_cmd_buffer *cmd) /* Find cbuf maps for the 5 cbuf groups */ const struct nvk_shader *cbuf_shaders[5] = { NULL, }; - for (gl_shader_stage stage = 0; stage < MESA_SHADER_STAGES; stage++) { + for (mesa_shader_stage stage = 0; stage < MESA_SHADER_STAGES; stage++) { const struct nvk_shader *shader = cmd->state.gfx.shaders[stage]; if (shader == NULL) continue; diff --git a/src/nouveau/vulkan/nvk_cmd_indirect.c b/src/nouveau/vulkan/nvk_cmd_indirect.c index 20e5c93dd96..c3b040021ef 100644 --- a/src/nouveau/vulkan/nvk_cmd_indirect.c +++ b/src/nouveau/vulkan/nvk_cmd_indirect.c @@ -444,11 +444,11 @@ build_gfx_set_exec(nir_builder *b, struct nvk_nir_push *p, nir_def *token_addr, case VK_INDIRECT_EXECUTION_SET_INFO_TYPE_SHADER_OBJECTS_EXT: { int32_t i = 0; - gl_shader_stage type_stage[6] = {}; + mesa_shader_stage type_stage[6] = {}; nir_def *type_shader_idx[6] = {}; - gl_shader_stage last_vtgm = MESA_SHADER_VERTEX; + mesa_shader_stage last_vtgm = MESA_SHADER_VERTEX; u_foreach_bit(s, token->shaderStages) { - gl_shader_stage stage = vk_to_mesa_shader_stage(1 << s); + mesa_shader_stage stage = vk_to_mesa_shader_stage(1 << s); if (stage != MESA_SHADER_FRAGMENT) last_vtgm = stage; @@ -1076,7 +1076,7 @@ nvk_CmdExecuteGeneratedCommandsEXT(VkCommandBuffer commandBuffer, uint8_t set_types = 0; u_foreach_bit(s, layout->set_stages) { - gl_shader_stage stage = vk_to_mesa_shader_stage(1 << s); + mesa_shader_stage stage = vk_to_mesa_shader_stage(1 << s); uint32_t type = mesa_to_nv9097_shader_type(stage); set_types |= BITFIELD_BIT(type); } diff --git a/src/nouveau/vulkan/nvk_indirect_execution_set.c b/src/nouveau/vulkan/nvk_indirect_execution_set.c index 1712bdacb43..cf900ee1dd9 100644 --- a/src/nouveau/vulkan/nvk_indirect_execution_set.c +++ b/src/nouveau/vulkan/nvk_indirect_execution_set.c @@ -76,16 +76,16 @@ uint16_t nvk_ies_gfx_pipeline_max_dw_count(const struct nvk_physical_device *pdev, VkShaderStageFlags stages) { - gl_shader_stage last_vtgm = MESA_SHADER_VERTEX; + mesa_shader_stage last_vtgm = MESA_SHADER_VERTEX; u_foreach_bit(s, stages) { - gl_shader_stage stage = vk_to_mesa_shader_stage(1 << s); + mesa_shader_stage stage = vk_to_mesa_shader_stage(1 << s); if (stage != MESA_SHADER_FRAGMENT) last_vtgm = stage; } uint16_t push_dw = 0; u_foreach_bit(s, stages) { - gl_shader_stage stage = vk_to_mesa_shader_stage(1 << s); + mesa_shader_stage stage = vk_to_mesa_shader_stage(1 << s); push_dw += nvk_max_shader_push_dw(pdev, stage, stage == last_vtgm); } @@ -106,10 +106,10 @@ nvk_ies_set_gfx_pipeline(struct nvk_device *dev, uint32_t index, struct vk_pipeline *pipeline) { - gl_shader_stage last_vtgm = MESA_SHADER_VERTEX; + mesa_shader_stage last_vtgm = MESA_SHADER_VERTEX; struct nvk_shader *type_shader[6] = {}; u_foreach_bit(s, pipeline->stages) { - gl_shader_stage stage = vk_to_mesa_shader_stage(1 << s); + mesa_shader_stage stage = vk_to_mesa_shader_stage(1 << s); struct vk_shader *vk_shader = vk_pipeline_get_shader(pipeline, stage); struct nvk_shader *shader = container_of(vk_shader, struct nvk_shader, vk); @@ -152,7 +152,7 @@ nvk_ies_gfx_shader_max_dw_count(const struct nvk_physical_device *pdev, /* Each entry is a single shader so take the max */ uint16_t max_push_dw = 0; u_foreach_bit(s, stages) { - gl_shader_stage stage = vk_to_mesa_shader_stage(1 << s); + mesa_shader_stage stage = vk_to_mesa_shader_stage(1 << s); uint16_t push_dw = nvk_max_shader_push_dw(pdev, stage, last_vtgm); max_push_dw = MAX2(max_push_dw, push_dw); } diff --git a/src/nouveau/vulkan/nvk_shader.c b/src/nouveau/vulkan/nvk_shader.c index 27d7e197beb..c5a926064dd 100644 --- a/src/nouveau/vulkan/nvk_shader.c +++ b/src/nouveau/vulkan/nvk_shader.c @@ -60,7 +60,7 @@ nvk_physical_device_compiler_flags(const struct nvk_physical_device *pdev) static const nir_shader_compiler_options * nvk_get_nir_options(struct vk_physical_device *vk_pdev, - gl_shader_stage stage, + mesa_shader_stage stage, UNUSED const struct vk_pipeline_robustness_state *rs) { const struct nvk_physical_device *pdev = @@ -112,7 +112,7 @@ nvk_ssbo_addr_format(const struct nvk_physical_device *pdev, static struct spirv_to_nir_options nvk_get_spirv_options(struct vk_physical_device *vk_pdev, - UNUSED gl_shader_stage stage, + UNUSED mesa_shader_stage stage, const struct vk_pipeline_robustness_state *rs) { const struct nvk_physical_device *pdev = @@ -603,7 +603,7 @@ nvk_shader_upload(struct nvk_device *dev, struct nvk_shader *shader) } uint32_t -mesa_to_nv9097_shader_type(gl_shader_stage stage) +mesa_to_nv9097_shader_type(mesa_shader_stage stage) { static const uint32_t mesa_to_nv9097[] = { [MESA_SHADER_VERTEX] = NV9097_SET_PIPELINE_SHADER_TYPE_VERTEX, @@ -617,14 +617,14 @@ mesa_to_nv9097_shader_type(gl_shader_stage stage) } uint32_t -nvk_pipeline_bind_group(gl_shader_stage stage) +nvk_pipeline_bind_group(mesa_shader_stage stage) { return stage; } uint16_t nvk_max_shader_push_dw(const struct nvk_physical_device *pdev, - gl_shader_stage stage, bool last_vtgm) + mesa_shader_stage stage, bool last_vtgm) { if (stage == MESA_SHADER_COMPUTE) return 0; diff --git a/src/nouveau/vulkan/nvk_shader.h b/src/nouveau/vulkan/nvk_shader.h index 666635bd89c..5a8d40674be 100644 --- a/src/nouveau/vulkan/nvk_shader.h +++ b/src/nouveau/vulkan/nvk_shader.h @@ -39,7 +39,7 @@ struct vk_shader_module; #define NVK_SHADER_STAGE_GRAPHICS_BITS \ (NVK_SHADER_STAGE_VTGM_BITS | VK_SHADER_STAGE_FRAGMENT_BIT) -static inline gl_shader_stage +static inline mesa_shader_stage nvk_last_vtgm_shader_stage(VkShaderStageFlags stages) { stages &= ~VK_SHADER_STAGE_FRAGMENT_BIT; @@ -48,7 +48,7 @@ nvk_last_vtgm_shader_stage(VkShaderStageFlags stages) } static inline uint32_t -nvk_cbuf_binding_for_stage(gl_shader_stage stage) +nvk_cbuf_binding_for_stage(mesa_shader_stage stage) { return stage; } @@ -81,7 +81,7 @@ struct nvk_cbuf_map { uint16_t nvk_max_shader_push_dw(const struct nvk_physical_device *pdev, - gl_shader_stage stage, bool last_vtgm); + mesa_shader_stage stage, bool last_vtgm); struct nvk_shader { struct vk_shader vk; @@ -148,7 +148,7 @@ nvk_compile_nir_shader(struct nvk_device *dev, nir_shader *nir, const VkAllocationCallbacks *alloc, struct nvk_shader **shader_out); -uint32_t mesa_to_nv9097_shader_type(gl_shader_stage stage); -uint32_t nvk_pipeline_bind_group(gl_shader_stage stage); +uint32_t mesa_to_nv9097_shader_type(mesa_shader_stage stage); +uint32_t nvk_pipeline_bind_group(mesa_shader_stage stage); #endif diff --git a/src/panfrost/compiler/bi_lower_divergent_indirects.c b/src/panfrost/compiler/bi_lower_divergent_indirects.c index a93ed36db25..b265dd59b64 100644 --- a/src/panfrost/compiler/bi_lower_divergent_indirects.c +++ b/src/panfrost/compiler/bi_lower_divergent_indirects.c @@ -41,7 +41,7 @@ static bool bi_lower_divergent_indirects_impl(nir_builder *b, nir_intrinsic_instr *intr, void *data) { - gl_shader_stage stage = b->shader->info.stage; + mesa_shader_stage stage = b->shader->info.stage; nir_src *offset; /* Not all indirect access needs this workaround */ diff --git a/src/panfrost/compiler/bifrost/bi_pack.c b/src/panfrost/compiler/bifrost/bi_pack.c index d42c55e8706..fe81a6b538a 100644 --- a/src/panfrost/compiler/bifrost/bi_pack.c +++ b/src/panfrost/compiler/bifrost/bi_pack.c @@ -319,7 +319,7 @@ bi_get_src_new(bi_instr *ins, bi_registers *regs, unsigned s) static struct bi_packed_tuple bi_pack_tuple(bi_clause *clause, bi_tuple *tuple, bi_tuple *prev, - bool first_tuple, gl_shader_stage stage) + bool first_tuple, mesa_shader_stage stage) { bi_assign_slots(tuple, prev); tuple->regs.fau_idx = tuple->fau_idx; @@ -615,7 +615,7 @@ bi_pack_format(struct util_dynarray *emission, unsigned index, static void bi_pack_clause(bi_context *ctx, bi_clause *clause, bi_clause *next_1, bi_clause *next_2, struct util_dynarray *emission, - gl_shader_stage stage) + mesa_shader_stage stage) { struct bi_packed_tuple ins[8] = {0}; diff --git a/src/panfrost/compiler/bifrost_compile.c b/src/panfrost/compiler/bifrost_compile.c index d0e3d077318..fd465374979 100644 --- a/src/panfrost/compiler/bifrost_compile.c +++ b/src/panfrost/compiler/bifrost_compile.c @@ -2017,7 +2017,7 @@ bi_emit_intrinsic(bi_builder *b, nir_intrinsic_instr *instr) bi_index dst = nir_intrinsic_infos[instr->intrinsic].has_dest ? bi_def_index(&instr->def) : bi_null(); - gl_shader_stage stage = b->shader->stage; + mesa_shader_stage stage = b->shader->stage; switch (instr->intrinsic) { case nir_intrinsic_load_barycentric_pixel: diff --git a/src/panfrost/compiler/compiler.h b/src/panfrost/compiler/compiler.h index 02fe0b4440c..53aaf7a8b3c 100644 --- a/src/panfrost/compiler/compiler.h +++ b/src/panfrost/compiler/compiler.h @@ -948,7 +948,7 @@ typedef struct { const struct pan_compile_inputs *inputs; nir_shader *nir; struct bi_shader_info info; - gl_shader_stage stage; + mesa_shader_stage stage; struct list_head blocks; /* list of bi_block */ uint32_t quirks; unsigned arch; diff --git a/src/panfrost/lib/pan_shader.h b/src/panfrost/lib/pan_shader.h index a4469b258aa..1678c60e86e 100644 --- a/src/panfrost/lib/pan_shader.h +++ b/src/panfrost/lib/pan_shader.h @@ -134,7 +134,7 @@ pan_shader_prepare_midgard_rsd(const struct pan_shader_info *info, #define pan_preloads(reg) (preload & BITFIELD64_BIT(reg)) static void -pan_make_preload(gl_shader_stage stage, uint64_t preload, +pan_make_preload(mesa_shader_stage stage, uint64_t preload, struct MALI_PRELOAD *out) { switch (stage) { diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h index 7d3cf69cfa2..f68162a89be 100644 --- a/src/panfrost/midgard/compiler.h +++ b/src/panfrost/midgard/compiler.h @@ -260,7 +260,7 @@ typedef struct compiler_context { const struct pan_compile_inputs *inputs; nir_shader *nir; struct pan_shader_info *info; - gl_shader_stage stage; + mesa_shader_stage stage; /* Index to precolour to r0 for an input blend colour */ unsigned blend_input; @@ -708,7 +708,7 @@ void midgard_emit_derivatives(compiler_context *ctx, void midgard_lower_derivatives(compiler_context *ctx, midgard_block *block); -bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op); +bool mir_op_computes_derivatives(mesa_shader_stage stage, unsigned op); void mir_analyze_helper_terminate(compiler_context *ctx); void mir_analyze_helper_requirements(compiler_context *ctx); diff --git a/src/panfrost/midgard/midgard_derivatives.c b/src/panfrost/midgard/midgard_derivatives.c index 0a63fe79681..709fa83af72 100644 --- a/src/panfrost/midgard/midgard_derivatives.c +++ b/src/panfrost/midgard/midgard_derivatives.c @@ -73,7 +73,7 @@ mir_derivative_mode(nir_intrinsic_op op) * implicitly */ bool -mir_op_computes_derivatives(gl_shader_stage stage, unsigned op) +mir_op_computes_derivatives(mesa_shader_stage stage, unsigned op) { /* Only fragment shaders may compute derivatives, but the sense of * "normal" changes in vertex shaders on certain GPUs */ diff --git a/src/panfrost/midgard/midgard_helper_invocations.c b/src/panfrost/midgard/midgard_helper_invocations.c index 8c5aaba7ceb..58cd29a42ec 100644 --- a/src/panfrost/midgard/midgard_helper_invocations.c +++ b/src/panfrost/midgard/midgard_helper_invocations.c @@ -64,7 +64,7 @@ /* Does a block use helpers directly */ static bool -mir_block_uses_helpers(gl_shader_stage stage, midgard_block *block) +mir_block_uses_helpers(mesa_shader_stage stage, midgard_block *block) { mir_foreach_instr_in_block(block, ins) { if (ins->type != TAG_TEXTURE_4) diff --git a/src/panfrost/util/pan_ir.h b/src/panfrost/util/pan_ir.h index 6522a129156..38cecdc9df9 100644 --- a/src/panfrost/util/pan_ir.h +++ b/src/panfrost/util/pan_ir.h @@ -194,7 +194,7 @@ struct midgard_shader_info { }; struct pan_shader_info { - gl_shader_stage stage; + mesa_shader_stage stage; unsigned work_reg_count; unsigned tls_size; unsigned wls_size; diff --git a/src/panfrost/vulkan/jm/panvk_cmd_buffer.h b/src/panfrost/vulkan/jm/panvk_cmd_buffer.h index aa4b6c19730..655a7b5a491 100644 --- a/src/panfrost/vulkan/jm/panvk_cmd_buffer.h +++ b/src/panfrost/vulkan/jm/panvk_cmd_buffer.h @@ -149,7 +149,7 @@ void panvk_per_arch(cmd_preload_fb_after_batch_split)( void panvk_per_arch(cmd_bind_shaders)(struct vk_command_buffer *vk_cmd, uint32_t stage_count, - const gl_shader_stage *stages, + const mesa_shader_stage *stages, struct vk_shader **const shaders); #endif diff --git a/src/panfrost/vulkan/jm/panvk_vX_cmd_draw.c b/src/panfrost/vulkan/jm/panvk_vX_cmd_draw.c index 8b573b80b0c..e77a630996f 100644 --- a/src/panfrost/vulkan/jm/panvk_vX_cmd_draw.c +++ b/src/panfrost/vulkan/jm/panvk_vX_cmd_draw.c @@ -411,7 +411,7 @@ panvk_draw_prepare_tiler_context(struct panvk_cmd_buffer *cmdbuf, } static mali_pixel_format -panvk_varying_hw_format(gl_shader_stage stage, gl_varying_slot loc, +panvk_varying_hw_format(mesa_shader_stage stage, gl_varying_slot loc, enum pipe_format pfmt) { switch (loc) { diff --git a/src/panfrost/vulkan/panvk_shader.h b/src/panfrost/vulkan/panvk_shader.h index 02979ce5070..026975525cf 100644 --- a/src/panfrost/vulkan/panvk_shader.h +++ b/src/panfrost/vulkan/panvk_shader.h @@ -380,7 +380,7 @@ struct panvk_shader { }; static inline unsigned -panvk_shader_num_variants(gl_shader_stage stage) +panvk_shader_num_variants(mesa_shader_stage stage) { if (stage == MESA_SHADER_VERTEX) return PANVK_VS_VARIANTS; diff --git a/src/panfrost/vulkan/panvk_vX_shader.c b/src/panfrost/vulkan/panvk_vX_shader.c index 7cf6f8a8c95..79932644ce6 100644 --- a/src/panfrost/vulkan/panvk_vX_shader.c +++ b/src/panfrost/vulkan/panvk_vX_shader.c @@ -364,7 +364,7 @@ panvk_buffer_ssbo_addr_format(VkPipelineRobustnessBufferBehaviorEXT robustness) static const nir_shader_compiler_options * panvk_get_nir_options(UNUSED struct vk_physical_device *vk_pdev, - UNUSED gl_shader_stage stage, + UNUSED mesa_shader_stage stage, UNUSED const struct vk_pipeline_robustness_state *rs) { struct panvk_physical_device *phys_dev = to_panvk_physical_device(vk_pdev); @@ -373,7 +373,7 @@ panvk_get_nir_options(UNUSED struct vk_physical_device *vk_pdev, static struct spirv_to_nir_options panvk_get_spirv_options(UNUSED struct vk_physical_device *vk_pdev, - UNUSED gl_shader_stage stage, + UNUSED mesa_shader_stage stage, const struct vk_pipeline_robustness_state *rs) { return (struct spirv_to_nir_options){ @@ -768,7 +768,7 @@ panvk_lower_nir(struct panvk_device *dev, nir_shader *nir, { struct panvk_instance *instance = to_panvk_instance(dev->vk.physical->instance); - gl_shader_stage stage = nir->info.stage; + mesa_shader_stage stage = nir->info.stage; #if PAN_ARCH >= 10 if (stage == MESA_SHADER_VERTEX && compile_input->view_mask) { @@ -1607,7 +1607,7 @@ panvk_deserialize_shader(struct vk_device *vk_dev, struct blob_reader *blob, struct panvk_device *device = to_panvk_device(vk_dev); struct panvk_shader *shader; - gl_shader_stage stage = blob_read_uint8(blob); + mesa_shader_stage stage = blob_read_uint8(blob); if (blob->overrun) return vk_error(device, VK_ERROR_INCOMPATIBLE_SHADER_BINARY_EXT); @@ -1912,7 +1912,7 @@ panvk_shader_get_executable_internal_representations( #if PAN_ARCH < 9 static mali_pixel_format -get_varying_format(gl_shader_stage stage, gl_varying_slot loc, +get_varying_format(mesa_shader_stage stage, gl_varying_slot loc, enum pipe_format pfmt) { switch (loc) { @@ -2132,7 +2132,7 @@ static const struct vk_shader_ops panvk_shader_ops = { }; static void -panvk_cmd_bind_shader(struct panvk_cmd_buffer *cmd, const gl_shader_stage stage, +panvk_cmd_bind_shader(struct panvk_cmd_buffer *cmd, const mesa_shader_stage stage, struct panvk_shader *shader) { switch (stage) { @@ -2165,7 +2165,7 @@ panvk_cmd_bind_shader(struct panvk_cmd_buffer *cmd, const gl_shader_stage stage, static void panvk_cmd_bind_shaders(struct vk_command_buffer *vk_cmd, uint32_t stage_count, - const gl_shader_stage *stages, + const mesa_shader_stage *stages, struct vk_shader **const shaders) { struct panvk_cmd_buffer *cmd = diff --git a/src/vulkan/runtime/vk_nir.c b/src/vulkan/runtime/vk_nir.c index 93b34a6ceea..1a14aab0d3f 100644 --- a/src/vulkan/runtime/vk_nir.c +++ b/src/vulkan/runtime/vk_nir.c @@ -118,7 +118,7 @@ nir_vk_is_not_xfb_output(nir_variable *var, void *data) nir_shader * vk_spirv_to_nir(struct vk_device *device, const uint32_t *spirv_data, size_t spirv_size_B, - gl_shader_stage stage, const char *entrypoint_name, + mesa_shader_stage stage, const char *entrypoint_name, enum gl_subgroup_size subgroup_size, const VkSpecializationInfo *spec_info, const struct spirv_to_nir_options *spirv_options, diff --git a/src/vulkan/runtime/vk_nir.h b/src/vulkan/runtime/vk_nir.h index 7504c2b2113..943153e8b5b 100644 --- a/src/vulkan/runtime/vk_nir.h +++ b/src/vulkan/runtime/vk_nir.h @@ -43,7 +43,7 @@ nir_vk_is_not_xfb_output(nir_variable *var, void *data); nir_shader * vk_spirv_to_nir(struct vk_device *device, const uint32_t *spirv_data, size_t spirv_size_B, - gl_shader_stage stage, const char *entrypoint_name, + mesa_shader_stage stage, const char *entrypoint_name, enum gl_subgroup_size subgroup_size, const VkSpecializationInfo *spec_info, const struct spirv_to_nir_options *spirv_options, diff --git a/src/vulkan/runtime/vk_pipeline.c b/src/vulkan/runtime/vk_pipeline.c index b4312112f55..b7dbacecb85 100644 --- a/src/vulkan/runtime/vk_pipeline.c +++ b/src/vulkan/runtime/vk_pipeline.c @@ -104,7 +104,7 @@ get_required_subgroup_size(const void *info_pNext) enum gl_subgroup_size vk_get_subgroup_size(uint32_t spirv_version, - gl_shader_stage stage, + mesa_shader_stage stage, const void *info_pNext, bool allow_varying, bool require_full) @@ -136,7 +136,7 @@ vk_pipeline_shader_stage_to_nir(struct vk_device *device, void *mem_ctx, nir_shader **nir_out) { VK_FROM_HANDLE(vk_shader_module, module, info->module); - const gl_shader_stage stage = vk_to_mesa_shader_stage(info->stage); + const mesa_shader_stage stage = vk_to_mesa_shader_stage(info->stage); assert(info->sType == VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO); @@ -650,7 +650,7 @@ struct vk_pipeline_precomp_shader { */ uint8_t cache_key[SHA1_DIGEST_LENGTH]; - gl_shader_stage stage; + mesa_shader_stage stage; struct vk_pipeline_robustness_state rs; @@ -877,7 +877,7 @@ vk_pipeline_precompile_shader(struct vk_device *device, VK_PIPELINE_CREATE_2_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_KHR) return VK_PIPELINE_COMPILE_REQUIRED; - const gl_shader_stage stage = vk_to_mesa_shader_stage(info->stage); + const mesa_shader_stage stage = vk_to_mesa_shader_stage(info->stage); const struct nir_shader_compiler_options *nir_options = ops->get_nir_options(device->physical, stage, &rs); const struct spirv_to_nir_options spirv_options = @@ -913,7 +913,7 @@ vk_pipeline_precompile_shader(struct vk_device *device, } struct vk_pipeline_stage { - gl_shader_stage stage; + mesa_shader_stage stage; struct vk_pipeline_precomp_shader *precomp; struct vk_shader *shader; @@ -1003,7 +1003,7 @@ vk_graphics_pipeline_destroy(struct vk_device *device, static bool vk_device_supports_stage(struct vk_device *device, - gl_shader_stage stage) + mesa_shader_stage stage) { const struct vk_features *features = &device->physical->supported_features; @@ -1026,7 +1026,7 @@ vk_device_supports_stage(struct vk_device *device, } } -static const gl_shader_stage all_gfx_stages[] = { +static const mesa_shader_stage all_gfx_stages[] = { MESA_SHADER_VERTEX, MESA_SHADER_TESS_CTRL, MESA_SHADER_TESS_EVAL, @@ -1057,12 +1057,12 @@ vk_graphics_pipeline_cmd_bind(struct vk_command_buffer *cmd_buffer, } uint32_t stage_count = 0; - gl_shader_stage stages[ARRAY_SIZE(all_gfx_stages)]; + mesa_shader_stage stages[ARRAY_SIZE(all_gfx_stages)]; struct vk_shader *shaders[ARRAY_SIZE(all_gfx_stages)]; VkShaderStageFlags vk_stages = 0; for (uint32_t i = 0; i < ARRAY_SIZE(all_gfx_stages); i++) { - gl_shader_stage stage = all_gfx_stages[i]; + mesa_shader_stage stage = all_gfx_stages[i]; if (!vk_device_supports_stage(device, stage)) { assert(stage_shader[stage] == NULL); continue; @@ -1087,7 +1087,7 @@ vk_graphics_pipeline_cmd_bind(struct vk_command_buffer *cmd_buffer, static VkShaderCreateFlagsEXT vk_pipeline_to_shader_flags(VkPipelineCreateFlags2KHR pipeline_flags, - gl_shader_stage stage) + mesa_shader_stage stage) { VkShaderCreateFlagsEXT shader_flags = 0; @@ -1578,7 +1578,7 @@ vk_graphics_pipeline_get_internal_representations( static struct vk_shader * vk_graphics_pipeline_get_shader(struct vk_pipeline *pipeline, - gl_shader_stage stage) + mesa_shader_stage stage) { struct vk_graphics_pipeline *gfx_pipeline = container_of(pipeline, struct vk_graphics_pipeline, base); @@ -1730,7 +1730,7 @@ vk_create_graphics_pipeline(struct vk_device *device, if (!(state->shader_stages & stage_info->stage)) continue; - gl_shader_stage stage = vk_to_mesa_shader_stage(stage_info->stage); + mesa_shader_stage stage = vk_to_mesa_shader_stage(stage_info->stage); assert(vk_device_supports_stage(device, stage)); stage_feedbacks[stage].flags |= @@ -1857,7 +1857,7 @@ vk_create_graphics_pipeline(struct vk_device *device, */ uint32_t cache_hit_count = 0; for (uint32_t i = 0; i < stage_count; i++) { - const gl_shader_stage stage = stages[i].stage; + const mesa_shader_stage stage = stages[i].stage; if (stage_feedbacks[stage].flags & VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT) cache_hit_count++; @@ -1875,7 +1875,7 @@ vk_create_graphics_pipeline(struct vk_device *device, pCreateInfo->stageCount); for (uint32_t i = 0; i < feedback_info->pipelineStageCreationFeedbackCount; i++) { - const gl_shader_stage stage = + const mesa_shader_stage stage = vk_to_mesa_shader_stage(pCreateInfo->pStages[i].stage); feedback_info->pPipelineStageCreationFeedbacks[i] = @@ -1985,7 +1985,7 @@ vk_compute_pipeline_cmd_bind(struct vk_command_buffer *cmd_buffer, cmd_buffer->pipeline_shader_stages &= ~VK_SHADER_STAGE_COMPUTE_BIT; } - gl_shader_stage stage = MESA_SHADER_COMPUTE; + mesa_shader_stage stage = MESA_SHADER_COMPUTE; ops->cmd_bind_shaders(cmd_buffer, 1, &stage, &shader); } @@ -2154,7 +2154,7 @@ vk_compute_pipeline_get_internal_representations( static struct vk_shader * vk_compute_pipeline_get_shader(struct vk_pipeline *pipeline, - gl_shader_stage stage) + mesa_shader_stage stage) { struct vk_compute_pipeline *comp_pipeline = container_of(pipeline, struct vk_compute_pipeline, base); diff --git a/src/vulkan/runtime/vk_pipeline.h b/src/vulkan/runtime/vk_pipeline.h index 7ba0e51f0fe..8ebaacf5ab0 100644 --- a/src/vulkan/runtime/vk_pipeline.h +++ b/src/vulkan/runtime/vk_pipeline.h @@ -67,7 +67,7 @@ vk_pipeline_shader_stage_to_nir(struct vk_device *device, enum gl_subgroup_size vk_get_subgroup_size(uint32_t spirv_version, - gl_shader_stage stage, + mesa_shader_stage stage, const void *info_pNext, bool allow_varying, bool require_full); @@ -196,7 +196,7 @@ struct vk_pipeline_ops { struct vk_pipeline *pipeline); struct vk_shader *(*get_shader)(struct vk_pipeline *pipeline, - gl_shader_stage stage); + mesa_shader_stage stage); }; void *vk_pipeline_zalloc(struct vk_device *device, @@ -219,7 +219,7 @@ void vk_pipeline_free(struct vk_device *device, static inline struct vk_shader * vk_pipeline_get_shader(struct vk_pipeline *pipeline, - gl_shader_stage stage) + mesa_shader_stage stage) { if (pipeline->ops->get_shader == NULL) return NULL; diff --git a/src/vulkan/runtime/vk_shader.c b/src/vulkan/runtime/vk_shader.c index af0860483e4..2045bb9e013 100644 --- a/src/vulkan/runtime/vk_shader.c +++ b/src/vulkan/runtime/vk_shader.c @@ -41,7 +41,7 @@ static void vk_shader_init(struct vk_shader *shader, struct vk_device *device, const struct vk_shader_ops *ops, - gl_shader_stage stage) + mesa_shader_stage stage) { vk_object_base_init(device, &shader->base, VK_OBJECT_TYPE_SHADER_EXT); shader->ops = ops; @@ -51,7 +51,7 @@ vk_shader_init(struct vk_shader *shader, void * vk_shader_zalloc(struct vk_device *device, const struct vk_shader_ops *ops, - gl_shader_stage stage, + mesa_shader_stage stage, const VkAllocationCallbacks *alloc, size_t size) { @@ -79,7 +79,7 @@ void * vk_shader_multizalloc(struct vk_device *device, struct vk_multialloc *ma, const struct vk_shader_ops *ops, - gl_shader_stage stage, + mesa_shader_stage stage, const VkAllocationCallbacks *alloc) { struct vk_shader *shader = @@ -103,7 +103,7 @@ vk_shader_free(struct vk_device *device, } int -vk_shader_cmp_graphics_stages(gl_shader_stage a, gl_shader_stage b) +vk_shader_cmp_graphics_stages(mesa_shader_stage a, mesa_shader_stage b) { static const int stage_order[MESA_SHADER_MESH + 1] = { [MESA_SHADER_VERTEX] = 1, @@ -122,7 +122,7 @@ vk_shader_cmp_graphics_stages(gl_shader_stage a, gl_shader_stage b) } struct stage_idx { - gl_shader_stage stage; + mesa_shader_stage stage; uint32_t idx; }; @@ -140,7 +140,7 @@ vk_shader_to_nir(struct vk_device *device, { const struct vk_device_shader_ops *ops = device->shader_ops; - const gl_shader_stage stage = vk_to_mesa_shader_stage(info->stage); + const mesa_shader_stage stage = vk_to_mesa_shader_stage(info->stage); const nir_shader_compiler_options *nir_options = ops->get_nir_options(device->physical, stage, rs); struct spirv_to_nir_options spirv_options = @@ -598,7 +598,7 @@ vk_common_CmdBindShadersEXT(VkCommandBuffer commandBuffer, struct vk_device *device = cmd_buffer->base.device; const struct vk_device_shader_ops *ops = device->shader_ops; - STACK_ARRAY(gl_shader_stage, stages, stageCount); + STACK_ARRAY(mesa_shader_stage, stages, stageCount); STACK_ARRAY(struct vk_shader *, shaders, stageCount); VkShaderStageFlags vk_stages = 0; diff --git a/src/vulkan/runtime/vk_shader.h b/src/vulkan/runtime/vk_shader.h index 4cd8e0c2f90..37e01233233 100644 --- a/src/vulkan/runtime/vk_shader.h +++ b/src/vulkan/runtime/vk_shader.h @@ -46,12 +46,12 @@ struct vk_physical_device; struct vk_pipeline; struct vk_pipeline_robustness_state; -int vk_shader_cmp_graphics_stages(gl_shader_stage a, gl_shader_stage b); +int vk_shader_cmp_graphics_stages(mesa_shader_stage a, mesa_shader_stage b); #define VK_SHADER_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_MESA 0x1000 struct vk_shader_compile_info { - gl_shader_stage stage; + mesa_shader_stage stage; VkShaderCreateFlagsEXT flags; VkShaderStageFlags next_stage_mask; struct nir_shader *nir; @@ -72,7 +72,7 @@ struct vk_shader_ops; #pragma GCC diagnostic error "-Wpadded" #endif struct vk_shader_pipeline_cache_key { - gl_shader_stage stage; + mesa_shader_stage stage; blake3_hash blake3; }; #ifdef __GNUC__ @@ -84,7 +84,7 @@ struct vk_shader { const struct vk_shader_ops *ops; - gl_shader_stage stage; + mesa_shader_stage stage; /* Used for the generic VkPipeline implementation */ struct { @@ -150,13 +150,13 @@ struct vk_shader_ops { void *vk_shader_zalloc(struct vk_device *device, const struct vk_shader_ops *ops, - gl_shader_stage stage, + mesa_shader_stage stage, const VkAllocationCallbacks *alloc, size_t size); void *vk_shader_multizalloc(struct vk_device *device, struct vk_multialloc *ma, const struct vk_shader_ops *ops, - gl_shader_stage stage, + mesa_shader_stage stage, const VkAllocationCallbacks *alloc); void vk_shader_free(struct vk_device *device, const VkAllocationCallbacks *alloc, @@ -178,7 +178,7 @@ struct vk_device_shader_ops { */ const struct nir_shader_compiler_options *(*get_nir_options)( struct vk_physical_device *device, - gl_shader_stage stage, + mesa_shader_stage stage, const struct vk_pipeline_robustness_state *rs); /** Retrieves a SPIR-V options struct @@ -188,7 +188,7 @@ struct vk_device_shader_ops { */ struct spirv_to_nir_options (*get_spirv_options)( struct vk_physical_device *device, - gl_shader_stage stage, + mesa_shader_stage stage, const struct vk_pipeline_robustness_state *rs); /** Preprocesses a NIR shader @@ -255,7 +255,7 @@ struct vk_device_shader_ops { */ void (*cmd_bind_shaders)(struct vk_command_buffer *cmd_buffer, uint32_t stage_count, - const gl_shader_stage *stages, + const mesa_shader_stage *stages, struct vk_shader ** const shaders); /** Sets dynamic state */ diff --git a/src/vulkan/util/vk_util.h b/src/vulkan/util/vk_util.h index b3cab1e5c70..b60ceae83b8 100644 --- a/src/vulkan/util/vk_util.h +++ b/src/vulkan/util/vk_util.h @@ -315,15 +315,15 @@ struct vk_pipeline_cache_header { } \ } while (0) -static inline gl_shader_stage +static inline mesa_shader_stage vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage) { assert(util_bitcount((uint32_t) vk_stage) == 1); - return (gl_shader_stage) (ffs((uint32_t) vk_stage) - 1); + return (mesa_shader_stage) (ffs((uint32_t) vk_stage) - 1); } static inline VkShaderStageFlagBits -mesa_to_vk_shader_stage(gl_shader_stage mesa_stage) +mesa_to_vk_shader_stage(mesa_shader_stage mesa_stage) { return (VkShaderStageFlagBits) (1 << ((uint32_t) mesa_stage)); }