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svga: add GL43 resource validation at draw time

Browse source 
This patch adds GL43 tracked states stack and supports GL43 resource
validation at draw time. This patch is squash of in house patches
to support GL43 on VMware driver.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14270>
This commit is contained in:
Neha Bhende 2021-12-16 15:07:58 -08:00 • committed by Marge Bot
parent 1e99a30738
commit 1942c06f9c
48 changed files with 3254 additions and 1494 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

222
src/gallium/drivers/svga/include/VGPU10ShaderTokens.h
View file

@ -1,5 +1,6 @@
/**********************************************************
* Copyright 2007-2015 VMware, Inc. All rights reserved.
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright 2012-2022 VMware, Inc.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@ -21,19 +22,22 @@
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
*/
/*
* VGPU10ShaderTokens.h --
*
* VGPU10 shader token definitions.
*
*/
#ifndef VGPU10SHADERTOKENS_H
#define VGPU10SHADERTOKENS_H
/* Shader limits */
#define VGPU10_MAX_VS_INPUTS 16
#define VGPU10_MAX_VS_OUTPUTS 16
#define VGPU10_MAX_GS_INPUTS 16
@ -49,22 +53,26 @@
#define VGPU10_MIN_TEXEL_FETCH_OFFSET -8
#define VGPU10_MAX_TEXEL_FETCH_OFFSET 7
/* Shader Model 4.1 limits */
#define VGPU10_1_MAX_VS_INPUTS 32
#define VGPU10_1_MAX_VS_OUTPUTS 32
#define VGPU10_1_MAX_GS_INPUTS 32
/* Shader Model 5.0 limits */
#define VGPU11_MAX_HS_INPUTS 32
#define VGPU11_MAX_HS_INPUT_CONTROL_POINTS 32
#define VGPU11_MAX_HS_INPUT_PATCH_CONSTANTS 32
#define VGPU11_MAX_HS_OUTPUT_CP_PHASE_ELEMENTS 32
#define VGPU11_MAX_HS_OUTPUT_CONTROL_POINTS 32
#define VGPU11_MAX_HS_OUTPUTS 32
#define VGPU11_MAX_DS_INPUT_CONTROL_POINTS 32
#define VGPU11_MAX_DS_INPUT_PATCH_CONSTANTS 32
#define VGPU11_MAX_DS_OUTPUTS 32
#define VGPU11_MAX_GS_STREAMS 4
#define VGPU11_MAX_FUNCTION_BODIES 256
#define VGPU11_MAX_FUNCTION_TABLES 256
#define VGPU11_MAX_INTERFACES 253
/* Maximums of limits for all stages */
#define VGPU10_MAX_INPUTS 32
#define VGPU10_MAX_OUTPUTS 32
#define VGPU10_MAX_INPUT_PATCH_CONSTANTS 32
@ -74,7 +82,7 @@ typedef enum {
VGPU10_VERTEX_SHADER = 1,
VGPU10_GEOMETRY_SHADER = 2,
/* DX11 */
VGPU10_HULL_SHADER = 3,
VGPU10_DOMAIN_SHADER = 4,
VGPU10_COMPUTE_SHADER = 5
@ -85,7 +93,7 @@ typedef union {
unsigned int minorVersion : 4;
unsigned int majorVersion : 4;
unsigned int : 8;
unsigned int programType : 16; /* VGPU10_PROGRAM_TYPE */
unsigned int programType : 16;
};
uint32 value;
} VGPU10ProgramToken;
@ -200,16 +208,16 @@ typedef enum {
VGPU10_OPCODE_DCL_INDEXABLE_TEMP = 105,
VGPU10_OPCODE_DCL_GLOBAL_FLAGS = 106,
/* GL guest */
VGPU10_OPCODE_VMWARE = 107,
/* DX10.1 */
VGPU10_OPCODE_LOD = 108,
VGPU10_OPCODE_GATHER4 = 109,
VGPU10_OPCODE_SAMPLE_POS = 110,
VGPU10_OPCODE_SAMPLE_INFO = 111,
/* DX11 */
VGPU10_OPCODE_RESERVED1 = 112,
VGPU10_OPCODE_HS_DECLS = 113,
VGPU10_OPCODE_HS_CONTROL_POINT_PHASE = 114,
@ -308,7 +316,7 @@ typedef enum {
VGPU10_OPCODE_ABORT = 207,
VGPU10_OPCODE_DEBUG_BREAK = 208,
/* DX11.1 */
VGPU10_OPCODE_RESERVED0 = 209,
VGPU10_OPCODE_DDIV = 210,
VGPU10_OPCODE_DFMA = 211,
@ -319,15 +327,15 @@ typedef enum {
VGPU10_OPCODE_ITOD = 216,
VGPU10_OPCODE_UTOD = 217,
VGPU10_NUM_OPCODES /* Should be the last entry. */
VGPU10_NUM_OPCODES
} VGPU10_OPCODE_TYPE;
/* Sub-opcode of VGPU10_OPCODE_VMWARE. */
typedef enum {
VGPU10_VMWARE_OPCODE_IDIV = 0,
VGPU10_VMWARE_OPCODE_DFRC = 1,
VGPU10_VMWARE_OPCODE_DRSQ = 2,
VGPU10_VMWARE_NUM_OPCODES /* Should be the last entry. */
VGPU10_VMWARE_NUM_OPCODES
} VGPU10_VMWARE_OPCODE_TYPE;
typedef enum {
@ -337,22 +345,27 @@ typedef enum {
VGPU10_INTERPOLATION_LINEAR_CENTROID = 3,
VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE = 4,
VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID = 5,
VGPU10_INTERPOLATION_LINEAR_SAMPLE = 6, /* DX10.1 */
VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_SAMPLE = 7 /* DX10.1 */
VGPU10_INTERPOLATION_LINEAR_SAMPLE = 6,
VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_SAMPLE = 7
} VGPU10_INTERPOLATION_MODE;
typedef enum {
VGPU10_RESOURCE_DIMENSION_UNKNOWN = 0,
VGPU10_RESOURCE_DIMENSION_BUFFER = 1,
VGPU10_RESOURCE_DIMENSION_TEXTURE1D = 2,
VGPU10_RESOURCE_DIMENSION_TEXTURE2D = 3,
VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS = 4,
VGPU10_RESOURCE_DIMENSION_TEXTURE3D = 5,
VGPU10_RESOURCE_DIMENSION_TEXTURECUBE = 6,
VGPU10_RESOURCE_DIMENSION_TEXTURE1DARRAY = 7,
VGPU10_RESOURCE_DIMENSION_TEXTURE2DARRAY = 8,
VGPU10_RESOURCE_DIMENSION_TEXTURE2DMSARRAY = 9,
VGPU10_RESOURCE_DIMENSION_TEXTURECUBEARRAY = 10
VGPU10_RESOURCE_DIMENSION_UNKNOWN = 0,
VGPU10_RESOURCE_DIMENSION_BUFFER = 1,
VGPU10_RESOURCE_DIMENSION_TEXTURE1D = 2,
VGPU10_RESOURCE_DIMENSION_TEXTURE2D = 3,
VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS = 4,
VGPU10_RESOURCE_DIMENSION_TEXTURE3D = 5,
VGPU10_RESOURCE_DIMENSION_TEXTURECUBE = 6,
VGPU10_RESOURCE_DIMENSION_TEXTURE1DARRAY = 7,
VGPU10_RESOURCE_DIMENSION_TEXTURE2DARRAY = 8,
VGPU10_RESOURCE_DIMENSION_TEXTURE2DMSARRAY = 9,
VGPU10_RESOURCE_DIMENSION_TEXTURECUBEARRAY = 10,
VGPU10_RESOURCE_DIMENSION_RAW_BUFFER = 11,
VGPU10_RESOURCE_DIMENSION_STRUCTURED_BUFFER = 12,
VGPU10_RESOURCE_DIMENSION_MAX = 12
} VGPU10_RESOURCE_DIMENSION;
typedef enum {
@ -380,7 +393,7 @@ typedef enum {
VGPU10_PRIMITIVE_TRIANGLE_ADJ = 7,
VGPU10_PRIMITIVE_SM40_MAX = 7,
/* DX11 */
VGPU10_PRIMITIVE_1_CONTROL_POINT_PATCH = 8,
VGPU10_PRIMITIVE_2_CONTROL_POINT_PATCH = 9,
VGPU10_PRIMITIVE_3_CONTROL_POINT_PATCH = 10,
@ -448,7 +461,7 @@ typedef enum {
VGPU10_INSTRUCTION_RETURN_UINT = 1
} VGPU10_INSTRUCTION_RETURN_TYPE;
/* DX11 */
typedef enum {
VGPU10_TESSELLATOR_DOMAIN_UNDEFINED = 0,
VGPU10_TESSELLATOR_DOMAIN_ISOLINE = 1,
@ -457,7 +470,7 @@ typedef enum {
VGPU10_TESSELLATOR_DOMAIN_MAX = 3
} VGPU10_TESSELLATOR_DOMAIN;
/* DX11 */
typedef enum {
VGPU10_TESSELLATOR_PARTITIONING_UNDEFINED = 0,
VGPU10_TESSELLATOR_PARTITIONING_INTEGER = 1,
@ -467,7 +480,7 @@ typedef enum {
VGPU10_TESSELLATOR_PARTITIONING_MAX = 4
} VGPU10_TESSELLATOR_PARTITIONING;
/* DX11 */
typedef enum {
VGPU10_TESSELLATOR_OUTPUT_UNDEFINED = 0,
VGPU10_TESSELLATOR_OUTPUT_POINT = 1,
@ -479,65 +492,65 @@ typedef enum {
typedef union {
struct {
unsigned int opcodeType : 11; /* VGPU10_OPCODE_TYPE */
unsigned int interpolationMode : 4; /* VGPU10_INTERPOLATION_MODE */
unsigned int opcodeType : 11;
unsigned int interpolationMode : 4;
unsigned int : 3;
unsigned int testBoolean : 1; /* VGPU10_INSTRUCTION_TEST_BOOLEAN */
unsigned int preciseValues : 4; /* DX11 VGPU10_OPERAND_4_COMPONENT_MASK_* */
unsigned int testBoolean : 1;
unsigned int preciseValues : 4;
unsigned int : 1;
unsigned int instructionLength : 7;
unsigned int extended : 1;
};
/* VGPU10_OPCODE_VMWARE */
struct {
unsigned int : 11;
unsigned int vmwareOpcodeType : 4; /* VGPU10_VMWARE_OPCODE_TYPE */
unsigned int vmwareOpcodeType : 4;
};
struct {
unsigned int : 11;
unsigned int resourceDimension : 5; /* VGPU10_RESOURCE_DIMENSION */
unsigned int resourceDimension : 5;
unsigned int sampleCount : 7;
};
struct {
unsigned int : 11;
unsigned int samplerMode : 4; /* VGPU10_SAMPLER_MODE */
unsigned int samplerMode : 4;
};
struct {
unsigned int : 11;
unsigned int accessPattern : 1; /* VGPU10_CB_ACCESS_PATTERN */
unsigned int accessPattern : 1;
};
struct {
unsigned int : 11;
unsigned int primitive : 6; /* VGPU10_PRIMITIVE */
unsigned int primitive : 6;
};
struct {
unsigned int : 11;
unsigned int primitiveTopology : 6; /* VGPU10_PRIMITIVE_TOPOLOGY */
unsigned int primitiveTopology : 7;
};
struct {
unsigned int : 11;
unsigned int customDataClass : 21; /* VGPU10_CUSTOMDATA_CLASS */
unsigned int customDataClass : 21;
};
struct {
unsigned int : 11;
unsigned int resinfoReturnType : 2; /* VGPU10_RESINFO_RETURN_TYPE */
unsigned int resinfoReturnType : 2;
unsigned int saturate : 1;
};
struct {
unsigned int : 11;
unsigned int refactoringAllowed : 1;
/* DX11 */
unsigned int enableDoublePrecisionFloatOps : 1;
unsigned int forceEarlyDepthStencil : 1;
unsigned int enableRawAndStructuredBuffers : 1;
};
struct {
unsigned int : 11;
unsigned int instReturnType : 2; /* VGPU10_INSTRUCTION_RETURN_TYPE */
unsigned int instReturnType : 2;
};
/* DX11 */
struct {
unsigned int : 11;
unsigned int syncThreadsInGroup : 1;
@ -546,29 +559,28 @@ typedef union {
unsigned int syncUAVMemoryGlobal : 1;
};
struct {
unsigned int : 11; /* VGPU10_OPCODE_DCL_INPUT_CONTROL_POINT_COUNT
* VGPU10_OPCODE_DCL_OUTPUT_CONTROL_POINT_COUNT */
unsigned int : 11;
unsigned int controlPointCount : 6;
};
struct {
unsigned int : 11; /* VGPU10_OPCODE_DCL_TESS_DOMAIN */
unsigned int tessDomain : 2; /* VGPU10_TESSELLATOR_DOMAIN */
unsigned int : 11;
unsigned int tessDomain : 2;
};
struct {
unsigned int : 11; /* VGPU10_OPCODE_DCL_TESS_PARTITIONING */
unsigned int tessPartitioning : 3; /* VGPU10_TESSELLATOR_PARTITIONING */
unsigned int : 11;
unsigned int tessPartitioning : 3;
};
struct {
unsigned int : 11; /* VGPU10_OPCODE_DCL_TESS_OUTPUT_PRIMITIVE */
unsigned int tessOutputPrimitive : 3; /* VGPU10_TESSELLATOR_OUTPUT_PRIMITIVE */
unsigned int : 11;
unsigned int tessOutputPrimitive : 3;
};
struct {
unsigned int : 11; /* VGPU10_OPCODE_DCL_INTERFACE */
unsigned int : 11;
unsigned int interfaceIndexedDynamically : 1;
};
struct {
unsigned int : 11; /* VGPU10_OPCODE_DCL_UAV_* */
unsigned int uavResourceDimension : 5; /* VGPU10_RESOURCE_DIMENSION */
unsigned int : 11;
unsigned int uavResourceDimension : 5;
unsigned int globallyCoherent : 1;
unsigned int : 6;
unsigned int uavHasCounter : 1;
@ -578,20 +590,37 @@ typedef union {
typedef enum {
VGPU10_EXTENDED_OPCODE_EMPTY = 0,
VGPU10_EXTENDED_OPCODE_SAMPLE_CONTROLS
VGPU10_EXTENDED_OPCODE_EMPTY = 0,
VGPU10_EXTENDED_OPCODE_SAMPLE_CONTROLS = 1,
VGPU10_EXTENDED_OPCODE_RESOURCE_DIM = 2,
VGPU10_EXTENDED_OPCODE_RESOURCE_RETURN_TYPE = 3
} VGPU10_EXTENDED_OPCODE_TYPE;
typedef union {
struct {
unsigned int opcodeType : 6; /* VGPU10_EXTENDED_OPCODE_TYPE */
unsigned int opcodeType : 6;
unsigned int : 3;
unsigned int offsetU : 4; /* Two's complement. */
unsigned int offsetV : 4; /* Two's complement. */
unsigned int offsetW : 4; /* Two's complement. */
unsigned int offsetU : 4;
unsigned int offsetV : 4;
unsigned int offsetW : 4;
unsigned int : 10;
unsigned int extended : 1;
};
struct {
unsigned int : 6;
unsigned int resourceDimension : 5;
};
struct {
unsigned int : 6;
unsigned int resourceReturnTypeX : 4;
unsigned int resourceReturnTypeY : 4;
unsigned int resourceReturnTypeZ : 4;
unsigned int resourceReturnTypeW : 4;
};
uint32 value;
} VGPU10OpcodeToken1;
@ -600,7 +629,7 @@ typedef enum {
VGPU10_OPERAND_0_COMPONENT = 0,
VGPU10_OPERAND_1_COMPONENT = 1,
VGPU10_OPERAND_4_COMPONENT = 2,
VGPU10_OPERAND_N_COMPONENT = 3 /* Unused for now. */
VGPU10_OPERAND_N_COMPONENT = 3
} VGPU10_OPERAND_NUM_COMPONENTS;
typedef enum {
@ -653,12 +682,12 @@ typedef enum {
VGPU10_OPERAND_TYPE_NULL = 13,
VGPU10_OPERAND_TYPE_SM40_MAX = 13,
/* DX10.1 */
VGPU10_OPERAND_TYPE_RASTERIZER = 14,
VGPU10_OPERAND_TYPE_OUTPUT_COVERAGE_MASK = 15,
VGPU10_OPERAND_TYPE_SM41_MAX = 15,
/* DX11 */
VGPU10_OPERAND_TYPE_STREAM = 16,
VGPU10_OPERAND_TYPE_FUNCTION_BODY = 17,
VGPU10_OPERAND_TYPE_FUNCTION_TABLE = 18,
@ -706,27 +735,27 @@ typedef enum {
typedef union {
struct {
unsigned int numComponents : 2; /* VGPU10_OPERAND_NUM_COMPONENTS */
unsigned int selectionMode : 2; /* VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE */
unsigned int mask : 4; /* D3D10_SB_OPERAND_4_COMPONENT_MASK_* */
unsigned int numComponents : 2;
unsigned int selectionMode : 2;
unsigned int mask : 4;
unsigned int : 4;
unsigned int operandType : 8; /* VGPU10_OPERAND_TYPE */
unsigned int indexDimension : 2; /* VGPU10_OPERAND_INDEX_DIMENSION */
unsigned int index0Representation : 3; /* VGPU10_OPERAND_INDEX_REPRESENTATION */
unsigned int index1Representation : 3; /* VGPU10_OPERAND_INDEX_REPRESENTATION */
unsigned int operandType : 8;
unsigned int indexDimension : 2;
unsigned int index0Representation : 3;
unsigned int index1Representation : 3;
unsigned int : 3;
unsigned int extended : 1;
};
struct {
unsigned int : 4;
unsigned int swizzleX : 2; /* VGPU10_COMPONENT_NAME */
unsigned int swizzleY : 2; /* VGPU10_COMPONENT_NAME */
unsigned int swizzleZ : 2; /* VGPU10_COMPONENT_NAME */
unsigned int swizzleW : 2; /* VGPU10_COMPONENT_NAME */
unsigned int swizzleX : 2;
unsigned int swizzleY : 2;
unsigned int swizzleZ : 2;
unsigned int swizzleW : 2;
};
struct {
unsigned int : 4;
unsigned int selectMask : 2; /* VGPU10_COMPONENT_NAME */
unsigned int selectMask : 2;
};
uint32 value;
} VGPU10OperandToken0;
@ -746,8 +775,8 @@ typedef enum {
typedef union {
struct {
unsigned int extendedOperandType : 6; /* VGPU10_EXTENDED_OPERAND_TYPE */
unsigned int operandModifier : 8; /* VGPU10_OPERAND_MODIFIER */
unsigned int extendedOperandType : 6;
unsigned int operandModifier : 8;
unsigned int : 17;
unsigned int extended : 1;
};
@ -757,21 +786,29 @@ typedef union {
typedef enum {
VGPU10_RETURN_TYPE_MIN = 1,
VGPU10_RETURN_TYPE_UNORM = 1,
VGPU10_RETURN_TYPE_SNORM = 2,
VGPU10_RETURN_TYPE_SINT = 3,
VGPU10_RETURN_TYPE_UINT = 4,
VGPU10_RETURN_TYPE_FLOAT = 5,
VGPU10_RETURN_TYPE_MIXED = 6,
VGPU10_RETURN_TYPE_MAX = 6
VGPU10_RETURN_TYPE_SM40_MAX = 6,
VGPU10_RETURN_TYPE_DOUBLE = 7,
VGPU10_RETURN_TYPE_CONTINUED = 8,
VGPU10_RETURN_TYPE_UNUSED = 9,
VGPU10_RETURN_TYPE_MAX = 9
} VGPU10_RESOURCE_RETURN_TYPE;
typedef union {
struct {
unsigned int component0 : 4; /* VGPU10_RESOURCE_RETURN_TYPE */
unsigned int component1 : 4; /* VGPU10_RESOURCE_RETURN_TYPE */
unsigned int component2 : 4; /* VGPU10_RESOURCE_RETURN_TYPE */
unsigned int component3 : 4; /* VGPU10_RESOURCE_RETURN_TYPE */
unsigned int component0 : 4;
unsigned int component1 : 4;
unsigned int component2 : 4;
unsigned int component3 : 4;
};
uint32 value;
} VGPU10ResourceReturnTypeToken;
@ -779,6 +816,7 @@ typedef union {
typedef enum {
VGPU10_NAME_MIN = 0,
VGPU10_NAME_UNDEFINED = 0,
VGPU10_NAME_POSITION = 1,
VGPU10_NAME_CLIP_DISTANCE = 2,
@ -792,7 +830,7 @@ typedef enum {
VGPU10_NAME_SAMPLE_INDEX = 10,
VGPU10_NAME_SM40_MAX = 10,
/* DX11 */
VGPU10_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR = 11,
VGPU10_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR = 12,
VGPU10_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR = 13,
@ -811,7 +849,7 @@ typedef enum {
typedef union {
struct {
unsigned int name : 16; /* VGPU10_SYSTEM_NAME */
unsigned int name : 16;
};
uint32 value;
} VGPU10NameToken;

21
src/gallium/drivers/svga/include/svga3d_devcaps.h
View file

@ -1,5 +1,6 @@
/**********************************************************
* Copyright 1998-2017 VMware, Inc. All rights reserved.
/* SPDX-License-Identifier: GPL-3.0 OR MIT */
/*
* Copyright 1998-2022 VMware, Inc.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@ -21,7 +22,7 @@
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
*/
/*
* svga3d_devcaps.h --
@ -424,24 +425,28 @@ typedef enum {
SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM = 241,
SVGA3D_DEVCAP_DXFMT_BC4_UNORM = 242,
SVGA3D_DEVCAP_DXFMT_BC5_UNORM = 243,
SVGA3D_DEVCAP_SM41 = 244,
SVGA3D_DEVCAP_MULTISAMPLE_2X = 245,
SVGA3D_DEVCAP_MULTISAMPLE_4X = 246,
SVGA3D_DEVCAP_MS_FULL_QUALITY = 247,
SVGA3D_DEVCAP_LOGICOPS = 248,
SVGA3D_DEVCAP_LOGIC_BLENDOPS = 249,
SVGA3D_DEVCAP_DXFMT_B4G4R4A4_UNORM = 250,
SVGA3D_DEVCAP_DEAD12 = 250,
SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS = 251,
SVGA3D_DEVCAP_DXFMT_BC6H_UF16 = 252,
SVGA3D_DEVCAP_DXFMT_BC6H_SF16 = 253,
SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS = 254,
SVGA3D_DEVCAP_DXFMT_BC7_UNORM = 255,
SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB = 256,
SVGA3D_DEVCAP_DXFMT_AYUV = 257,
SVGA3D_DEVCAP_DEAD13 = 257,
SVGA3D_DEVCAP_SM5 = 258,
SVGA3D_DEVCAP_MULTISAMPLE_8X = 259,
SVGA3D_DEVCAP_FORCED_SAMPLE_COUNT_1 = 260,
SVGA3D_DEVCAP_MAX = 261,
SVGA3D_DEVCAP_MAX_FORCED_SAMPLE_COUNT = 260,
SVGA3D_DEVCAP_GL43 = 261,
SVGA3D_DEVCAP_MAX = 262,
} SVGA3dDevCapIndex;

1089
src/gallium/drivers/svga/include/svga3d_surfacedefs.h
View file

File diff suppressed because it is too large Load diff

858
src/gallium/drivers/svga/include/svga3d_types.h
View file

File diff suppressed because it is too large Load diff

2
src/gallium/drivers/svga/svga_cmd.h
View file

@ -636,7 +636,7 @@ enum pipe_error
SVGA3D_vgpu10_SetVertexBuffers(struct svga_winsys_context *swc,
unsigned count,
uint32 startBuffer,
const SVGA3dVertexBuffer *bufferInfo,
const SVGA3dVertexBuffer_v2 *bufferInfo,
struct svga_winsys_surface **surfaces);
enum pipe_error

2
src/gallium/drivers/svga/svga_cmd_vgpu10.c
View file

@ -1172,7 +1172,7 @@ enum pipe_error
SVGA3D_vgpu10_SetVertexBuffers(struct svga_winsys_context *swc,
unsigned count,
uint32 startBuffer,
const SVGA3dVertexBuffer *bufferInfo,
const SVGA3dVertexBuffer_v2 *bufferInfo,
struct svga_winsys_surface **surfaces)
{
SVGA3dCmdDXSetVertexBuffers *cmd;

63
src/gallium/drivers/svga/svga_context.c
View file

@ -61,13 +61,6 @@ svga_destroy(struct pipe_context *pipe)
struct svga_context *svga = svga_context(pipe);
unsigned shader, i;
/* free any alternate rasterizer states used for point sprite */
for (i = 0; i < ARRAY_SIZE(svga->rasterizer_no_cull); i++) {
if (svga->rasterizer_no_cull[i]) {
pipe->delete_rasterizer_state(pipe, svga->rasterizer_no_cull[i]);
}
}
/* free depthstencil_disable state */
if (svga->depthstencil_disable) {
pipe->delete_depth_stencil_alpha_state(pipe, svga->depthstencil_disable);
@ -98,6 +91,7 @@ svga_destroy(struct pipe_context *pipe)
svga_cleanup_tss_binding(svga);
svga_cleanup_vertex_state(svga);
svga_cleanup_tcs_state(svga);
svga_cleanup_shader_image_state(svga);
svga_destroy_swtnl(svga);
svga_hwtnl_destroy(svga->hwtnl);
@ -114,6 +108,9 @@ svga_destroy(struct pipe_context *pipe)
util_bitmask_destroy(svga->surface_view_id_bm);
util_bitmask_destroy(svga->stream_output_id_bm);
util_bitmask_destroy(svga->query_id_bm);
util_bitmask_destroy(svga->uav_id_bm);
util_bitmask_destroy(svga->uav_to_free_id_bm);
u_upload_destroy(svga->const0_upload);
u_upload_destroy(svga->pipe.stream_uploader);
u_upload_destroy(svga->pipe.const_uploader);
@ -126,6 +123,15 @@ svga_destroy(struct pipe_context *pipe)
}
}
/* free any pending srvs that were created for rawbuf sr view for
* constant buf.
*/
if (svga_have_gl43(svga)) {
svga_destroy_rawbuf_srv(svga);
util_bitmask_destroy(svga->sampler_view_to_free_id_bm);
pipe_resource_reference(&svga->dummy_resource, NULL);
}
FREE(svga);
}
@ -189,6 +195,9 @@ svga_context_create(struct pipe_screen *screen, void *priv, unsigned flags)
svga_init_stream_output_functions(svga);
svga_init_clear_functions(svga);
svga_init_tracked_state(svga);
svga_init_shader_image_functions(svga);
svga_init_shader_buffer_functions(svga);
svga_init_cs_functions(svga);
/* init misc state */
svga->curr.sample_mask = ~0;
@ -230,6 +239,15 @@ svga_context_create(struct pipe_screen *screen, void *priv, unsigned flags)
if (!(svga->query_id_bm = util_bitmask_create()))
goto cleanup;
if (!(svga->uav_id_bm = util_bitmask_create()))
goto cleanup;
if (!(svga->uav_to_free_id_bm = util_bitmask_create()))
goto cleanup;
if (!(svga->sampler_view_to_free_id_bm = util_bitmask_create()))
goto cleanup;
svga->hwtnl = svga_hwtnl_create(svga);
if (svga->hwtnl == NULL)
goto cleanup;
@ -275,6 +293,11 @@ svga_context_create(struct pipe_screen *screen, void *priv, unsigned flags)
svga->state.hw_draw.num_backed_views = 0;
svga->state.hw_draw.rasterizer_discard = FALSE;
/* Initialize uavs */
svga->state.hw_draw.uavSpliceIndex = -1;
svga->state.hw_draw.num_uavs = 0;
svga->state.hw_draw.num_cs_uavs = 0;
/* Initialize the shader pointers */
svga->state.hw_draw.vs = NULL;
svga->state.hw_draw.gs = NULL;
@ -289,6 +312,10 @@ svga_context_create(struct pipe_screen *screen, void *priv, unsigned flags)
sizeof(svga->state.hw_draw.default_constbuf_size));
memset(svga->state.hw_draw.enabled_constbufs, 0,
sizeof(svga->state.hw_draw.enabled_constbufs));
memset(svga->state.hw_draw.enabled_rawbufs, 0,
sizeof(svga->state.hw_draw.enabled_rawbufs));
memset(svga->state.hw_draw.rawbufs, 0,
sizeof(svga->state.hw_draw.rawbufs));
svga->state.hw_draw.ib = NULL;
svga->state.hw_draw.num_vbuffers = 0;
memset(svga->state.hw_draw.vbuffers, 0,
@ -296,6 +323,17 @@ svga_context_create(struct pipe_screen *screen, void *priv, unsigned flags)
svga->state.hw_draw.const0_buffer = NULL;
svga->state.hw_draw.const0_handle = NULL;
if (svga_have_gl43(svga)) {
for (unsigned shader = 0; shader < PIPE_SHADER_TYPES; ++shader) {
for (unsigned i = 0;
i < ARRAY_SIZE(svga->state.hw_draw.rawbufs[shader]); i++) {
svga->state.hw_draw.rawbufs[shader][i].srvid = SVGA3D_INVALID_ID;
}
}
svga_uav_cache_init(svga);
svga->dummy_resource = NULL;
}
/* Create a no-operation blend state which we will bind whenever the
* requested blend state is impossible (e.g. due to having an integer
* render target attached).
@ -346,11 +384,15 @@ cleanup:
util_bitmask_destroy(svga->input_element_object_id_bm);
util_bitmask_destroy(svga->rast_object_id_bm);
util_bitmask_destroy(svga->sampler_object_id_bm);
util_bitmask_destroy(svga->sampler_view_id_bm);
util_bitmask_destroy(svga->shader_id_bm);
util_bitmask_destroy(svga->surface_view_id_bm);
util_bitmask_destroy(svga->stream_output_id_bm);
util_bitmask_destroy(svga->query_id_bm);
util_bitmask_destroy(svga->uav_id_bm);
util_bitmask_destroy(svga->uav_to_free_id_bm);
util_bitmask_destroy(svga->sampler_view_id_bm);
FREE(svga);
svga = NULL;
@ -424,6 +466,11 @@ svga_context_flush(struct svga_context *svga,
if (svga_need_to_rebind_resources(svga)) {
svga->rebind.flags.query = TRUE;
}
if (svga_sws(svga)->have_index_vertex_buffer_offset_cmd) {
svga->rebind.flags.vertexbufs = TRUE;
svga->rebind.flags.indexbuf = TRUE;
}
}
if (SVGA_DEBUG & DEBUG_SYNC) {

48
src/gallium/drivers/svga/svga_context.h
View file

@ -85,10 +85,12 @@ enum svga_hud {
SVGA_QUERY_MAX
};
/**
* Maximum supported number of constant buffers per shader
* including the zero slot for the default constant buffer.
*/
#define SVGA_MAX_CONST_BUFS 14
#define SVGA_MAX_CONST_BUFS 15
/**
* Maximum constant buffer size that can be set in the
@ -183,6 +185,8 @@ struct svga_depth_stencil_state {
#define SVGA_PIPELINE_FLAG_LINES (1<<PIPE_PRIM_LINES)
#define SVGA_PIPELINE_FLAG_TRIS (1<<PIPE_PRIM_TRIANGLES)
#define SVGA_MAX_FRAMEBUFFER_DEFAULT_SAMPLES 4
struct svga_rasterizer_state {
struct pipe_rasterizer_state templ; /* needed for draw module */
@ -208,6 +212,11 @@ struct svga_rasterizer_state {
SVGA3dRasterizerStateId id; /**< vgpu10 */
/* Alternate SVGA rasterizer state object with forcedSampleCount */
int altRastIds[SVGA_MAX_FRAMEBUFFER_DEFAULT_SAMPLES+1];
struct svga_rasterizer_state *no_cull_rasterizer;
/** For debugging: */
const char* need_pipeline_tris_str;
const char* need_pipeline_lines_str;
@ -277,6 +286,14 @@ struct svga_constant_buffer {
unsigned size;
};
struct svga_raw_buffer {
struct svga_winsys_surface *handle;
unsigned buffer_offset;
unsigned buffer_size;
struct pipe_resource *buffer;
int32 srvid;
};
/* Use to calculate differences between state emitted to hardware and
* current driver-calculated state.
*/
@ -284,10 +301,10 @@ struct svga_state
{
const struct svga_blend_state *blend;
const struct svga_depth_stencil_state *depth;
const struct svga_rasterizer_state *rast;
const struct svga_sampler_state *sampler[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
const struct svga_velems_state *velems;
struct svga_rasterizer_state *rast;
struct pipe_sampler_view *sampler_views[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS]; /* or texture ID's? */
struct svga_fragment_shader *fs;
struct svga_vertex_shader *vs;
@ -305,6 +322,7 @@ struct svga_state
* svga_shader_emitter_v10.num_shader_consts.
*/
struct pipe_constant_buffer constbufs[PIPE_SHADER_TYPES][SVGA_MAX_CONST_BUFS];
struct svga_raw_buffer rawbufs[PIPE_SHADER_TYPES][SVGA_MAX_CONST_BUFS];
struct pipe_framebuffer_state framebuffer;
float depthscale;
@ -428,6 +446,8 @@ struct svga_hw_draw_state
/** Currently bound constant buffer, per shader stage */
struct pipe_resource *constbuf[PIPE_SHADER_TYPES][SVGA_MAX_CONST_BUFS];
struct svga_constant_buffer constbufoffsets[PIPE_SHADER_TYPES][SVGA_MAX_CONST_BUFS];
struct svga_raw_buffer rawbufs[PIPE_SHADER_TYPES][SVGA_MAX_CONST_BUFS];
unsigned enabled_rawbufs[PIPE_SHADER_TYPES];
/** Bitmask of enabled constant buffers */
unsigned enabled_constbufs[PIPE_SHADER_TYPES];
@ -450,7 +470,7 @@ struct svga_hw_draw_state
SVGA3dPrimitiveType topology;
/** Vertex buffer state */
SVGA3dVertexBuffer vbuffer_attrs[PIPE_MAX_ATTRIBS];
SVGA3dVertexBuffer_v2 vbuffer_attrs[PIPE_MAX_ATTRIBS];
struct pipe_resource *vbuffers[PIPE_MAX_ATTRIBS];
unsigned num_vbuffers;
@ -544,12 +564,14 @@ struct svga_uav
SVGA3dUAViewId uaViewId;
unsigned timestamp[2];
};
struct svga_cache_uav
{
unsigned num_uaViews;
unsigned next_uaView;
struct svga_uav uaViews[SVGA3D_DX11_1_MAX_UAVIEWS];
};
struct svga_context
{
struct pipe_context pipe;
@ -599,6 +621,9 @@ struct svga_context
/* Bitmask of sampler view IDs */
struct util_bitmask *sampler_view_id_bm;
/* Bitmask of to-free sampler view IDs created for raw buffer srv */
struct util_bitmask *sampler_view_to_free_id_bm;
/* Bitmask of used shader IDs */
struct util_bitmask *shader_id_bm;
@ -649,7 +674,12 @@ struct svga_context
unsigned tes:1;
unsigned cs:1;
unsigned query:1;
unsigned images:1;
unsigned shaderbufs:1;
unsigned atomicbufs:1;
unsigned uav:1;
unsigned indexbuf:1;
unsigned vertexbufs:1;
} flags;
unsigned val;
} rebind;
@ -734,9 +764,6 @@ struct svga_context
void *sampler;
} polygon_stipple;
/** Alternate rasterizer states created for point sprite */
struct svga_rasterizer_state *rasterizer_no_cull[2];
/** Depth stencil state created to disable depth stencil test */
struct svga_depth_stencil_state *depthstencil_disable;
@ -856,6 +883,7 @@ void svga_init_query_functions( struct svga_context *svga );
void svga_init_surface_functions(struct svga_context *svga);
void svga_init_stream_output_functions( struct svga_context *svga );
void svga_init_clear_functions( struct svga_context *svga );
void svga_init_shader_image_functions( struct svga_context *svga );
void svga_cleanup_vertex_state( struct svga_context *svga );
void svga_cleanup_sampler_state( struct svga_context *svga );
@ -882,6 +910,11 @@ svga_context_create(struct pipe_screen *screen,
void svga_toggle_render_condition(struct svga_context *svga,
boolean render_condition_enabled,
boolean on);
int svga_define_rasterizer_object(struct svga_context *svga,
struct svga_rasterizer_state *,
unsigned samples);
enum pipe_error
svga_validate_sampler_resources(struct svga_context *svga,
enum svga_pipe_type);
@ -904,6 +937,9 @@ svga_destroy_rawbuf_srv(struct svga_context *svga);
void
svga_uav_cache_init(struct svga_context *svga);
void
svga_destroy_rawbuf_srv(struct svga_context *svga);
/***********************************************************************
* Inline conversion functions. These are better-typed than the

320
src/gallium/drivers/svga/svga_draw.c
View file

@ -342,14 +342,30 @@ xlate_index_format(unsigned indexWidth)
}
static enum pipe_error
validate_sampler_resources(struct svga_context *svga)
/**
* A helper function to validate sampler view resources to ensure any
* pending updates to buffers will be emitted before they are referenced
* at draw or dispatch time. It also rebinds the resources if needed.
*/
enum pipe_error
svga_validate_sampler_resources(struct svga_context *svga,
enum svga_pipe_type pipe_type)
{
enum pipe_shader_type shader;
enum pipe_shader_type shader, first_shader, last_shader;
assert(svga_have_vgpu10(svga));
for (shader = PIPE_SHADER_VERTEX; shader <= PIPE_SHADER_COMPUTE; shader++) {
if (pipe_type == SVGA_PIPE_GRAPHICS) {
first_shader = PIPE_SHADER_VERTEX;
last_shader = PIPE_SHADER_TESS_EVAL;
}
else {
assert(svga_have_gl43(svga));
first_shader = PIPE_SHADER_COMPUTE;
last_shader = PIPE_SHADER_COMPUTE;
}
for (shader = first_shader; shader <= last_shader; shader++) {
unsigned count = svga->curr.num_sampler_views[shader];
unsigned i;
struct svga_winsys_surface *surfaces[PIPE_MAX_SAMPLERS];
@ -409,14 +425,31 @@ validate_sampler_resources(struct svga_context *svga)
}
static enum pipe_error
validate_constant_buffers(struct svga_context *svga)
/**
* A helper function to validate constant buffers to ensure any
* pending updates to the buffers will be emitted before they are referenced
* at draw or dispatch time. It also rebinds the resources if needed.
*/
enum pipe_error
svga_validate_constant_buffers(struct svga_context *svga,
enum svga_pipe_type pipe_type)
{
enum pipe_shader_type shader;
enum pipe_shader_type shader, first_shader, last_shader;
assert(svga_have_vgpu10(svga));
for (shader = PIPE_SHADER_VERTEX; shader <= PIPE_SHADER_COMPUTE; shader++) {
if (pipe_type == SVGA_PIPE_GRAPHICS) {
first_shader = PIPE_SHADER_VERTEX;
last_shader = PIPE_SHADER_TESS_EVAL;
}
else {
assert(svga_have_gl43(svga));
first_shader = PIPE_SHADER_COMPUTE;
last_shader = PIPE_SHADER_COMPUTE;
}
for (shader = first_shader; shader <= last_shader; shader++) {
enum pipe_error ret;
struct svga_buffer *buffer;
@ -463,6 +496,28 @@ validate_constant_buffers(struct svga_context *svga)
return ret;
}
}
/* Reference raw constant buffers as they are not included in the
* hw constant buffers list.
*/
unsigned enabled_rawbufs = svga->state.hw_draw.enabled_rawbufs[shader] & ~1u;
while (enabled_rawbufs) {
unsigned i = u_bit_scan(&enabled_rawbufs);
buffer = svga_buffer(svga->curr.constbufs[shader][i].buffer);
assert(buffer != NULL);
handle = svga_buffer_handle(svga, &buffer->b,
PIPE_BIND_SAMPLER_VIEW);
if (svga->rebind.flags.constbufs && handle) {
ret = svga->swc->resource_rebind(svga->swc,
handle,
NULL,
SVGA_RELOC_READ);
if (ret != PIPE_OK)
return ret;
}
}
}
svga->rebind.flags.constbufs = FALSE;
@ -470,6 +525,94 @@ validate_constant_buffers(struct svga_context *svga)
}
/**
* A helper function to validate image view resources to ensure any
* pending updates to buffers will be emitted before they are referenced
* at draw or dispatch time. It also rebinds the resources if needed.
*/
enum pipe_error
svga_validate_image_views(struct svga_context *svga,
enum svga_pipe_type pipe_type)
{
enum pipe_shader_type shader, first_shader, last_shader;
bool rebind = svga->rebind.flags.images;
enum pipe_error ret;
assert(svga_have_gl43(svga));
if (pipe_type == SVGA_PIPE_GRAPHICS) {
first_shader = PIPE_SHADER_VERTEX;
last_shader = PIPE_SHADER_TESS_EVAL;
}
else {
first_shader = PIPE_SHADER_COMPUTE;
last_shader = PIPE_SHADER_COMPUTE;
}
for (shader = first_shader; shader <= last_shader; shader++) {
ret = svga_validate_image_view_resources(svga,
svga->state.hw_draw.num_image_views[shader],
&svga->state.hw_draw.image_views[shader][0], rebind);
if (ret != PIPE_OK)
return ret;
}
svga->rebind.flags.images = FALSE;
return PIPE_OK;
}
/**
* A helper function to validate shader buffer and atomic buffer resources to
* ensure any pending updates to buffers will be emitted before they are
* referenced at draw or dispatch time. It also rebinds the resources if needed.
*/
enum pipe_error
svga_validate_shader_buffers(struct svga_context *svga,
enum svga_pipe_type pipe_type)
{
enum pipe_shader_type shader, first_shader, last_shader;
bool rebind = svga->rebind.flags.shaderbufs;
enum pipe_error ret;
assert(svga_have_gl43(svga));
if (pipe_type == SVGA_PIPE_GRAPHICS) {
first_shader = PIPE_SHADER_VERTEX;
last_shader = PIPE_SHADER_TESS_EVAL;
}
else {
first_shader = PIPE_SHADER_COMPUTE;
last_shader = PIPE_SHADER_COMPUTE;
}
for (shader = first_shader; shader <= last_shader; shader++) {
ret = svga_validate_shader_buffer_resources(svga,
svga->state.hw_draw.num_shader_buffers[shader],
&svga->state.hw_draw.shader_buffers[shader][0], rebind);
if (ret != PIPE_OK)
return ret;
}
svga->rebind.flags.shaderbufs = FALSE;
ret = svga_validate_shader_buffer_resources(svga,
svga->state.hw_draw.num_atomic_buffers,
svga->state.hw_draw.atomic_buffers,
svga->rebind.flags.atomicbufs);
if (ret != PIPE_OK)
return ret;
svga->rebind.flags.atomicbufs = FALSE;
return PIPE_OK;
}
/**
* Was the last command put into the command buffer a drawing command?
* We use this to determine if we can skip emitting buffer re-bind
@ -505,9 +648,9 @@ last_command_was_draw(const struct svga_context *svga)
*/
static boolean
vertex_buffers_equal(unsigned count,
SVGA3dVertexBuffer *pVBufAttr1,
SVGA3dVertexBuffer_v2 *pVBufAttr1,
struct pipe_resource **pVBuf1,
SVGA3dVertexBuffer *pVBufAttr2,
SVGA3dVertexBuffer_v2 *pVBufAttr2,
struct pipe_resource **pVBuf2)
{
return (memcmp(pVBufAttr1, pVBufAttr2,
@ -526,24 +669,58 @@ validate_vertex_buffers(struct svga_hwtnl *hwtnl,
struct svga_context *svga = hwtnl->svga;
struct pipe_resource *vbuffers[SVGA3D_INPUTREG_MAX];
struct svga_winsys_surface *vbuffer_handles[SVGA3D_INPUTREG_MAX];
struct svga_winsys_surface *so_vertex_count_handle;
struct svga_winsys_surface *so_vertex_count_handle = NULL;
const unsigned vbuf_count = so_vertex_count ? 1 : hwtnl->cmd.vbuf_count;
SVGA3dVertexBuffer_v2 vbuffer_attrs[PIPE_MAX_ATTRIBS];
int last_vbuf = -1;
unsigned i;
assert(svga_have_vgpu10(svga));
/* setup vertex attribute input layout */
if (svga->state.hw_draw.layout_id != hwtnl->cmd.vdecl_layout_id) {
enum pipe_error ret =
SVGA3D_vgpu10_SetInputLayout(svga->swc,
hwtnl->cmd.vdecl_layout_id);
if (ret != PIPE_OK)
return ret;
svga->state.hw_draw.layout_id = hwtnl->cmd.vdecl_layout_id;
}
/* Get handle for each referenced vertex buffer, unless we're using a
* stream-out buffer to specify the drawing information (DrawAuto).
* Also set up the buffer attributes.
*/
if (so_vertex_count) {
i = 0;
so_vertex_count_handle = svga_buffer_handle(svga,
so_vertex_count->buffer,
(PIPE_BIND_VERTEX_BUFFER |
PIPE_BIND_STREAM_OUTPUT));
if (!so_vertex_count_handle)
return PIPE_ERROR_OUT_OF_MEMORY;
/* Set IA slot0 input buffer to the SO buffer */
assert(vbuf_count == 1);
vbuffer_attrs[0].stride = hwtnl->cmd.vbufs[0].stride;
vbuffer_attrs[0].offset = hwtnl->cmd.vbufs[0].buffer_offset;
vbuffer_attrs[0].sid = 0;
assert(so_vertex_count->buffer != NULL);
vbuffer_attrs[0].sizeInBytes = svga_buffer(so_vertex_count->buffer)->size;
vbuffers[0] = so_vertex_count->buffer;
vbuffer_handles[0] = so_vertex_count_handle;
i = 1;
}
else {
for (i = 0; i < vbuf_count; i++) {
struct svga_buffer *sbuf =
svga_buffer(hwtnl->cmd.vbufs[i].buffer.resource);
vbuffer_attrs[i].stride = hwtnl->cmd.vbufs[i].stride;
vbuffer_attrs[i].offset = hwtnl->cmd.vbufs[i].buffer_offset;
vbuffer_attrs[i].sid = 0;
if (sbuf) {
vbuffer_handles[i] = svga_buffer_handle(svga, &sbuf->b,
PIPE_BIND_VERTEX_BUFFER);
@ -552,17 +729,25 @@ validate_vertex_buffers(struct svga_hwtnl *hwtnl,
return PIPE_ERROR_OUT_OF_MEMORY;
vbuffers[i] = &sbuf->b;
last_vbuf = i;
vbuffer_attrs[i].sizeInBytes = sbuf->size;
}
else {
vbuffers[i] = NULL;
vbuffer_handles[i] = NULL;
vbuffer_attrs[i].sizeInBytes = 0;
}
}
}
/* Unbind the unreferenced the vertex buffer handles */
for (; i < svga->state.hw_draw.num_vbuffers; i++) {
vbuffers[i] = NULL;
vbuffer_handles[i] = NULL;
vbuffer_attrs[i].sid = 0;
vbuffer_attrs[i].stride = 0;
vbuffer_attrs[i].offset = 0;
vbuffer_attrs[i].sizeInBytes = 0;
}
/* Get handle for each referenced vertex buffer */
@ -616,25 +801,6 @@ validate_vertex_buffers(struct svga_hwtnl *hwtnl,
/* setup vertex buffers */
{
SVGA3dVertexBuffer vbuffer_attrs[PIPE_MAX_ATTRIBS];
if (so_vertex_count) {
/* Set IA slot0 input buffer to the SO buffer */
assert(vbuf_count == 1);
vbuffer_attrs[0].stride = hwtnl->cmd.vbufs[0].stride;
vbuffer_attrs[0].offset = hwtnl->cmd.vbufs[0].buffer_offset;
vbuffer_attrs[0].sid = 0;
vbuffers[0] = so_vertex_count->buffer;
vbuffer_handles[0] = so_vertex_count_handle;
}
else {
for (i = 0; i < vbuf_count; i++) {
vbuffer_attrs[i].stride = hwtnl->cmd.vbufs[i].stride;
vbuffer_attrs[i].offset = hwtnl->cmd.vbufs[i].buffer_offset;
vbuffer_attrs[i].sid = 0;
}
}
/* If any of the vertex buffer state has changed, issue
* the SetVertexBuffers command. Otherwise, we will just
* need to rebind the resources.
@ -654,20 +820,13 @@ validate_vertex_buffers(struct svga_hwtnl *hwtnl,
*/
num_vbuffers = MAX2(vbuf_count, svga->state.hw_draw.num_vbuffers);
/* Zero-out the old buffers we want to unbind (the number of loop
* iterations here is typically very small, and often zero.)
*/
for (i = vbuf_count; i < num_vbuffers; i++) {
vbuffer_attrs[i].sid = 0;
vbuffer_attrs[i].stride = 0;
vbuffer_attrs[i].offset = 0;
vbuffer_handles[i] = NULL;
}
if (num_vbuffers > 0) {
SVGA3dVertexBuffer *pbufAttrs = vbuffer_attrs;
SVGA3dVertexBuffer_v2 *pbufAttrs = vbuffer_attrs;
struct svga_winsys_surface **pbufHandles = vbuffer_handles;
unsigned numVBuf = 0;
boolean emitVBufs =
!svga_sws(svga)->have_index_vertex_buffer_offset_cmd ||
svga->rebind.flags.vertexbufs;
/* Loop through the vertex buffer lists to only emit
* those vertex buffers that are not already in the
@ -681,6 +840,10 @@ validate_vertex_buffers(struct svga_hwtnl *hwtnl,
&svga->state.hw_draw.vbuffer_attrs[i],
&svga->state.hw_draw.vbuffers[i]);
/* Check if we can use the SetVertexBuffersOffsetAndSize command */
emitVBufs = emitVBufs ||
(vbuffers[i] != svga->state.hw_draw.vbuffers[i]);
if (!emit && i == num_vbuffers-1) {
/* Include the last vertex buffer in the next emit
* if it is different.
@ -696,11 +859,23 @@ validate_vertex_buffers(struct svga_hwtnl *hwtnl,
* In this case, there is nothing to send yet.
*/
if (numVBuf) {
enum pipe_error ret =
SVGA3D_vgpu10_SetVertexBuffers(svga->swc,
numVBuf,
i - numVBuf,
pbufAttrs, pbufHandles);
enum pipe_error ret;
/* If all vertex buffers handle are the same as the one
* in the device, just use the
* SetVertexBuffersOffsetAndSize comand.
*/
if (emitVBufs) {
ret = SVGA3D_vgpu10_SetVertexBuffers(svga->swc,
numVBuf,
i - numVBuf,
pbufAttrs, pbufHandles);
} else {
ret = SVGA3D_vgpu10_SetVertexBuffersOffsetAndSize(svga->swc,
numVBuf,
i - numVBuf,
pbufAttrs);
}
if (ret != PIPE_OK)
return ret;
}
@ -740,6 +915,8 @@ validate_vertex_buffers(struct svga_hwtnl *hwtnl,
}
}
svga->rebind.flags.vertexbufs = FALSE;
return PIPE_OK;
}
@ -755,6 +932,7 @@ validate_index_buffer(struct svga_hwtnl *hwtnl,
struct svga_context *svga = hwtnl->svga;
struct svga_winsys_surface *ib_handle =
svga_buffer_handle(svga, ib, PIPE_BIND_INDEX_BUFFER);
enum pipe_error ret;
if (!ib_handle)
return PIPE_ERROR_OUT_OF_MEMORY;
@ -770,12 +948,26 @@ validate_index_buffer(struct svga_hwtnl *hwtnl,
range->indexArray.offset != svga->state.hw_draw.ib_offset) {
assert(indexFormat != SVGA3D_FORMAT_INVALID);
enum pipe_error ret =
SVGA3D_vgpu10_SetIndexBuffer(svga->swc, ib_handle,
indexFormat,
range->indexArray.offset);
if (ret != PIPE_OK)
return ret;
if ((ib == svga->state.hw_draw.ib) &&
svga_sws(hwtnl->svga)->have_index_vertex_buffer_offset_cmd &&
!svga->rebind.flags.indexbuf) {
ret = SVGA3D_vgpu10_SetIndexBufferOffsetAndSize(svga->swc,
indexFormat,
range->indexArray.offset,
sbuf->size);
if (ret != PIPE_OK)
return ret;
}
else {
ret = SVGA3D_vgpu10_SetIndexBuffer(svga->swc, ib_handle,
indexFormat,
range->indexArray.offset);
if (ret != PIPE_OK)
return ret;
}
pipe_resource_reference(&svga->state.hw_draw.ib, ib);
svga->state.hw_draw.ib_format = indexFormat;
@ -795,6 +987,8 @@ validate_index_buffer(struct svga_hwtnl *hwtnl,
}
}
svga->rebind.flags.indexbuf = FALSE;
return PIPE_OK;
}
@ -842,14 +1036,30 @@ draw_vgpu10(struct svga_hwtnl *hwtnl,
*/
}
ret = validate_sampler_resources(svga);
ret = svga_validate_sampler_resources(svga, SVGA_PIPE_GRAPHICS);
if (ret != PIPE_OK)
return ret;
ret = validate_constant_buffers(svga);
ret = svga_validate_constant_buffers(svga, SVGA_PIPE_GRAPHICS);
if (ret != PIPE_OK)
return ret;
if (svga_have_gl43(svga)) {
ret = svga_validate_image_views(svga, SVGA_PIPE_GRAPHICS);
if (ret != PIPE_OK)
return ret;
ret = svga_validate_shader_buffers(svga, SVGA_PIPE_GRAPHICS);
if (ret != PIPE_OK)
return ret;
if (svga->rebind.flags.uav) {
ret= svga_rebind_uav(svga);
if (ret != PIPE_OK)
return ret;
}
}
ret = validate_vertex_buffers(hwtnl, so_vertex_count);
if (ret != PIPE_OK)
return ret;

201
src/gallium/drivers/svga/svga_format.c
View file

@ -61,9 +61,9 @@ static const struct vgpu10_format_entry format_conversion_table[] =
[ PIPE_FORMAT_B8G8R8X8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM, SVGA3D_B8G8R8X8_UNORM, TF_GEN_MIPS },
[ PIPE_FORMAT_B5G5R5A1_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B5G5R5A1_UNORM, SVGA3D_B5G5R5A1_UNORM, TF_GEN_MIPS },
[ PIPE_FORMAT_B5G6R5_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B5G6R5_UNORM, SVGA3D_B5G6R5_UNORM, TF_GEN_MIPS },
[ PIPE_FORMAT_R10G10B10A2_UNORM ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, TF_GEN_MIPS },
[ PIPE_FORMAT_R10G10B10A2_UNORM ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_L8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UNORM, TF_XXX1 },
[ PIPE_FORMAT_A8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_A8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS | TF_000X},
[ PIPE_FORMAT_A8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_A8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS | TF_000X | TF_UAV },
[ PIPE_FORMAT_I8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UNORM, TF_XXXX },
[ PIPE_FORMAT_L8A8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8_UNORM, TF_XXXY },
[ PIPE_FORMAT_L16_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UNORM, TF_XXX1 },
@ -71,10 +71,10 @@ static const struct vgpu10_format_entry format_conversion_table[] =
[ PIPE_FORMAT_Z32_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT, SVGA3D_D32_FLOAT, 0 },
[ PIPE_FORMAT_Z24_UNORM_S8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D24_UNORM_S8_UINT, 0 },
[ PIPE_FORMAT_Z24X8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D24_UNORM_S8_UINT, 0 },
[ PIPE_FORMAT_R32_FLOAT ] = { SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R32G32_FLOAT ] = { SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R32_FLOAT ] = { SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_R32G32_FLOAT ] = { SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_R32G32B32_FLOAT ] = { SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R32G32B32A32_FLOAT ] = { SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R32G32B32A32_FLOAT ] = { SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_R32_USCALED ] = { SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
[ PIPE_FORMAT_R32G32_USCALED ] = { SVGA3D_R32G32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
[ PIPE_FORMAT_R32G32B32_USCALED ] = { SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
@ -83,45 +83,42 @@ static const struct vgpu10_format_entry format_conversion_table[] =
[ PIPE_FORMAT_R32G32_SSCALED ] = { SVGA3D_R32G32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
[ PIPE_FORMAT_R32G32B32_SSCALED ] = { SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
[ PIPE_FORMAT_R32G32B32A32_SSCALED ] = { SVGA3D_R32G32B32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
[ PIPE_FORMAT_R16_UNORM ] = { SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, TF_GEN_MIPS },
[ PIPE_FORMAT_R16G16_UNORM ] = { SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, TF_GEN_MIPS },
[ PIPE_FORMAT_R16_UNORM ] = { SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_R16G16_UNORM ] = { SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_R16G16B16_UNORM ] = { SVGA3D_R16G16B16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
[ PIPE_FORMAT_R16G16B16A16_UNORM ] = { SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, TF_GEN_MIPS },
[ PIPE_FORMAT_R16G16B16A16_UNORM ] = { SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_R16_USCALED ] = { SVGA3D_R16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
[ PIPE_FORMAT_R16G16_USCALED ] = { SVGA3D_R16G16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
[ PIPE_FORMAT_R16G16B16_USCALED ] = { SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
[ PIPE_FORMAT_R16G16B16A16_USCALED ] = { SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
[ PIPE_FORMAT_R16_SNORM ] = { SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, 0 },
[ PIPE_FORMAT_R16G16_SNORM ] = { SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, 0 },
[ PIPE_FORMAT_R16_SNORM ] = { SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, TF_UAV },
[ PIPE_FORMAT_R16G16_SNORM ] = { SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, TF_UAV },
[ PIPE_FORMAT_R16G16B16_SNORM ] = { SVGA3D_R16G16B16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
[ PIPE_FORMAT_R16G16B16A16_SNORM ] = { SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, 0 },
[ PIPE_FORMAT_R16G16B16A16_SNORM ] = { SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, TF_UAV },
[ PIPE_FORMAT_R16_SSCALED ] = { SVGA3D_R16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
[ PIPE_FORMAT_R16G16_SSCALED ] = { SVGA3D_R16G16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
[ PIPE_FORMAT_R16G16B16_SSCALED ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
[ PIPE_FORMAT_R16G16B16A16_SSCALED ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
[ PIPE_FORMAT_R8_UNORM ] = { SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS },
[ PIPE_FORMAT_R8G8_UNORM ] = { SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, TF_GEN_MIPS },
[ PIPE_FORMAT_R8_UNORM ] = { SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_R8G8_UNORM ] = { SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_R8G8B8_UNORM ] = { SVGA3D_R8G8B8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
[ PIPE_FORMAT_R8G8B8A8_UNORM ] = { SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, TF_GEN_MIPS },
[ PIPE_FORMAT_R8G8B8A8_UNORM ] = { SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_R8_USCALED ] = { SVGA3D_R8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
[ PIPE_FORMAT_R8G8_USCALED ] = { SVGA3D_R8G8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
[ PIPE_FORMAT_R8G8B8_USCALED ] = { SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
[ PIPE_FORMAT_R8G8B8A8_USCALED ] = { SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
[ PIPE_FORMAT_R8_SNORM ] = { SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, 0 },
[ PIPE_FORMAT_R8G8_SNORM ] = { SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, 0 },
[ PIPE_FORMAT_R8_SNORM ] = { SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, TF_UAV },
[ PIPE_FORMAT_R8G8_SNORM ] = { SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, TF_UAV },
[ PIPE_FORMAT_R8G8B8_SNORM ] = { SVGA3D_R8G8B8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
[ PIPE_FORMAT_R8G8B8A8_SNORM ] = { SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, 0 },
[ PIPE_FORMAT_R8G8B8A8_SNORM ] = { SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, TF_UAV },
[ PIPE_FORMAT_R8_SSCALED ] = { SVGA3D_R8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
[ PIPE_FORMAT_R8G8_SSCALED ] = { SVGA3D_R8G8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
[ PIPE_FORMAT_R8G8B8_SSCALED ] = { SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
[ PIPE_FORMAT_R8G8B8A8_SSCALED ] = { SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
[ PIPE_FORMAT_R16_FLOAT ] = { SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R16G16_FLOAT ] = { SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R16_FLOAT ] = { SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_R16G16_FLOAT ] = { SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_R16G16B16_FLOAT ] = { SVGA3D_R16G16B16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
[ PIPE_FORMAT_R16G16B16A16_FLOAT ] = { SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R16G16B16A16_FLOAT ] = { SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_B8G8R8A8_SRGB ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
[ PIPE_FORMAT_B8G8R8X8_SRGB ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
[ PIPE_FORMAT_R8G8B8A8_SRGB ] = { SVGA3D_FORMAT_INVALID, SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
@ -138,7 +135,7 @@ static const struct vgpu10_format_entry format_conversion_table[] =
[ PIPE_FORMAT_RGTC2_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC5_UNORM, SVGA3D_FORMAT_INVALID, 0 },
[ PIPE_FORMAT_RGTC2_SNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC5_SNORM, SVGA3D_FORMAT_INVALID, 0 },
[ PIPE_FORMAT_R10G10B10A2_USCALED ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_USCALED },
[ PIPE_FORMAT_R11G11B10_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_R11G11B10_FLOAT, SVGA3D_R11G11B10_FLOAT, TF_GEN_MIPS },
[ PIPE_FORMAT_R11G11B10_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_R11G11B10_FLOAT, SVGA3D_R11G11B10_FLOAT, TF_GEN_MIPS | TF_UAV },
[ PIPE_FORMAT_R9G9B9E5_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3D_FORMAT_INVALID, 0 },
[ PIPE_FORMAT_Z32_FLOAT_S8X24_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, 0 },
[ PIPE_FORMAT_B10G10R10A2_UNORM ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA },
@ -158,30 +155,30 @@ static const struct vgpu10_format_entry format_conversion_table[] =
[ PIPE_FORMAT_B10G10R10A2_USCALED ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_USCALED },
[ PIPE_FORMAT_B10G10R10A2_SSCALED ] = { SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SSCALED },
[ PIPE_FORMAT_B10G10R10A2_SNORM ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SNORM },
[ PIPE_FORMAT_R8_UINT ] = { SVGA3D_R8_UINT, SVGA3D_R8_UINT, SVGA3D_R8_UINT, 0 },
[ PIPE_FORMAT_R8G8_UINT ] = { SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, 0 },
[ PIPE_FORMAT_R8_UINT ] = { SVGA3D_R8_UINT, SVGA3D_R8_UINT, SVGA3D_R8_UINT, TF_UAV },
[ PIPE_FORMAT_R8G8_UINT ] = { SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, TF_UAV },
[ PIPE_FORMAT_R8G8B8_UINT ] = { SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
[ PIPE_FORMAT_R8G8B8A8_UINT ] = { SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, 0 },
[ PIPE_FORMAT_R8_SINT ] = { SVGA3D_R8_SINT, SVGA3D_R8_SINT, SVGA3D_R8_SINT, 0 },
[ PIPE_FORMAT_R8G8_SINT ] = { SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, 0 },
[ PIPE_FORMAT_R8G8B8A8_UINT ] = { SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, TF_UAV },
[ PIPE_FORMAT_R8_SINT ] = { SVGA3D_R8_SINT, SVGA3D_R8_SINT, SVGA3D_R8_SINT, TF_UAV },
[ PIPE_FORMAT_R8G8_SINT ] = { SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, TF_UAV },
[ PIPE_FORMAT_R8G8B8_SINT ] = { SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
[ PIPE_FORMAT_R8G8B8A8_SINT ] = { SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, 0 },
[ PIPE_FORMAT_R16_UINT ] = { SVGA3D_R16_UINT, SVGA3D_R16_UINT, SVGA3D_R16_UINT, 0 },
[ PIPE_FORMAT_R16G16_UINT ] = { SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, 0 },
[ PIPE_FORMAT_R8G8B8A8_SINT ] = { SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, TF_UAV },
[ PIPE_FORMAT_R16_UINT ] = { SVGA3D_R16_UINT, SVGA3D_R16_UINT, SVGA3D_R16_UINT, TF_UAV },
[ PIPE_FORMAT_R16G16_UINT ] = { SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, TF_UAV },
[ PIPE_FORMAT_R16G16B16_UINT ] = { SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
[ PIPE_FORMAT_R16G16B16A16_UINT ] = { SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, 0 },
[ PIPE_FORMAT_R16_SINT ] = { SVGA3D_R16_SINT, SVGA3D_R16_SINT, SVGA3D_R16_SINT, 0 },
[ PIPE_FORMAT_R16G16_SINT ] = { SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, 0 },
[ PIPE_FORMAT_R16G16B16A16_UINT ] = { SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, TF_UAV },
[ PIPE_FORMAT_R16_SINT ] = { SVGA3D_R16_SINT, SVGA3D_R16_SINT, SVGA3D_R16_SINT, TF_UAV },
[ PIPE_FORMAT_R16G16_SINT ] = { SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, TF_UAV },
[ PIPE_FORMAT_R16G16B16_SINT ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
[ PIPE_FORMAT_R16G16B16A16_SINT ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, 0 },
[ PIPE_FORMAT_R32_UINT ] = { SVGA3D_R32_UINT, SVGA3D_R32_UINT, SVGA3D_R32_UINT, 0 },
[ PIPE_FORMAT_R32G32_UINT ] = { SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, 0 },
[ PIPE_FORMAT_R16G16B16A16_SINT ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, TF_UAV },
[ PIPE_FORMAT_R32_UINT ] = { SVGA3D_R32_UINT, SVGA3D_R32_UINT, SVGA3D_R32_UINT, TF_UAV },
[ PIPE_FORMAT_R32G32_UINT ] = { SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, TF_UAV },
[ PIPE_FORMAT_R32G32B32_UINT ] = { SVGA3D_R32G32B32_UINT, SVGA3D_R32G32B32_UINT, SVGA3D_R32G32B32_UINT, 0 },
[ PIPE_FORMAT_R32G32B32A32_UINT ] = { SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, 0 },
[ PIPE_FORMAT_R32_SINT ] = { SVGA3D_R32_SINT, SVGA3D_R32_SINT, SVGA3D_R32_SINT, 0 },
[ PIPE_FORMAT_R32G32_SINT ] = { SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, 0 },
[ PIPE_FORMAT_R32G32B32A32_UINT ] = { SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, TF_UAV },
[ PIPE_FORMAT_R32_SINT ] = { SVGA3D_R32_SINT, SVGA3D_R32_SINT, SVGA3D_R32_SINT, TF_UAV },
[ PIPE_FORMAT_R32G32_SINT ] = { SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, TF_UAV },
[ PIPE_FORMAT_R32G32B32_SINT ] = { SVGA3D_R32G32B32_SINT, SVGA3D_R32G32B32_SINT, SVGA3D_R32G32B32_SINT, 0 },
[ PIPE_FORMAT_R32G32B32A32_SINT ] = { SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, 0 },
[ PIPE_FORMAT_R32G32B32A32_SINT ] = { SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, TF_UAV },
[ PIPE_FORMAT_A8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_000X },
[ PIPE_FORMAT_I8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_XXXX },
[ PIPE_FORMAT_L8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_XXX1 },
@ -206,7 +203,13 @@ static const struct vgpu10_format_entry format_conversion_table[] =
[ PIPE_FORMAT_I32_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_XXXX },
[ PIPE_FORMAT_L32_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_XXX1 },
[ PIPE_FORMAT_L32A32_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32G32_SINT, TF_XXXY },
[ PIPE_FORMAT_R10G10B10A2_UINT ] = { SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, 0 },
[ PIPE_FORMAT_R10G10B10A2_UINT ] = { SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, TF_UAV },
[ PIPE_FORMAT_BPTC_RGBA_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC7_UNORM, SVGA3D_FORMAT_INVALID, TF_SM5 },
[ PIPE_FORMAT_BPTC_SRGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC7_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_SM5 },
[ PIPE_FORMAT_BPTC_RGB_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC6H_SF16, SVGA3D_FORMAT_INVALID, TF_SM5 },
[ PIPE_FORMAT_BPTC_RGB_UFLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC6H_UF16, SVGA3D_FORMAT_INVALID, TF_SM5 },
[ PIPE_FORMAT_X24S8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_X24_G8_UINT, SVGA3D_FORMAT_INVALID, 0 },
[ PIPE_FORMAT_X32_S8X24_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_X32_G8X24_UINT, SVGA3D_FORMAT_INVALID, 0 },
/* Must specify following entry to give the sense of size of format_conversion_table[] */
[ PIPE_FORMAT_COUNT ] = {SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
};
@ -298,8 +301,18 @@ svga_translate_format(const struct svga_screen *ss,
else if (bind & PIPE_BIND_SCANOUT) {
return svga_translate_screen_target_format_vgpu10(format);
}
else if (bind & PIPE_BIND_SHADER_IMAGE) {
if (format_conversion_table[format].flags & TF_UAV)
return format_conversion_table[format].pixel_format;
else
return SVGA3D_FORMAT_INVALID;
}
else {
return entry->pixel_format;
if ((format_conversion_table[format].flags & TF_SM5) &&
!ss->sws->have_sm5)
return SVGA3D_FORMAT_INVALID;
else
return entry->pixel_format;
}
}
@ -784,10 +797,8 @@ static const struct format_cap format_cap_table[] = {
0, 0, 0, 0
},
{
"SVGA3D_AYUV",
SVGA3D_AYUV,
SVGA3D_DEVCAP_SURFACEFMT_AYUV,
0, 0, 0, 0
"SVGA3D_FORMAT_DEAD2",
SVGA3D_FORMAT_DEAD2, 0, 0, 0, 0, 0
},
{
"SVGA3D_R32G32B32A32_TYPELESS",
@ -1369,6 +1380,59 @@ static const struct format_cap format_cap_table[] = {
SVGA3D_BC5_UNORM,
SVGA3D_DEVCAP_DXFMT_BC5_UNORM,
4, 4, 16, 0
},
{
"SVGA3D_B4G4R4A4_UNORM",
SVGA3D_B4G4R4A4_UNORM,
0, 0, 0, 0
},
{
"SVGA3D_BC6H_TYPELESS",
SVGA3D_BC6H_TYPELESS,
SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS,
4, 4, 16, 0
},
{
"SVGA3D_BC6H_UF16",
SVGA3D_BC6H_UF16,
SVGA3D_DEVCAP_DXFMT_BC6H_UF16,
4, 4, 16, 0
},
{
"SVGA3D_BC6H_SF16",
SVGA3D_BC6H_SF16,
SVGA3D_DEVCAP_DXFMT_BC6H_SF16,
4, 4, 16, 0
},
{
"SVGA3D_BC7_TYPELESS",
SVGA3D_BC7_TYPELESS,
SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS,
4, 4, 16, 0
},
{
"SVGA3D_BC7_UNORM",
SVGA3D_BC7_UNORM,
SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS,
4, 4, 16, 0
},
{
"SVGA3D_BC7_UNORM_SRGB",
SVGA3D_BC7_UNORM_SRGB,
SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS,
4, 4, 16, 0
},
{
"SVGA3D_AYUV",
SVGA3D_AYUV,
0,
1, 1, 4, 0
},
{
"SVGA3D_R11G11B10_TYPELESS",
SVGA3D_R11G11B10_TYPELESS,
SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT,
1, 1, 4, 0
}
};
@ -1470,7 +1534,6 @@ svga_devcap_name(SVGA3dDevCapIndex cap)
DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_UYVY),
DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_YUY2),
DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_NV12),
DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_AYUV),
DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS),
DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT),
DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT),
@ -1662,7 +1725,7 @@ svga_get_dx_format_cap(struct svga_screen *ss,
if (entry->devcap) {
sws->get_cap(sws, entry->devcap, caps);
/* pre-SM41 capabable svga device supports SHADER_SAMPLE capability for
/* pre-SM41 capable svga device supports SHADER_SAMPLE capability for
* these formats but does not advertise the devcap.
* So enable this bit here.
*/
@ -1672,6 +1735,9 @@ svga_get_dx_format_cap(struct svga_screen *ss,
caps->u |= SVGA3D_DXFMT_SHADER_SAMPLE;
}
}
else {
caps->u = entry->defaultOperations;
}
if (0) {
debug_printf("Format %s, devcap %s = 0x%x (%s)\n",
@ -1853,20 +1919,24 @@ svga_typeless_format(SVGA3dSurfaceFormat format)
case SVGA3D_R32G32B32A32_UINT:
case SVGA3D_R32G32B32A32_SINT:
case SVGA3D_R32G32B32A32_FLOAT:
case SVGA3D_R32G32B32A32_TYPELESS:
return SVGA3D_R32G32B32A32_TYPELESS;
case SVGA3D_R32G32B32_FLOAT:
case SVGA3D_R32G32B32_UINT:
case SVGA3D_R32G32B32_SINT:
case SVGA3D_R32G32B32_TYPELESS:
return SVGA3D_R32G32B32_TYPELESS;
case SVGA3D_R16G16B16A16_UINT:
case SVGA3D_R16G16B16A16_UNORM:
case SVGA3D_R16G16B16A16_SNORM:
case SVGA3D_R16G16B16A16_SINT:
case SVGA3D_R16G16B16A16_FLOAT:
case SVGA3D_R16G16B16A16_TYPELESS:
return SVGA3D_R16G16B16A16_TYPELESS;
case SVGA3D_R32G32_UINT:
case SVGA3D_R32G32_SINT:
case SVGA3D_R32G32_FLOAT:
case SVGA3D_R32G32_TYPELESS:
return SVGA3D_R32G32_TYPELESS;
case SVGA3D_D32_FLOAT_S8X24_UINT:
case SVGA3D_X32_G8X24_UINT:
@ -1874,6 +1944,7 @@ svga_typeless_format(SVGA3dSurfaceFormat format)
return SVGA3D_R32G8X24_TYPELESS;
case SVGA3D_R10G10B10A2_UINT:
case SVGA3D_R10G10B10A2_UNORM:
case SVGA3D_R10G10B10A2_TYPELESS:
return SVGA3D_R10G10B10A2_TYPELESS;
case SVGA3D_R8G8B8A8_UNORM:
case SVGA3D_R8G8B8A8_SNORM:
@ -1887,6 +1958,7 @@ svga_typeless_format(SVGA3dSurfaceFormat format)
case SVGA3D_R16G16_UNORM:
case SVGA3D_R16G16_SNORM:
case SVGA3D_R16G16_FLOAT:
case SVGA3D_R16G16_TYPELESS:
return SVGA3D_R16G16_TYPELESS;
case SVGA3D_D32_FLOAT:
case SVGA3D_R32_FLOAT:
@ -1903,6 +1975,7 @@ svga_typeless_format(SVGA3dSurfaceFormat format)
case SVGA3D_R8G8_SNORM:
case SVGA3D_R8G8_UINT:
case SVGA3D_R8G8_SINT:
case SVGA3D_R8G8_TYPELESS:
return SVGA3D_R8G8_TYPELESS;
case SVGA3D_D16_UNORM:
case SVGA3D_R16_UNORM:
@ -1916,6 +1989,7 @@ svga_typeless_format(SVGA3dSurfaceFormat format)
case SVGA3D_R8_UINT:
case SVGA3D_R8_SNORM:
case SVGA3D_R8_SINT:
case SVGA3D_R8_TYPELESS:
return SVGA3D_R8_TYPELESS;
case SVGA3D_B8G8R8A8_UNORM_SRGB:
case SVGA3D_B8G8R8A8_UNORM:
@ -1939,16 +2013,28 @@ svga_typeless_format(SVGA3dSurfaceFormat format)
return SVGA3D_BC3_TYPELESS;
case SVGA3D_BC4_UNORM:
case SVGA3D_BC4_SNORM:
case SVGA3D_BC4_TYPELESS:
return SVGA3D_BC4_TYPELESS;
case SVGA3D_BC5_UNORM:
case SVGA3D_BC5_SNORM:
case SVGA3D_BC5_TYPELESS:
return SVGA3D_BC5_TYPELESS;
case SVGA3D_BC6H_UF16:
case SVGA3D_BC6H_SF16:
case SVGA3D_BC6H_TYPELESS:
return SVGA3D_BC6H_TYPELESS;
case SVGA3D_BC7_UNORM:
case SVGA3D_BC7_UNORM_SRGB:
case SVGA3D_BC7_TYPELESS:
return SVGA3D_BC7_TYPELESS;
case SVGA3D_R11G11B10_FLOAT:
case SVGA3D_R11G11B10_TYPELESS:
return SVGA3D_R11G11B10_TYPELESS;
/* Special cases (no corresponding _TYPELESS formats) */
case SVGA3D_A8_UNORM:
case SVGA3D_B5G5R5A1_UNORM:
case SVGA3D_B5G6R5_UNORM:
case SVGA3D_R11G11B10_FLOAT:
case SVGA3D_R9G9B9E5_SHAREDEXP:
return format;
default:
@ -2024,6 +2110,8 @@ svga_format_is_typeless(SVGA3dSurfaceFormat format)
case SVGA3D_BC3_TYPELESS:
case SVGA3D_BC4_TYPELESS:
case SVGA3D_BC5_TYPELESS:
case SVGA3D_BC6H_TYPELESS:
case SVGA3D_BC7_TYPELESS:
case SVGA3D_B8G8R8A8_TYPELESS:
case SVGA3D_B8G8R8X8_TYPELESS:
return true;
@ -2228,10 +2316,16 @@ svga_is_dx_format_supported(struct pipe_screen *screen,
assert(bindings);
assert(ss->sws->have_vgpu10);
if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
return false;
/* To support framebuffer without attachments */
if ((format == PIPE_FORMAT_NONE) && (bindings == PIPE_BIND_RENDER_TARGET))
return (ss->sws->have_gl43 && (sample_count <= ss->forcedSampleCount));
if (sample_count > 1) {
/* No MSAA support for shader image */
if (bindings & PIPE_BIND_SHADER_IMAGE)
return false;
/* In ms_samples, if bit N is set it means that we support
* multisample with N+1 samples per pixel.
*/
@ -2246,7 +2340,6 @@ svga_is_dx_format_supported(struct pipe_screen *screen,
*/
if (bindings & PIPE_BIND_VERTEX_BUFFER) {
SVGA3dSurfaceFormat svga_format;
unsigned flags;
svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
return svga_format != SVGA3D_FORMAT_INVALID;

2
src/gallium/drivers/svga/svga_format.h
View file

@ -60,6 +60,8 @@ struct svga_screen;
#define TF_XXXX (1 << 10) /* swizzle <X, X, X, X> */
#define TF_XXX1 (1 << 11) /* swizzle <X, X, X, 1> */
#define TF_XXXY (1 << 12) /* swizzle <X, X, X, Y> */
#define TF_UAV (1 << 13) /* supports uav */
#define TF_SM5 (1 << 14) /* supported in SM5 */
void
svga_translate_vertex_format_vgpu10(enum pipe_format format,

2
src/gallium/drivers/svga/svga_image_view.c
View file

@ -289,7 +289,7 @@ svga_validate_image_view_resources(struct svga_context *svga,
surf = tex->handle;
/* Mark texture as RENDERED */
svga_set_texture_rendered_to(tex, 0, 0);
svga_set_texture_rendered_to(tex);
}
assert(surf);

95
src/gallium/drivers/svga/svga_pipe_blit.c
View file

@ -103,8 +103,8 @@ intra_surface_copy(struct svga_context *svga, struct pipe_resource *tex,
SVGA_RETRY(svga, SVGA3D_vgpu10_IntraSurfaceCopy(svga->swc, stex->handle,
level, layer_face, &box));
/* Mark the texture subresource as rendered-to. */
svga_set_texture_rendered_to(stex, layer_face, level);
/* Mark the texture surface as RENDERED. */
svga_set_texture_rendered_to(stex);
}
/**
@ -139,8 +139,8 @@ copy_region_vgpu10(struct svga_context *svga, struct pipe_resource *src_tex,
/* Mark the texture subresource as defined. */
svga_define_texture_level(dtex, dst_layer_face, dst_level);
/* Mark the texture subresource as rendered-to. */
svga_set_texture_rendered_to(dtex, dst_layer_face, dst_level);
/* Mark the texture surface as RENDERED. */
svga_set_texture_rendered_to(dtex);
}
@ -504,7 +504,8 @@ try_copy_region(struct svga_context *svga,
blit->src.box.depth);
svga_define_texture_level(dtex, dst_layer_face, blit->dst.level);
svga_set_texture_rendered_to(dtex, dst_layer_face, blit->dst.level);
svga_set_texture_rendered_to(dtex);
return true;
}
@ -772,6 +773,66 @@ try_cpu_copy_region(struct svga_context *svga,
return false;
}
/**
* A helper function to resolve a multisampled surface to a single-sampled
* surface using SVGA command ResolveCopy.
*/
static boolean
try_resolve_copy(struct svga_context *svga,
const struct pipe_blit_info *blit)
{
enum pipe_error ret;
struct svga_texture *src_tex = svga_texture(blit->src.resource);
struct svga_texture *dst_tex = svga_texture(blit->dst.resource);
/* check if formats are compatible for resolve copy */
if (!formats_compatible(svga_screen(svga->pipe.screen),
src_tex->key.format, dst_tex->key.format))
return FALSE;
/* check if the copy dimensions are the same */
if ((blit->src.box.x || blit->src.box.y || blit->src.box.z) ||
(blit->dst.box.x || blit->dst.box.y || blit->dst.box.z) ||
(blit->src.box.width != blit->dst.box.width) ||
(blit->src.box.height != blit->dst.box.height) ||
(blit->src.box.depth != blit->dst.box.depth))
return FALSE;
ret = SVGA3D_vgpu10_ResolveCopy(svga->swc, 0, dst_tex->handle,
0, src_tex->handle, dst_tex->key.format);
if (ret != PIPE_OK) {
svga_context_flush(svga, NULL);
ret = SVGA3D_vgpu10_ResolveCopy(svga->swc, 0, dst_tex->handle,
0, src_tex->handle, dst_tex->key.format);
}
/* Mark surface state as RENDERED */
dst_tex->surface_state = SVGA_SURFACE_STATE_RENDERED;
return (ret == PIPE_OK);
}
/**
* Returns FALSE if the resource does not have data to copy.
*/
static boolean
is_texture_valid_to_copy(struct svga_context *svga,
struct pipe_resource *resource)
{
if (resource->target == PIPE_BUFFER) {
struct svga_buffer *buf = svga_buffer(resource);
struct svga_buffer_surface *bufsurf = buf->bufsurf;
return (bufsurf &&
bufsurf->surface_state >= SVGA_SURFACE_STATE_UPDATED);
} else {
struct svga_texture *tex = svga_texture(resource);
return ((tex->surface_state >= SVGA_SURFACE_STATE_UPDATED) ||
(resource->bind & PIPE_BIND_SHARED));
}
}
/**
* The pipe::blit member.
@ -794,6 +855,20 @@ svga_blit(struct pipe_context *pipe,
SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_BLIT);
if (!is_texture_valid_to_copy(svga, blit->src.resource)) {
debug_printf("%s: texture is not defined to copy\n",
__FUNCTION__);
goto done;
}
if (svga_have_sm4_1(svga) &&
blit->src.resource->nr_samples > 1 &&
blit->dst.resource->nr_samples <=1 &&
(blit->dst.resource->bind & PIPE_BIND_DISPLAY_TARGET)) {
if (try_resolve_copy(svga, blit))
goto done;
}
if (try_copy_region(svga, blit))
goto done;
@ -826,6 +901,12 @@ svga_resource_copy_region(struct pipe_context *pipe,
SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_COPYREGION);
if (!is_texture_valid_to_copy(svga, src_tex)) {
debug_printf("%s: texture is not defined to copy\n",
__FUNCTION__);
goto done;
}
if (dst_tex->target == PIPE_BUFFER && src_tex->target == PIPE_BUFFER) {
/* can't copy within the same buffer, unfortunately */
if (svga_have_vgpu10(svga) && src_tex != dst_tex) {
@ -841,6 +922,10 @@ svga_resource_copy_region(struct pipe_context *pipe,
dst_surf, src_box->x, dstx,
src_box->width));
dbuffer->dirty = TRUE;
/* Mark the buffer surface as RENDERED */
assert(dbuffer->bufsurf);
dbuffer->bufsurf->surface_state = SVGA_SURFACE_STATE_RENDERED;
}
else {
/* use map/memcpy fallback */

45
src/gallium/drivers/svga/svga_pipe_clear.c
View file

@ -174,14 +174,29 @@ try_clear(struct svga_context *svga,
if (svga_have_vgpu10(svga)) {
if (flags & SVGA3D_CLEAR_COLOR) {
unsigned i;
bool int_target = is_integer_target(fb, buffers);
if (is_integer_target(fb, buffers) && !ints_fit_in_floats(color)) {
if (int_target && !ints_fit_in_floats(color)) {
clear_buffers_with_quad(svga, buffers, color, depth, stencil);
/* We also cleared depth/stencil, so that's done */
flags &= ~(SVGA3D_CLEAR_DEPTH | SVGA3D_CLEAR_STENCIL);
}
else {
struct pipe_surface *rtv;
float rgba[4];
if (int_target) {
rgba[0] = (float) color->i[0];
rgba[1] = (float) color->i[1];
rgba[2] = (float) color->i[2];
rgba[3] = (float) color->i[3];
}
else {
rgba[0] = color->f[0];
rgba[1] = color->f[1];
rgba[2] = color->f[2];
rgba[3] = color->f[3];
}
/* Issue VGPU10 Clear commands */
for (i = 0; i < fb->nr_cbufs; i++) {
@ -194,8 +209,7 @@ try_clear(struct svga_context *svga,
if (!rtv)
return PIPE_ERROR_OUT_OF_MEMORY;
ret = SVGA3D_vgpu10_ClearRenderTargetView(svga->swc,
rtv, color->f);
ret = SVGA3D_vgpu10_ClearRenderTargetView(svga->swc, rtv, rgba);
if (ret != PIPE_OK)
return ret;
}
@ -325,7 +339,7 @@ svga_clear_texture(struct pipe_context *pipe,
if (box->x == 0 && box->y == 0 && box->width == surface->width &&
box->height == surface->height) {
/* clearing whole surface, use direct VGPU10 command */
assert(svga_surface(dsv)->view_id != SVGA3D_INVALID_ID);
SVGA_RETRY(svga, SVGA3D_vgpu10_ClearDepthStencilView(svga->swc, dsv,
clear_flags,
@ -367,16 +381,32 @@ svga_clear_texture(struct pipe_context *pipe,
if (box->x == 0 && box->y == 0 && box->width == surface->width &&
box->height == surface->height) {
struct pipe_framebuffer_state *curr = &svga->curr.framebuffer;
bool int_target = is_integer_target(curr, PIPE_CLEAR_COLOR);
if (is_integer_target(curr, PIPE_CLEAR_COLOR) &&
!ints_fit_in_floats(&color)) {
if (int_target && !ints_fit_in_floats(&color)) {
/* To clear full texture with integer format */
clear_buffers_with_quad(svga, PIPE_CLEAR_COLOR, &color, 0.0, 0);
}
else {
float rgba[4];
if (int_target) {
rgba[0] = (float) color.i[0];
rgba[1] = (float) color.i[1];
rgba[2] = (float) color.i[2];
rgba[3] = (float) color.i[3];
}
else {
rgba[0] = color.f[0];
rgba[1] = color.f[1];
rgba[2] = color.f[2];
rgba[3] = color.f[3];
}
/* clearing whole surface using VGPU10 command */
assert(svga_surface(rtv)->view_id != SVGA3D_INVALID_ID);
SVGA_RETRY(svga, SVGA3D_vgpu10_ClearRenderTargetView(svga->swc, rtv,
color.f));
rgba));
}
}
else {
@ -446,6 +476,7 @@ svga_try_clear_render_target(struct svga_context *svga,
if (!rtv)
return PIPE_ERROR_OUT_OF_MEMORY;
assert(svga_surface(rtv)->view_id != SVGA3D_INVALID_ID);
return SVGA3D_vgpu10_ClearRenderTargetView(svga->swc, rtv, color->f);
}

8
src/gallium/drivers/svga/svga_pipe_constants.c
View file

@ -54,6 +54,7 @@ svga_set_constant_buffer(struct pipe_context *pipe,
if (cb) {
buffer_size = cb->buffer_size;
if (cb->user_buffer) {
buf = svga_user_buffer_create(pipe->screen,
(void *) cb->user_buffer,
@ -94,6 +95,8 @@ svga_set_constant_buffer(struct pipe_context *pipe,
svga->dirty |= SVGA_NEW_TCS_CONSTS;
else if (shader == PIPE_SHADER_TESS_EVAL)
svga->dirty |= SVGA_NEW_TES_CONSTS;
else if (shader == PIPE_SHADER_COMPUTE)
svga->dirty |= SVGA_NEW_CS_CONSTS;
} else {
if (shader == PIPE_SHADER_FRAGMENT)
svga->dirty |= SVGA_NEW_FS_CONST_BUFFER;
@ -105,9 +108,14 @@ svga_set_constant_buffer(struct pipe_context *pipe,
svga->dirty |= SVGA_NEW_TCS_CONST_BUFFER;
else if (shader == PIPE_SHADER_TESS_EVAL)
svga->dirty |= SVGA_NEW_TES_CONST_BUFFER;
else if (shader == PIPE_SHADER_COMPUTE)
svga->dirty |= SVGA_NEW_CS_CONST_BUFFER;
/* update bitmask of dirty const buffers */
svga->state.dirty_constbufs[shader] |= (1 << index);
/* purge any stale rawbuf srv */
svga_destroy_rawbuf_srv(svga);
}
if (cb && cb->user_buffer) {

102
src/gallium/drivers/svga/svga_pipe_rasterizer.c
View file

@ -101,9 +101,10 @@ translate_cull_mode(unsigned cull)
}
static void
define_rasterizer_object(struct svga_context *svga,
struct svga_rasterizer_state *rast)
int
svga_define_rasterizer_object(struct svga_context *svga,
struct svga_rasterizer_state *rast,
unsigned samples)
{
struct svga_screen *svgascreen = svga_screen(svga->pipe.screen);
unsigned fill_mode = translate_fill_mode(rast->templ.fill_front);
@ -120,8 +121,10 @@ define_rasterizer_object(struct svga_context *svga,
rast->templ.line_stipple_pattern : 0;
const uint8 pv_last = !rast->templ.flatshade_first &&
svgascreen->haveProvokingVertex;
int rastId;
enum pipe_error ret;
rast->id = util_bitmask_add(svga->rast_object_id_bm);
rastId = util_bitmask_add(svga->rast_object_id_bm);
if (rast->templ.fill_front != rast->templ.fill_back) {
/* The VGPU10 device can't handle different front/back fill modes.
@ -131,24 +134,53 @@ define_rasterizer_object(struct svga_context *svga,
fill_mode = SVGA3D_FILLMODE_FILL;
}
SVGA_RETRY(svga, SVGA3D_vgpu10_DefineRasterizerState
(svga->swc,
rast->id,
fill_mode,
cull_mode,
rast->templ.front_ccw,
depth_bias,
depth_bias_clamp,
slope_scaled_depth_bias,
rast->templ.depth_clip_near,
rast->templ.scissor,
rast->templ.multisample,
rast->templ.line_smooth,
line_width,
rast->templ.line_stipple_enable,
line_factor,
line_pattern,
pv_last));
if (samples > 1 && svga_have_gl43(svga) &&
svgascreen->sws->have_rasterizer_state_v2_cmd) {
ret = SVGA3D_sm5_DefineRasterizerState_v2(svga->swc,
rastId,
fill_mode,
cull_mode,
rast->templ.front_ccw,
depth_bias,
depth_bias_clamp,
slope_scaled_depth_bias,
rast->templ.depth_clip_near,
rast->templ.scissor,
rast->templ.multisample,
rast->templ.line_smooth,
line_width,
rast->templ.line_stipple_enable,
line_factor,
line_pattern,
pv_last,
samples);
} else {
ret = SVGA3D_vgpu10_DefineRasterizerState(svga->swc,
rastId,
fill_mode,
cull_mode,
rast->templ.front_ccw,
depth_bias,
depth_bias_clamp,
slope_scaled_depth_bias,
rast->templ.depth_clip_near,
rast->templ.scissor,
rast->templ.multisample,
rast->templ.line_smooth,
line_width,
rast->templ.line_stipple_enable,
line_factor,
line_pattern,
pv_last);
}
if (ret != PIPE_OK) {
util_bitmask_clear(svga->rast_object_id_bm, rastId);
return SVGA3D_INVALID_ID;
}
return rastId;
}
@ -180,7 +212,7 @@ svga_create_rasterizer_state(struct pipe_context *pipe,
* though. Our smooth point implementation involves drawing a square,
* computing fragment distance from point center, then attenuating
* the fragment alpha value. We should not attenuate alpha if msaa
* is enabled. We should kill fragments entirely outside the circle
* is enabled. We should discard fragments entirely outside the circle
* and let the GPU compute per-fragment coverage.
* But as-is, our implementation gives acceptable results and passes
* Piglit's MSAA point smooth test.
@ -191,7 +223,7 @@ svga_create_rasterizer_state(struct pipe_context *pipe,
if (rast->templ.point_smooth &&
rast->templ.point_size_per_vertex == 0 &&
rast->templ.point_size <= screen->pointSmoothThreshold) {
/* If the point size is less than the threshold, disable smoothing.
/* If the point size is less than the threshold, deactivate smoothing.
* Note that this only effects point rendering when we use the
* pipe_rasterizer_state::point_size value, not when the point size
* is set in the VS.
@ -359,7 +391,23 @@ svga_create_rasterizer_state(struct pipe_context *pipe,
}
if (svga_have_vgpu10(svga)) {
define_rasterizer_object(svga, rast);
rast->id = svga_define_rasterizer_object(svga, rast, 0);
if (rast->id == SVGA3D_INVALID_ID) {
svga_context_flush(svga, NULL);
rast->id = svga_define_rasterizer_object(svga, rast, 0);
assert(rast->id != SVGA3D_INVALID_ID);
}
}
if (svga_have_gl43(svga)) {
/* initialize the alternate rasterizer state ids.
* For 0 and 1 sample count, we can use the same rasterizer object.
*/
rast->altRastIds[0] = rast->altRastIds[1] = rast->id;
for (unsigned i = 2; i < ARRAY_SIZE(rast->altRastIds); i++) {
rast->altRastIds[i] = SVGA3D_INVALID_ID;
}
}
if (templ->poly_smooth) {
@ -408,6 +456,10 @@ svga_delete_rasterizer_state(struct pipe_context *pipe, void *state)
struct svga_rasterizer_state *raster =
(struct svga_rasterizer_state *) state;
/* free any alternate rasterizer state used for point sprite */
if (raster->no_cull_rasterizer)
svga_delete_rasterizer_state(pipe, (void *)(raster->no_cull_rasterizer));
if (svga_have_vgpu10(svga)) {
SVGA_RETRY(svga, SVGA3D_vgpu10_DestroyRasterizerState(svga->swc,
raster->id));

4
src/gallium/drivers/svga/svga_pipe_sampler.c
View file

@ -341,7 +341,7 @@ svga_delete_sampler_state(struct pipe_context *pipe, void *sampler)
if (svga_have_vgpu10(svga)) {
unsigned i;
for (i = 0; i < 2; i++) {
for (i = 0; i < ARRAY_SIZE(ss->id); i++) {
if (ss->id[i] != SVGA3D_INVALID_ID) {
svga_hwtnl_flush_retry(svga);
@ -537,7 +537,7 @@ svga_cleanup_sampler_state(struct svga_context *svga)
{
enum pipe_shader_type shader;
for (shader = 0; shader <= PIPE_SHADER_TESS_EVAL; shader++) {
for (shader = 0; shader <= PIPE_SHADER_COMPUTE; shader++) {
unsigned i;
for (i = 0; i < svga->state.hw_draw.num_sampler_views[shader]; i++) {

5
src/gallium/drivers/svga/svga_pipe_streamout.c
View file

@ -450,6 +450,7 @@ svga_set_stream_output_targets(struct pipe_context *pipe,
for (i = 0; i < num_targets; i++) {
struct svga_stream_output_target *sot
= svga_stream_output_target(targets[i]);
struct svga_buffer *sbuf = svga_buffer(sot->base.buffer);
unsigned size;
svga->so_surfaces[i] = svga_buffer_handle(svga, sot->base.buffer,
@ -458,6 +459,10 @@ svga_set_stream_output_targets(struct pipe_context *pipe,
assert(svga_buffer(sot->base.buffer)->key.flags
& SVGA3D_SURFACE_BIND_STREAM_OUTPUT);
/* Mark the buffer surface as RENDERED */
assert(sbuf->bufsurf);
sbuf->bufsurf->surface_state = SVGA_SURFACE_STATE_RENDERED;
svga->so_targets[i] = &sot->base;
if (offsets[i] == -1) {
soBindings[i].offset = -1;

44
src/gallium/drivers/svga/svga_resource_buffer.c
View file

@ -79,6 +79,26 @@ svga_buffer_needs_hw_storage(const struct svga_screen *ss,
return !!(template->bind & bind_mask);
}
static inline boolean
need_buf_readback(struct svga_context *svga,
struct pipe_transfer *st)
{
struct svga_buffer *sbuf = svga_buffer(st->resource);
if (st->usage != PIPE_MAP_READ)
return FALSE;
/* No buffer surface has been created */
if (!sbuf->bufsurf)
return FALSE;
return ((sbuf->dirty ||
sbuf->bufsurf->surface_state == SVGA_SURFACE_STATE_RENDERED) &&
!sbuf->key.coherent && !svga->swc->force_coherent);
}
/**
* Create a buffer transfer.
*
@ -131,11 +151,12 @@ svga_buffer_transfer_map(struct pipe_context *pipe,
pipe_resource_reference(&sbuf->translated_indices.buffer, NULL);
}
if ((usage & PIPE_MAP_READ) && sbuf->dirty &&
!sbuf->key.coherent && !svga->swc->force_coherent) {
/* Host-side buffers can only be dirtied with vgpu10 features
* (streamout and buffer copy).
/* If it is a read transfer and the buffer is dirty or the buffer is bound
* to a uav, we will need to read the subresource content from the device.
*/
if (need_buf_readback(svga, transfer)) {
/* Host-side buffers can be dirtied with vgpu10 features
* (streamout and buffer copy) and sm5 feature via uav.
*/
assert(svga_have_vgpu10(svga));
@ -150,13 +171,16 @@ svga_buffer_transfer_map(struct pipe_context *pipe,
assert(sbuf->handle);
SVGA_RETRY(svga, SVGA3D_vgpu10_ReadbackSubResource(svga->swc,
sbuf->handle, 0));
SVGA_RETRY(svga, SVGA3D_ReadbackGBSurface(svga->swc, sbuf->handle));
svga->hud.num_readbacks++;
svga_context_finish(svga);
sbuf->dirty = FALSE;
/* Mark the buffer surface state as UPDATED */
assert(sbuf->bufsurf);
sbuf->bufsurf->surface_state = SVGA_SURFACE_STATE_UPDATED;
}
if (usage & PIPE_MAP_WRITE) {
@ -434,11 +458,13 @@ svga_resource_destroy(struct pipe_screen *screen,
DBG("%s deleting %p\n", __FUNCTION__, (void *) tex);
*/
SVGA_DBG(DEBUG_DMA, "unref sid %p (texture)\n", tex->handle);
svga_screen_surface_destroy(ss, &tex->key, &tex->handle);
boolean to_invalidate = svga_was_texture_rendered_to(tex);
svga_screen_surface_destroy(ss, &tex->key, to_invalidate, &tex->handle);
/* Destroy the backed surface handle if exists */
if (tex->backed_handle)
svga_screen_surface_destroy(ss, &tex->backed_key, &tex->backed_handle);
svga_screen_surface_destroy(ss, &tex->backed_key, to_invalidate, &tex->backed_handle);
ss->hud.total_resource_bytes -= tex->size;

12
src/gallium/drivers/svga/svga_resource_buffer.h
View file

@ -337,7 +337,13 @@ svga_buffer_hw_storage_unmap(struct svga_context *svga,
}
} else
sws->buffer_unmap(sws, sbuf->hwbuf);
/* Mark the buffer surface as UPDATED */
assert(sbuf->bufsurf);
sbuf->bufsurf->surface_state = SVGA_SURFACE_STATE_UPDATED;
}
static inline void
svga_set_buffer_rendered_to(struct svga_buffer_surface *bufsurf)
{
@ -345,6 +351,12 @@ svga_set_buffer_rendered_to(struct svga_buffer_surface *bufsurf)
}
static inline boolean
svga_was_buffer_rendered_to(const struct svga_buffer_surface *bufsurf)
{
return (bufsurf->surface_state == SVGA_SURFACE_STATE_RENDERED);
}
struct pipe_resource *
svga_user_buffer_create(struct pipe_screen *screen,

230
src/gallium/drivers/svga/svga_resource_buffer_upload.c
View file

@ -54,6 +54,10 @@ struct svga_3d_invalidate_gb_image {
};
static void
svga_buffer_upload_ranges(struct svga_context *, struct svga_buffer *);
/**
* Allocate a winsys_buffer (ie. DMA, aka GMR memory).
*
@ -142,8 +146,7 @@ svga_buffer_create_hw_storage(struct svga_screen *ss,
/**
* Allocate graphics memory for vertex/index/constant/etc buffer (not
* textures).
* Allocate graphics memory for vertex/index/constant/texture buffer.
*/
enum pipe_error
svga_buffer_create_host_surface(struct svga_screen *ss,
@ -155,7 +158,7 @@ svga_buffer_create_host_surface(struct svga_screen *ss,
assert(!sbuf->user);
if (!sbuf->handle) {
boolean validated;
boolean invalidated;
sbuf->key.flags = 0;
@ -190,6 +193,15 @@ svga_buffer_create_host_surface(struct svga_screen *ss,
sbuf->key.flags = SVGA3D_SURFACE_TRANSFER_FROM_BUFFER;
}
if (ss->sws->have_gl43 &&
(bind_flags & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE)) &&
(!(bind_flags & (PIPE_BIND_STREAM_OUTPUT)))) {
/* This surface can be bound to a uav. */
assert((bind_flags & PIPE_BIND_CONSTANT_BUFFER) == 0);
sbuf->key.flags |= SVGA3D_SURFACE_BIND_UAVIEW |
SVGA3D_SURFACE_BIND_RAW_VIEWS;
}
if (sbuf->b.flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) {
/* This surface can be mapped persistently. We use
* coherent memory to avoid implementing memory barriers for
@ -213,22 +225,31 @@ svga_buffer_create_host_surface(struct svga_screen *ss,
sbuf->handle = svga_screen_surface_create(ss, bind_flags,
sbuf->b.usage,
&validated, &sbuf->key);
&invalidated, &sbuf->key);
if (!sbuf->handle)
return PIPE_ERROR_OUT_OF_MEMORY;
/* Always set the discard flag on the first time the buffer is written
/* Set the discard flag on the first time the buffer is written
* as svga_screen_surface_create might have passed a recycled host
* buffer.
* buffer. This is only needed for host-backed mode. As in guest-backed
* mode, the recycled buffer would have been invalidated.
*/
sbuf->dma.flags.discard = TRUE;
if (!ss->sws->have_gb_objects)
sbuf->dma.flags.discard = TRUE;
SVGA_DBG(DEBUG_DMA, " --> got sid %p sz %d (buffer)\n",
sbuf->handle, sbuf->b.width0);
/* Add the new surface to the buffer surface list */
ret = svga_buffer_add_host_surface(sbuf, sbuf->handle, &sbuf->key,
bind_flags);
sbuf->bufsurf = svga_buffer_add_host_surface(sbuf, sbuf->handle,
&sbuf->key,
bind_flags);
if (sbuf->bufsurf == NULL)
return PIPE_ERROR_OUT_OF_MEMORY;
sbuf->bufsurf->surface_state =
invalidated ? SVGA_SURFACE_STATE_INVALIDATED :
SVGA_SURFACE_STATE_CREATED;
if (ss->sws->have_gb_objects) {
/* Initialize the surface with zero */
@ -263,14 +284,23 @@ svga_buffer_recreate_host_surface(struct svga_context *svga,
if (ret == PIPE_OK) {
/* Copy the surface data */
assert(sbuf->handle);
assert(sbuf->bufsurf);
SVGA_RETRY(svga, SVGA3D_vgpu10_BufferCopy(svga->swc, old_handle,
sbuf->handle,
0, 0, sbuf->b.width0));
/* Mark this surface as RENDERED */
sbuf->bufsurf->surface_state = SVGA_SURFACE_STATE_RENDERED;
}
/* Set the new bind flags for this buffer resource */
sbuf->bind_flags = bind_flags;
/* Set the dirty bit to signal a read back is needed before the data copied
* to this new surface can be referenced.
*/
sbuf->dirty = TRUE;
return ret;
}
@ -286,6 +316,10 @@ compatible_bind_flags(unsigned bind_flags,
return TRUE;
else if ((bind_flags|tobind_flags) & PIPE_BIND_CONSTANT_BUFFER)
return FALSE;
else if ((bind_flags & PIPE_BIND_STREAM_OUTPUT) &&
(tobind_flags & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SHADER_BUFFER)))
/* Stream out cannot be mixed with UAV */
return FALSE;
else
return TRUE;
}
@ -313,7 +347,7 @@ svga_buffer_get_host_surface(struct svga_buffer *sbuf,
/**
* Adds the host surface to the buffer surface list.
*/
enum pipe_error
struct svga_buffer_surface *
svga_buffer_add_host_surface(struct svga_buffer *sbuf,
struct svga_winsys_surface *handle,
struct svga_host_surface_cache_key *key,
@ -323,7 +357,7 @@ svga_buffer_add_host_surface(struct svga_buffer *sbuf,
bufsurf = CALLOC_STRUCT(svga_buffer_surface);
if (!bufsurf)
return PIPE_ERROR_OUT_OF_MEMORY;
return NULL;
bufsurf->bind_flags = bind_flags;
bufsurf->handle = handle;
@ -335,7 +369,7 @@ svga_buffer_add_host_surface(struct svga_buffer *sbuf,
/* Set the new bind flags for this buffer resource */
sbuf->bind_flags = bind_flags;
return PIPE_OK;
return bufsurf;
}
@ -358,12 +392,14 @@ svga_buffer_bind_host_surface(struct svga_context *svga,
SVGA_RETRY(svga, SVGA3D_vgpu10_BufferCopy(svga->swc, sbuf->handle,
bufsurf->handle,
0, 0, sbuf->b.width0));
bufsurf->surface_state = SVGA_SURFACE_STATE_RENDERED;
}
/* Set this surface as the current one */
sbuf->handle = bufsurf->handle;
sbuf->key = bufsurf->key;
sbuf->bind_flags = bufsurf->bind_flags;
sbuf->bufsurf = bufsurf;
}
@ -387,6 +423,9 @@ svga_buffer_validate_host_surface(struct svga_context *svga,
struct svga_buffer_surface *bufsurf;
enum pipe_error ret = PIPE_OK;
/* upload any dirty ranges */
svga_buffer_upload_ranges(svga, sbuf);
/* Flush any pending upload first */
svga_buffer_upload_flush(svga, sbuf);
@ -409,7 +448,9 @@ svga_buffer_validate_host_surface(struct svga_context *svga,
/* Destroy the old surface */
svga_screen_surface_destroy(svga_screen(sbuf->b.screen),
&bufsurf->key, &bufsurf->handle);
&bufsurf->key,
svga_was_buffer_rendered_to(bufsurf),
&bufsurf->handle);
list_del(&bufsurf->list);
FREE(bufsurf);
@ -434,7 +475,9 @@ svga_buffer_destroy_host_surface(struct svga_screen *ss,
LIST_FOR_EACH_ENTRY_SAFE(bufsurf, next, &sbuf->surfaces, list) {
SVGA_DBG(DEBUG_DMA, " ungrab sid %p sz %d\n",
bufsurf->handle, sbuf->b.width0);
svga_screen_surface_destroy(ss, &bufsurf->key, &bufsurf->handle);
svga_screen_surface_destroy(ss, &bufsurf->key,
svga_was_buffer_rendered_to(bufsurf),
&bufsurf->handle);
FREE(bufsurf);
}
}
@ -464,57 +507,20 @@ svga_buffer_upload_gb_command(struct svga_context *svga,
assert(numBoxes);
assert(sbuf->dma.updates == NULL);
if (sbuf->dma.flags.discard) {
struct svga_3d_invalidate_gb_image *cicmd = NULL;
SVGA3dCmdInvalidateGBImage *invalidate_cmd;
const unsigned total_commands_size =
sizeof(*invalidate_cmd) + numBoxes * sizeof(*whole_update_cmd);
/* Allocate FIFO space for 'numBoxes' UPDATE_GB_IMAGE commands */
const unsigned total_commands_size =
sizeof(*update_cmd) + (numBoxes - 1) * sizeof(*whole_update_cmd);
/* Allocate FIFO space for one INVALIDATE_GB_IMAGE command followed by
* 'numBoxes' UPDATE_GB_IMAGE commands. Allocate all at once rather
* than with separate commands because we need to properly deal with
* filling the command buffer.
*/
invalidate_cmd = SVGA3D_FIFOReserve(swc,
SVGA_3D_CMD_INVALIDATE_GB_IMAGE,
total_commands_size, 1 + numBoxes);
if (!invalidate_cmd)
return PIPE_ERROR_OUT_OF_MEMORY;
update_cmd = SVGA3D_FIFOReserve(swc,
SVGA_3D_CMD_UPDATE_GB_IMAGE,
total_commands_size, numBoxes);
if (!update_cmd)
return PIPE_ERROR_OUT_OF_MEMORY;
cicmd = container_of(invalidate_cmd, struct svga_3d_invalidate_gb_image, body);
cicmd->header.size = sizeof(*invalidate_cmd);
swc->surface_relocation(swc, &invalidate_cmd->image.sid, NULL,
sbuf->handle,
(SVGA_RELOC_WRITE |
SVGA_RELOC_INTERNAL |
SVGA_RELOC_DMA));
invalidate_cmd->image.face = 0;
invalidate_cmd->image.mipmap = 0;
/* The whole_update_command is a SVGA3dCmdHeader plus the
* SVGA3dCmdUpdateGBImage command.
*/
whole_update_cmd = (struct svga_3d_update_gb_image *) &invalidate_cmd[1];
/* initialize the first UPDATE_GB_IMAGE command */
whole_update_cmd->header.id = SVGA_3D_CMD_UPDATE_GB_IMAGE;
update_cmd = &whole_update_cmd->body;
} else {
/* Allocate FIFO space for 'numBoxes' UPDATE_GB_IMAGE commands */
const unsigned total_commands_size =
sizeof(*update_cmd) + (numBoxes - 1) * sizeof(*whole_update_cmd);
update_cmd = SVGA3D_FIFOReserve(swc,
SVGA_3D_CMD_UPDATE_GB_IMAGE,
total_commands_size, numBoxes);
if (!update_cmd)
return PIPE_ERROR_OUT_OF_MEMORY;
/* The whole_update_command is a SVGA3dCmdHeader plus the
* SVGA3dCmdUpdateGBImage command.
*/
whole_update_cmd = container_of(update_cmd, struct svga_3d_update_gb_image, body);
}
/* The whole_update_command is a SVGA3dCmdHeader plus the
* SVGA3dCmdUpdateGBImage command.
*/
whole_update_cmd = container_of(update_cmd, struct svga_3d_update_gb_image, body);
/* Init the first UPDATE_GB_IMAGE command */
whole_update_cmd->header.size = sizeof(*update_cmd);
@ -840,7 +846,6 @@ svga_buffer_add_range(struct svga_buffer *sbuf, unsigned start, unsigned end)
}
/**
* Copy the contents of the malloc buffer to a hardware buffer.
*/
@ -978,6 +983,61 @@ svga_buffer_upload_piecewise(struct svga_screen *ss,
}
/**
* A helper function to add an update command for the dirty ranges if there
* isn't already one.
*/
static void
svga_buffer_upload_ranges(struct svga_context *svga,
struct svga_buffer *sbuf)
{
struct pipe_screen *screen = svga->pipe.screen;
struct svga_screen *ss = svga_screen(screen);
enum pipe_error ret = PIPE_OK;
if (sbuf->map.num_ranges) {
if (!sbuf->dma.pending) {
/* No pending DMA/update commands yet. */
/* Migrate the data from swbuf -> hwbuf if necessary */
ret = svga_buffer_update_hw(svga, sbuf, sbuf->bind_flags);
if (ret == PIPE_OK) {
/* Emit DMA or UpdateGBImage commands */
SVGA_RETRY_OOM(svga, ret, svga_buffer_upload_command(svga, sbuf));
if (ret == PIPE_OK) {
sbuf->dma.pending = TRUE;
assert(!sbuf->head.prev && !sbuf->head.next);
list_addtail(&sbuf->head, &svga->dirty_buffers);
}
}
else if (ret == PIPE_ERROR_OUT_OF_MEMORY) {
/*
* The buffer is too big to fit in the GMR aperture, so break it in
* smaller pieces.
*/
ret = svga_buffer_upload_piecewise(ss, svga, sbuf);
}
if (ret != PIPE_OK) {
/*
* Something unexpected happened above. There is very little that
* we can do other than proceeding while ignoring the dirty ranges.
*/
assert(0);
sbuf->map.num_ranges = 0;
}
}
else {
/*
* There a pending dma already. Make sure it is from this context.
*/
assert(sbuf->dma.svga == svga);
}
}
return;
}
/**
* Get (or create/upload) the winsys surface handle so that we can
* refer to this buffer in fifo commands.
@ -1033,48 +1093,12 @@ svga_buffer_handle(struct svga_context *svga, struct pipe_resource *buf,
}
assert(sbuf->handle);
assert(sbuf->bufsurf);
if (svga->swc->force_coherent || sbuf->key.coherent)
return sbuf->handle;
if (sbuf->map.num_ranges) {
if (!sbuf->dma.pending) {
/* No pending DMA/update commands yet. */
/* Migrate the data from swbuf -> hwbuf if necessary */
ret = svga_buffer_update_hw(svga, sbuf, sbuf->bind_flags);
if (ret == PIPE_OK) {
/* Emit DMA or UpdateGBImage commands */
SVGA_RETRY_OOM(svga, ret, svga_buffer_upload_command(svga, sbuf));
if (ret == PIPE_OK) {
sbuf->dma.pending = TRUE;
assert(!sbuf->head.prev && !sbuf->head.next);
list_addtail(&sbuf->head, &svga->dirty_buffers);
}
}
else if (ret == PIPE_ERROR_OUT_OF_MEMORY) {
/*
* The buffer is too big to fit in the GMR aperture, so break it in
* smaller pieces.
*/
ret = svga_buffer_upload_piecewise(ss, svga, sbuf);
}
if (ret != PIPE_OK) {
/*
* Something unexpected happened above. There is very little that
* we can do other than proceeding while ignoring the dirty ranges.
*/
assert(0);
sbuf->map.num_ranges = 0;
}
}
else {
/*
* There a pending dma already. Make sure it is from this context.
*/
assert(sbuf->dma.svga == svga);
}
}
/* upload any dirty ranges */
svga_buffer_upload_ranges(svga, sbuf);
assert(sbuf->map.num_ranges == 0 || sbuf->dma.pending);

2
src/gallium/drivers/svga/svga_resource_buffer_upload.h
View file

@ -55,7 +55,7 @@ svga_buffer_recreate_host_surface(struct svga_context *svga,
struct svga_buffer *sbuf,
unsigned bind_flags);
enum pipe_error
struct svga_buffer_surface *
svga_buffer_add_host_surface(struct svga_buffer *sbuf,
struct svga_winsys_surface *handle,
struct svga_host_surface_cache_key *key,

171
src/gallium/drivers/svga/svga_resource_texture.c
View file

@ -231,8 +231,7 @@ need_tex_readback(struct svga_transfer *st)
if ((st->base.usage & PIPE_MAP_WRITE) &&
((st->base.usage & PIPE_MAP_DISCARD_WHOLE_RESOURCE) == 0)) {
return svga_was_texture_rendered_to(svga_texture(st->base.resource),
st->slice, st->base.level);
return svga_was_texture_rendered_to(svga_texture(st->base.resource));
}
return FALSE;
@ -240,30 +239,19 @@ need_tex_readback(struct svga_transfer *st)
static void
readback_image_vgpu9(struct svga_context *svga,
struct svga_winsys_surface *surf,
unsigned slice,
unsigned level)
readback_texture_surface(struct svga_context *svga,
struct svga_texture *tex,
struct svga_winsys_surface *surf)
{
SVGA_RETRY(svga, SVGA3D_ReadbackGBImage(svga->swc, surf, slice, level));
SVGA_RETRY(svga, SVGA3D_ReadbackGBSurface(svga->swc, surf));
/* Mark the texture surface as UPDATED */
tex->surface_state = SVGA_SURFACE_STATE_UPDATED;
svga->hud.num_readbacks++;
SVGA_STATS_COUNT_INC(svga_sws(svga), SVGA_STATS_COUNT_TEXREADBACK);
}
static void
readback_image_vgpu10(struct svga_context *svga,
struct svga_winsys_surface *surf,
unsigned slice,
unsigned level,
unsigned numMipLevels)
{
unsigned subResource;
subResource = slice * numMipLevels + level;
SVGA_RETRY(svga, SVGA3D_vgpu10_ReadbackSubResource(svga->swc, surf,
subResource));
}
/**
* Use DMA for the transfer request
*/
@ -346,23 +334,15 @@ svga_texture_transfer_map_direct(struct svga_context *svga,
struct svga_texture *tex = svga_texture(texture);
struct svga_winsys_surface *surf = tex->handle;
unsigned level = st->base.level;
unsigned w, h, nblocksx, nblocksy, i;
unsigned w, h, nblocksx, nblocksy;
unsigned usage = st->base.usage;
if (need_tex_readback(st)) {
svga_surfaces_flush(svga);
if (!svga->swc->force_coherent || tex->imported) {
for (i = 0; i < st->box.d; i++) {
if (svga_have_vgpu10(svga)) {
readback_image_vgpu10(svga, surf, st->slice + i, level,
tex->b.last_level + 1);
} else {
readback_image_vgpu9(svga, surf, st->slice + i, level);
}
}
svga->hud.num_readbacks++;
SVGA_STATS_COUNT_INC(sws, SVGA_STATS_COUNT_TEXREADBACK);
/* Readback the whole surface */
readback_texture_surface(svga, tex, surf);
svga_context_flush(svga, NULL);
}
@ -370,7 +350,7 @@ svga_texture_transfer_map_direct(struct svga_context *svga,
* Note: if PIPE_MAP_DISCARD_WHOLE_RESOURCE were specified
* we could potentially clear the flag for all faces/layers/mips.
*/
svga_clear_texture_rendered_to(tex, st->slice, level);
svga_clear_texture_rendered_to(tex);
}
else {
assert(usage & PIPE_MAP_WRITE);
@ -427,7 +407,6 @@ svga_texture_transfer_map_direct(struct svga_context *svga,
map = svga->swc->surface_map(svga->swc, surf, usage, &retry, &rebind);
svga_retry_exit(svga);
}
if (map && rebind) {
enum pipe_error ret;
@ -584,8 +563,7 @@ svga_texture_transfer_map(struct pipe_context *pipe,
boolean can_use_upload = tex->can_use_upload &&
!(st->base.usage & PIPE_MAP_READ);
boolean was_rendered_to =
svga_was_texture_rendered_to(svga_texture(texture),
st->slice, st->base.level);
svga_was_texture_rendered_to(svga_texture(texture));
/* If the texture was already rendered to and upload buffer
* is supported, then we will use upload buffer to
@ -721,7 +699,7 @@ svga_texture_transfer_unmap_dma(struct svga_context *svga,
}
svga_transfer_dma(svga, st, SVGA3D_WRITE_HOST_VRAM, flags);
svga_set_texture_rendered_to(tex, st->slice, st->base.level);
svga_set_texture_rendered_to(tex);
}
FREE(st->swbuf);
@ -785,6 +763,9 @@ svga_texture_transfer_unmap_direct(struct svga_context *svga,
transfer->level);
}
}
/* Mark the texture surface state as UPDATED */
tex->surface_state = SVGA_SURFACE_STATE_UPDATED;
}
}
@ -901,12 +882,6 @@ svga_texture_create(struct pipe_screen *screen,
goto fail_notex;
}
tex->rendered_to = CALLOC(template->depth0 * template->array_size,
sizeof(tex->rendered_to[0]));
if (!tex->rendered_to) {
goto fail;
}
tex->dirty = CALLOC(template->depth0 * template->array_size,
sizeof(tex->dirty[0]));
if (!tex->dirty) {
@ -1062,14 +1037,22 @@ svga_texture_create(struct pipe_screen *screen,
goto fail;
}
/* Use typeless formats for sRGB and depth resources. Typeless
* formats can be reinterpreted as other formats. For example,
* SVGA3D_R8G8B8A8_UNORM_TYPELESS can be interpreted as
* SVGA3D_R8G8B8A8_UNORM_SRGB or SVGA3D_R8G8B8A8_UNORM.
*/
if (svgascreen->sws->have_vgpu10 &&
(util_format_is_srgb(template->format) ||
format_has_depth(template->format))) {
bool use_typeless = FALSE;
if (svgascreen->sws->have_gl43) {
/* Do not use typeless for SHARED, SCANOUT or DISPLAY_TARGET surfaces. */
use_typeless = !(bindings & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT |
PIPE_BIND_DISPLAY_TARGET));
} else if (svgascreen->sws->have_vgpu10) {
/* For VGPU10 device, use typeless formats only for sRGB and depth resources
* if they do not have SHARED, SCANOUT or DISPLAY_TARGET bind flags
*/
use_typeless = (util_format_is_srgb(template->format) ||
format_has_depth(template->format)) &&
!(bindings & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT |
PIPE_BIND_DISPLAY_TARGET));
}
if (use_typeless) {
SVGA3dSurfaceFormat typeless = svga_typeless_format(tex->key.format);
if (0) {
debug_printf("Convert resource type %s -> %s (bind 0x%x)\n",
@ -1090,13 +1073,35 @@ svga_texture_create(struct pipe_screen *screen,
tex->key.format = typeless;
}
if (svgascreen->sws->have_sm5 &&
bindings & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET)) {
if (template->nr_samples < 2 &&
screen->is_format_supported(screen, template->format,
template->target,
template->nr_samples,
template->nr_storage_samples,
PIPE_BIND_SHADER_IMAGE)) {
/* Any non multi-samples texture that can be used as a render target
* or sampler view can be bound to an image unit.
* So make sure to set the UAV flag here.
*/
tex->key.flags |= SVGA3D_SURFACE_BIND_UAVIEW;
}
}
SVGA_DBG(DEBUG_DMA, "surface_create for texture\n");
boolean invalidated;
tex->handle = svga_screen_surface_create(svgascreen, bindings,
tex->b.usage,
&tex->validated, &tex->key);
&invalidated, &tex->key);
if (!tex->handle) {
goto fail;
}
if (invalidated) {
tex->surface_state = SVGA_SURFACE_STATE_INVALIDATED;
} else {
tex->surface_state = SVGA_SURFACE_STATE_CREATED;
}
SVGA_DBG(DEBUG_DMA, " --> got sid %p (texture)\n", tex->handle);
@ -1122,8 +1127,6 @@ svga_texture_create(struct pipe_screen *screen,
fail:
if (tex->dirty)
FREE(tex->dirty);
if (tex->rendered_to)
FREE(tex->rendered_to);
if (tex->defined)
FREE(tex->defined);
FREE(tex);
@ -1181,9 +1184,24 @@ svga_texture_from_handle(struct pipe_screen *screen,
tex->key.format = format;
tex->handle = srf;
tex->rendered_to = CALLOC(1, sizeof(tex->rendered_to[0]));
if (!tex->rendered_to)
goto out_no_rendered_to;
/* set bind flags for the imported texture handle according to the bind
* flags in the template
*/
if (template->bind & PIPE_BIND_RENDER_TARGET){
tex->key.flags |= SVGA3D_SURFACE_HINT_RENDERTARGET;
tex->key.flags |= SVGA3D_SURFACE_BIND_RENDER_TARGET;
}
if (template->bind & PIPE_BIND_DEPTH_STENCIL) {
tex->key.flags |= SVGA3D_SURFACE_HINT_DEPTHSTENCIL;
tex->key.flags |= SVGA3D_SURFACE_BIND_DEPTH_STENCIL;
}
if (template->bind & PIPE_BIND_SAMPLER_VIEW) {
tex->key.flags |= SVGA3D_SURFACE_HINT_TEXTURE;
tex->key.flags |= SVGA3D_SURFACE_BIND_SHADER_RESOURCE;
}
tex->dirty = CALLOC(1, sizeof(tex->dirty[0]));
if (!tex->dirty)
@ -1196,8 +1214,6 @@ svga_texture_from_handle(struct pipe_screen *screen,
return &tex->b;
out_no_dirty:
FREE(tex->rendered_to);
out_no_rendered_to:
FREE(tex->defined);
out_no_defined:
FREE(tex);
@ -1222,10 +1238,6 @@ svga_texture_generate_mipmap(struct pipe_context *pipe,
assert(svga_have_vgpu10(svga));
/* Only support 2D texture for now */
if (pt->target != PIPE_TEXTURE_2D)
return false;
/* Fallback to the mipmap generation utility for those formats that
* do not support hw generate mipmap
*/
@ -1239,11 +1251,21 @@ svga_texture_generate_mipmap(struct pipe_context *pipe,
return false;
templ.format = format;
templ.target = pt->target;
templ.u.tex.first_layer = first_layer;
templ.u.tex.last_layer = last_layer;
templ.u.tex.first_level = base_level;
templ.u.tex.last_level = last_level;
if (pt->target == PIPE_TEXTURE_CUBE) {
/**
* state tracker generates mipmap one face at a time.
* But SVGA generates mipmap for the entire cubemap.
*/
templ.u.tex.first_layer = 0;
templ.u.tex.last_layer = 5;
}
psv = pipe->create_sampler_view(pipe, pt, &templ);
if (psv == NULL)
return false;
@ -1254,6 +1276,9 @@ svga_texture_generate_mipmap(struct pipe_context *pipe,
SVGA_RETRY(svga, SVGA3D_vgpu10_GenMips(svga->swc, sv->id, tex->handle));
pipe_sampler_view_reference(&psv, NULL);
/* Mark the texture surface as RENDERED */
svga_set_texture_rendered_to(tex);
svga->hud.num_generate_mipmap++;
return true;
@ -1449,11 +1474,11 @@ svga_texture_transfer_unmap_upload(struct svga_context *svga,
dstsurf, subResource,
&st->upload.box));
offset += st->base.layer_stride;
/* Set rendered-to flag */
svga_set_texture_rendered_to(tex, layer, st->base.level);
}
/* Mark the texture surface state as RENDERED */
svga_set_texture_rendered_to(tex);
pipe_resource_reference(&st->upload.buf, NULL);
}
@ -1476,8 +1501,12 @@ svga_texture_device_format_has_alpha(struct pipe_resource *texture)
/* the svga_texture() call below is invalid for PIPE_BUFFER resources */
assert(texture->target != PIPE_BUFFER);
enum svga3d_block_desc block_desc =
svga3dsurface_get_desc(svga_texture(texture)->key.format)->block_desc;
const struct svga3d_surface_desc *surf_desc =
svga3dsurface_get_desc(svga_texture(texture)->key.format);
return !!(block_desc & SVGA3DBLOCKDESC_ALPHA);
enum svga3d_block_desc block_desc = surf_desc->block_desc;
return !!((block_desc & SVGA3DBLOCKDESC_ALPHA) ||
((block_desc == SVGA3DBLOCKDESC_TYPELESS) &&
(surf_desc->bitDepth.alpha > 0)));
}

31
src/gallium/drivers/svga/svga_resource_texture.h
View file

@ -33,6 +33,7 @@
#include "util/u_memory.h"
#include "util/u_transfer.h"
#include "svga_screen_cache.h"
#include "svga_context.h"
struct pipe_context;
struct pipe_screen;
@ -73,13 +74,6 @@ struct svga_texture
*/
struct svga_winsys_surface *handle;
/**
* Whether the host side surface is validated, either through the
* InvalidateGBSurface command or after the surface is updated
* or rendered to.
*/
boolean validated;
/**
* Whether the host side surface is imported and not created by this
* driver.
@ -101,6 +95,8 @@ struct svga_texture
*/
ushort *dirty;
enum svga_surface_state surface_state;
/**
* A cached backing host side surface to be used if this texture is being
* used for rendering and sampling at the same time.
@ -209,7 +205,6 @@ svga_define_texture_level(struct svga_texture *tex,
{
check_face_level(tex, face, level);
tex->defined[face] |= 1 << level;
tex->validated = TRUE;
}
@ -223,30 +218,22 @@ svga_is_texture_level_defined(const struct svga_texture *tex,
static inline void
svga_set_texture_rendered_to(struct svga_texture *tex,
unsigned face, unsigned level)
svga_set_texture_rendered_to(struct svga_texture *tex)
{
check_face_level(tex, face, level);
tex->rendered_to[face] |= 1 << level;
tex->validated = TRUE;
tex->surface_state = SVGA_SURFACE_STATE_RENDERED;
}
static inline void
svga_clear_texture_rendered_to(struct svga_texture *tex,
unsigned face, unsigned level)
svga_clear_texture_rendered_to(struct svga_texture *tex)
{
check_face_level(tex, face, level);
tex->rendered_to[face] &= ~(1 << level);
tex->surface_state = SVGA_SURFACE_STATE_UPDATED;
}
static inline boolean
svga_was_texture_rendered_to(const struct svga_texture *tex,
unsigned face, unsigned level)
svga_was_texture_rendered_to(const struct svga_texture *tex)
{
check_face_level(tex, face, level);
return !!(tex->rendered_to[face] & (1 << level));
return (tex->surface_state == SVGA_SURFACE_STATE_RENDERED);
}
static inline void

4
src/gallium/drivers/svga/svga_sampler_view.c
View file

@ -223,7 +223,9 @@ svga_destroy_sampler_view_priv(struct svga_sampler_view *v)
if (v->handle != tex->handle) {
struct svga_screen *ss = svga_screen(v->texture->screen);
SVGA_DBG(DEBUG_DMA, "unref sid %p (sampler view)\n", v->handle);
svga_screen_surface_destroy(ss, &v->key, &v->handle);
svga_screen_surface_destroy(ss, &v->key,
svga_was_texture_rendered_to(tex),
&v->handle);
}
/* Note: we're not refcounting the texture resource here to avoid

83
src/gallium/drivers/svga/svga_screen.c
View file

@ -74,6 +74,9 @@ static const struct debug_named_value svga_debug_flags[] = {
{ "streamout", DEBUG_STREAMOUT, NULL },
{ "query", DEBUG_QUERY, NULL },
{ "samplers", DEBUG_SAMPLERS, NULL },
{ "image", DEBUG_IMAGE, NULL },
{ "uav", DEBUG_UAV, NULL },
{ "retry", DEBUG_RETRY, NULL },
DEBUG_NAMED_VALUE_END
};
#endif
@ -621,7 +624,7 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
(shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL))
return 0;
if (shader == PIPE_SHADER_COMPUTE)
if ((!sws->have_gl43) && (shader == PIPE_SHADER_COMPUTE))
return 0;
/* NOTE: we do not query the device for any caps/limits at this time */
@ -725,6 +728,45 @@ svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
}
static int
svga_sm5_get_compute_param(struct pipe_screen *screen,
enum pipe_shader_ir ir_type,
enum pipe_compute_cap param,
void *ret)
{
ASSERTED struct svga_screen *svgascreen = svga_screen(screen);
ASSERTED struct svga_winsys_screen *sws = svgascreen->sws;
uint64_t *iret = (uint64_t *)ret;
assert(sws->have_gl43);
assert(ir_type == PIPE_SHADER_IR_TGSI);
switch (param) {
case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
iret[0] = 65535;
iret[1] = 65535;
iret[2] = 65535;
return 3 * sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
iret[0] = 1024;
iret[1] = 1024;
iret[2] = 64;
return 3 * sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
*iret = 1024;
return sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
*iret = 32768;
return sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
*iret = 0;
return sizeof(uint64_t);
default:
debug_printf("Unexpected compute param %u\n", param);
}
return 0;
}
static void
svga_fence_reference(struct pipe_screen *screen,
struct pipe_fence_handle **ptr,
@ -957,6 +999,9 @@ svga_screen_create(struct svga_winsys_screen *sws)
screen->fence_get_fd = svga_fence_get_fd;
screen->get_driver_query_info = svga_get_driver_query_info;
screen->get_compute_param = svga_sm5_get_compute_param;
svgascreen->sws = sws;
svga_init_screen_resource_functions(svgascreen);
@ -974,10 +1019,29 @@ svga_screen_create(struct svga_winsys_screen *sws)
goto error2;
}
svgascreen->debug.sampler_state_mapping =
debug_get_bool_option("SVGA_SAMPLER_STATE_MAPPING", FALSE);
if (sws->have_gl43) {
svgascreen->forcedSampleCount =
get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FORCED_SAMPLE_COUNT, 0);
sws->have_gl43 = sws->have_gl43 && (svgascreen->forcedSampleCount >= 4);
/* Allow a temporary environment variable to enable/disable GL43 support.
*/
sws->have_gl43 =
debug_get_bool_option("SVGA_GL43", sws->have_gl43);
svgascreen->debug.sampler_state_mapping =
debug_get_bool_option("SVGA_SAMPLER_STATE_MAPPING", FALSE);
}
else {
/* sampler state mapping code is only enabled with GL43
* due to the limitation in SW Renderer. (VMware bug 2825014)
*/
svgascreen->debug.sampler_state_mapping = FALSE;
}
debug_printf("%s enabled\n",
sws->have_gl43 ? "SM5+" :
sws->have_sm5 ? "SM5" :
sws->have_sm4_1 ? "SM4_1" :
sws->have_vgpu10 ? "VGPU10" : "VGPU9");
@ -1053,10 +1117,15 @@ svga_screen_create(struct svga_winsys_screen *sws)
}
/* Maximum number of constant buffers */
svgascreen->max_const_buffers =
get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
svgascreen->max_const_buffers = MIN2(svgascreen->max_const_buffers,
SVGA_MAX_CONST_BUFS);
if (sws->have_gl43) {
svgascreen->max_const_buffers = SVGA_MAX_CONST_BUFS;
}
else {
svgascreen->max_const_buffers =
get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
svgascreen->max_const_buffers = MIN2(svgascreen->max_const_buffers,
SVGA_MAX_CONST_BUFS);
}
svgascreen->haveBlendLogicops =
get_bool_cap(sws, SVGA3D_DEVCAP_LOGIC_BLENDOPS, FALSE);

1
src/gallium/drivers/svga/svga_screen.h
View file

@ -58,6 +58,7 @@ struct svga_screen
unsigned max_const_buffers;
unsigned max_viewports;
unsigned ms_samples;
unsigned forcedSampleCount; /* available with GL43 capable device only */
unsigned max_vs_inputs;
unsigned max_vs_outputs;
unsigned max_gs_inputs;

12
src/gallium/drivers/svga/svga_screen_cache.c
View file

@ -212,6 +212,7 @@ svga_screen_cache_shrink(struct svga_screen *svgascreen,
static void
svga_screen_cache_add(struct svga_screen *svgascreen,
const struct svga_host_surface_cache_key *key,
boolean to_invalidate,
struct svga_winsys_surface **p_handle)
{
struct svga_host_surface_cache *cache = &svgascreen->cache;
@ -293,8 +294,12 @@ svga_screen_cache_add(struct svga_screen *svgascreen,
"cache sid %p\n", entry->handle);
/* If we don't have gb objects, we don't need to invalidate. */
if (sws->have_gb_objects)
list_add(&entry->head, &cache->validated);
if (sws->have_gb_objects) {
if (to_invalidate)
list_add(&entry->head, &cache->validated);
else
list_add(&entry->head, &cache->invalidated);
}
else
list_add(&entry->head, &cache->invalidated);
@ -603,6 +608,7 @@ svga_screen_surface_create(struct svga_screen *svgascreen,
void
svga_screen_surface_destroy(struct svga_screen *svgascreen,
const struct svga_host_surface_cache_key *key,
boolean to_invalidate,
struct svga_winsys_surface **p_handle)
{
struct svga_winsys_screen *sws = svgascreen->sws;
@ -612,7 +618,7 @@ svga_screen_surface_destroy(struct svga_screen *svgascreen,
* that case.
*/
if (SVGA_SURFACE_CACHE_ENABLED && key->cachable) {
svga_screen_cache_add(svgascreen, key, p_handle);
svga_screen_cache_add(svgascreen, key, to_invalidate, p_handle);
}
else {
SVGA_DBG(DEBUG_DMA,

3
src/gallium/drivers/svga/svga_screen_cache.h
View file

@ -148,12 +148,13 @@ svga_screen_cache_init(struct svga_screen *svgascreen);
struct svga_winsys_surface *
svga_screen_surface_create(struct svga_screen *svgascreen,
unsigned bind_flags, enum pipe_resource_usage usage,
boolean *validated,
boolean *invalidated,
struct svga_host_surface_cache_key *key);
void
svga_screen_surface_destroy(struct svga_screen *svgascreen,
const struct svga_host_surface_cache_key *key,
boolean to_invalidate,
struct svga_winsys_surface **handle);
void

11
src/gallium/drivers/svga/svga_shader.c
View file

@ -465,7 +465,7 @@ svga_init_shader_key_common(const struct svga_context *svga,
}
if (svga_have_gl43(svga)) {
if (shader->info.images_declared ||
if (shader->info.images_declared || shader->info.hw_atomic_declared ||
shader->info.shader_buffers_declared) {
/* Save the uavSpliceIndex which is the index used for the first uav
@ -477,7 +477,7 @@ svga_init_shader_key_common(const struct svga_context *svga,
unsigned uav_splice_index = key->uav_splice_index;
/* Also get the texture data type to be used in the uav declaration */
struct svga_image_view *cur_image_view =
const struct svga_image_view *cur_image_view =
&svga->curr.image_views[shader_type][0];
for (unsigned i = 0; i < ARRAY_SIZE(svga->curr.image_views[shader_type]);
@ -512,7 +512,7 @@ svga_init_shader_key_common(const struct svga_context *svga,
key->images[i].uav_index = SVGA3D_INVALID_ID;
}
struct svga_shader_buffer *cur_sbuf =
const struct svga_shader_buffer *cur_sbuf =
&svga->curr.shader_buffers[shader_type][0];
for (unsigned i = 0; i < ARRAY_SIZE(svga->curr.shader_buffers[shader_type]);
@ -524,7 +524,7 @@ svga_init_shader_key_common(const struct svga_context *svga,
key->shader_buf_uav_index[i] = SVGA3D_INVALID_ID;
}
struct svga_shader_buffer *cur_buf = &svga->curr.atomic_buffers[0];
const struct svga_shader_buffer *cur_buf = &svga->curr.atomic_buffers[0];
for (unsigned i = 0; i < ARRAY_SIZE(svga->curr.atomic_buffers);
i++, cur_buf++) {
@ -786,6 +786,9 @@ svga_new_shader_variant(struct svga_context *svga, enum pipe_shader_type type)
case PIPE_SHADER_TESS_CTRL:
variant = CALLOC(1, sizeof(struct svga_tcs_variant));
break;
case PIPE_SHADER_COMPUTE:
variant = CALLOC(1, sizeof(struct svga_cs_variant));
break;
default:
return NULL;
}

6
src/gallium/drivers/svga/svga_shader.h
View file

@ -159,11 +159,11 @@ struct svga_compile_key
enum pipe_texture_target resource_target;
unsigned is_array:1;
unsigned is_single_layer:1;
unsigned uav_index:7;
unsigned uav_index;
} images[PIPE_MAX_SHADER_IMAGES];
uint16_t shader_buf_uav_index[PIPE_MAX_SHADER_BUFFERS];
uint16_t atomic_buf_uav_index[PIPE_MAX_HW_ATOMIC_BUFFERS];
uint32_t shader_buf_uav_index[PIPE_MAX_SHADER_BUFFERS];
uint32_t atomic_buf_uav_index[PIPE_MAX_HW_ATOMIC_BUFFERS];
};
/* A key for a variant of token string of a shader */

2
src/gallium/drivers/svga/svga_shader_buffer.c
View file

@ -97,7 +97,7 @@ svga_set_shader_buffers(struct pipe_context *pipe,
assert(start + num <= SVGA_MAX_SHADER_BUFFERS);
#ifdef DEBUG
struct pipe_shader_buffer *b = buffers;
const struct pipe_shader_buffer *b = buffers;
SVGA_DBG(DEBUG_UAV, "%s: shader=%d start=%d num=%d ",
__FUNCTION__, shader, start, num);
if (buffers) {

78
src/gallium/drivers/svga/svga_state.c
View file

@ -138,6 +138,39 @@ static const struct svga_tracked_state *hw_draw_state_sm5[] =
};
/**
* Atoms to update hardware state prior to emitting a draw packet
* for GL43 device which includes uav update.
*/
static const struct svga_tracked_state *hw_draw_state_gl43[] =
{
&svga_need_tgsi_transform,
&svga_hw_uav,
&svga_need_rawbuf_srv,
&svga_hw_fs,
&svga_hw_gs,
&svga_hw_tes,
&svga_hw_tcs,
&svga_hw_vs,
&svga_hw_rss,
&svga_hw_sampler,
&svga_hw_sampler_bindings,
&svga_hw_clip_planes,
&svga_hw_vdecl,
&svga_hw_fs_constants,
&svga_hw_fs_constbufs,
&svga_hw_gs_constants,
&svga_hw_gs_constbufs,
&svga_hw_tes_constants,
&svga_hw_tes_constbufs,
&svga_hw_tcs_constants,
&svga_hw_tcs_constbufs,
&svga_hw_vs_constants,
&svga_hw_vs_constbufs,
NULL
};
static const struct svga_tracked_state *swtnl_draw_state[] =
{
&svga_update_swtnl_draw,
@ -309,7 +342,6 @@ svga_update_state_retry(struct svga_context *svga, unsigned max_level)
}
#define EMIT_RS(_rs, _count, _name, _value) \
do { \
_rs[_count].state = _name; \
@ -383,7 +415,45 @@ svga_init_tracked_state(struct svga_context *svga)
{
/* Set the hw_draw_state atom list to the one for the particular gpu version.
*/
state_levels[2] = svga_have_sm5(svga) ? hw_draw_state_sm5 :
(svga_have_vgpu10(svga) ? hw_draw_state_vgpu10 :
hw_draw_state_vgpu9);
state_levels[2] =
svga_have_gl43(svga) ? hw_draw_state_gl43 :
(svga_have_sm5(svga) ? hw_draw_state_sm5 :
((svga_have_vgpu10(svga) ? hw_draw_state_vgpu10 :
hw_draw_state_vgpu9)));
}
static const struct svga_tracked_state *compute_state[] =
{
&svga_hw_cs_uav,
&svga_hw_cs_sampler,
&svga_hw_cs_sampler_bindings,
&svga_hw_cs,
&svga_hw_cs_constants,
&svga_hw_cs_constbufs,
NULL
};
/**
* Update compute state.
* If the first attempt fails, flush the command buffer and retry.
* \return true if success, false if second attempt fails.
*/
bool
svga_update_compute_state(struct svga_context *svga)
{
enum pipe_error ret = PIPE_OK;
uint64_t compute_dirty = svga->dirty;
if (compute_dirty) {
SVGA_RETRY_OOM(svga, ret, update_state(svga, compute_state,
&compute_dirty));
/* Set the dirty flag to the remaining dirty bits which are
* not processed in the compute pipeline.
*/
svga->dirty = compute_dirty;
}
return ret == PIPE_OK;
}

11
src/gallium/drivers/svga/svga_state.h
View file

@ -76,11 +76,22 @@ extern struct svga_tracked_state svga_hw_gs_constants;
extern struct svga_tracked_state svga_hw_vs_constants;
extern struct svga_tracked_state svga_hw_tes_constants;
extern struct svga_tracked_state svga_hw_tcs_constants;
extern struct svga_tracked_state svga_hw_cs_constants;
extern struct svga_tracked_state svga_hw_fs_constbufs;
extern struct svga_tracked_state svga_hw_vs_constbufs;
extern struct svga_tracked_state svga_hw_gs_constbufs;
extern struct svga_tracked_state svga_hw_tcs_constbufs;
extern struct svga_tracked_state svga_hw_tes_constbufs;
extern struct svga_tracked_state svga_hw_cs_constbufs;
extern struct svga_tracked_state svga_hw_uav;
extern struct svga_tracked_state svga_hw_cs;
extern struct svga_tracked_state svga_hw_cs_uav;
extern struct svga_tracked_state svga_hw_cs_sampler;
extern struct svga_tracked_state svga_hw_cs_sampler_bindings;
extern struct svga_tracked_state svga_need_rawbuf_srv;
extern struct svga_tracked_state svga_cs_need_rawbuf_srv;
/* SWTNL_DRAW
*/

379
src/gallium/drivers/svga/svga_state_constants.c
View file

@ -25,6 +25,7 @@
**********************************************************/
#include "util/format/u_format.h"
#include "util/u_bitmask.h"
#include "util/u_inlines.h"
#include "util/u_memory.h"
#include "pipe/p_defines.h"
@ -42,6 +43,44 @@
#include "svga_hw_reg.h"
static unsigned
svga_get_image_size_constant(const struct svga_context *svga, float **dest,
enum pipe_shader_type shader,
unsigned num_image_views,
const struct svga_image_view images[PIPE_SHADER_TYPES][SVGA3D_MAX_UAVIEWS])
{
uint32_t *dest_u = (uint32_t *) *dest;
for (int i = 0; i < num_image_views; i++) {
if (images[shader][i].desc.resource) {
if (images[shader][i].desc.resource->target == PIPE_BUFFER) {
unsigned bytes_per_element = util_format_get_blocksize(images[shader][i].desc.format);
*dest_u++ = images[shader][i].desc.resource->width0 / bytes_per_element;
}
else
*dest_u++ = images[shader][i].desc.resource->width0;
if (images[shader][i].desc.resource->target == PIPE_TEXTURE_1D_ARRAY)
*dest_u++ = images[shader][i].desc.resource->array_size;
else
*dest_u++ = images[shader][i].desc.resource->height0;
if (images[shader][i].desc.resource->target == PIPE_TEXTURE_2D_ARRAY)
*dest_u++ = images[shader][i].desc.resource->array_size;
else if (images[shader][i].desc.resource->target == PIPE_TEXTURE_CUBE_ARRAY)
*dest_u++ = images[shader][i].desc.resource->array_size / 6;
else
*dest_u++ = images[shader][i].desc.resource->depth0;
*dest_u++ = 1; // Later this can be used for sample counts
}
else {
*dest_u += 4;
}
}
return num_image_views;
}
/*
* Don't try to send more than 4kb of successive constants.
*/
@ -104,6 +143,14 @@ svga_get_extra_constants_common(const struct svga_context *svga,
}
}
/* image_size */
if (variant->key.image_size_used) {
count += svga_get_image_size_constant(svga, &dest, shader,
svga->state.hw_draw.num_image_views[shader],
svga->state.hw_draw.image_views);
}
return count;
}
@ -571,6 +618,121 @@ emit_consts_vgpu9(struct svga_context *svga, enum pipe_shader_type shader)
}
/**
* A helper function to destroy any pending unused srv.
*/
void
svga_destroy_rawbuf_srv(struct svga_context *svga)
{
unsigned index = 0;
while ((index = util_bitmask_get_next_index(
svga->sampler_view_to_free_id_bm, index))
!= UTIL_BITMASK_INVALID_INDEX) {
SVGA_RETRY(svga, SVGA3D_vgpu10_DestroyShaderResourceView(svga->swc,
index));
util_bitmask_clear(svga->sampler_view_id_bm, index);
util_bitmask_clear(svga->sampler_view_to_free_id_bm, index);
}
}
/**
* A helper function to emit constant buffer as srv raw buffer.
*/
static enum pipe_error
emit_rawbuf(struct svga_context *svga,
unsigned slot,
enum pipe_shader_type shader,
unsigned buffer_offset,
unsigned buffer_size,
void *buffer)
{
enum pipe_error ret = PIPE_OK;
struct svga_raw_buffer *rawbuf = &svga->state.hw_draw.rawbufs[shader][slot];
struct svga_winsys_surface *buf_handle = NULL;
unsigned srvid = SVGA3D_INVALID_ID;
unsigned enabled_rawbufs = svga->state.hw_draw.enabled_rawbufs[shader];
SVGA_STATS_TIME_PUSH(svga_sws(svga), SVGA_STATS_TIME_EMITRAWBUFFER);
if (buffer == NULL) {
if ((svga->state.hw_draw.enabled_rawbufs[shader] & (1 << slot)) == 0) {
goto done;
}
enabled_rawbufs &= ~(1 << slot);
}
else {
if ((rawbuf->buffer_offset != buffer_offset) ||
(rawbuf->buffer_size != buffer_size) ||
(rawbuf->buffer != buffer)) {
/* Add the current srvid to the delete list */
if (rawbuf->srvid != SVGA3D_INVALID_ID) {
util_bitmask_set(svga->sampler_view_to_free_id_bm, rawbuf->srvid);
rawbuf->srvid = SVGA3D_INVALID_ID;
}
buf_handle = svga_buffer_handle(svga, buffer,
PIPE_BIND_SAMPLER_VIEW);
if (!buf_handle) {
ret = PIPE_ERROR_OUT_OF_MEMORY;
goto done;
}
/* Create a srv for the constant buffer */
srvid = util_bitmask_add(svga->sampler_view_id_bm);
SVGA3dShaderResourceViewDesc viewDesc;
viewDesc.bufferex.firstElement = buffer_offset / 4;
viewDesc.bufferex.numElements = buffer_size / 4;
viewDesc.bufferex.flags = SVGA3D_BUFFEREX_SRV_RAW;
ret = SVGA3D_vgpu10_DefineShaderResourceView(svga->swc,
srvid, buf_handle, SVGA3D_R32_TYPELESS,
SVGA3D_RESOURCE_BUFFEREX, &viewDesc);
if (ret != PIPE_OK) {
util_bitmask_clear(svga->sampler_view_id_bm, srvid);
goto done;
}
/* Save the current raw buffer attributes in the slot */
rawbuf->srvid = srvid;
rawbuf->buffer_size = buffer_size;
rawbuf->buffer = buffer;
rawbuf->handle = buf_handle;
SVGA_STATS_COUNT_INC(svga_sws(svga), SVGA_STATS_COUNT_RAWBUFFERSRVIEW);
}
else {
/* Same buffer attributes in the slot. Can use the same SRV. */
assert(rawbuf->srvid != SVGA3D_INVALID_ID);
srvid = rawbuf->srvid;
buf_handle = rawbuf->handle;
}
enabled_rawbufs |= (1 << slot);
}
ret = SVGA3D_vgpu10_SetShaderResources(svga->swc,
svga_shader_type(shader),
slot + PIPE_MAX_SAMPLERS,
1,
&srvid,
&buf_handle);
if (ret != PIPE_OK) {
goto done;
}
/* Save the enabled rawbuf state */
svga->state.hw_draw.enabled_rawbufs[shader] = enabled_rawbufs;
done:
SVGA_STATS_TIME_POP(svga_sws(svga));
return ret;
}
/**
* A helper function to emit a constant buffer binding at the
* specified slot for the specified shader type
@ -678,6 +840,9 @@ emit_constbuf(struct svga_context *svga,
assert(new_buf_size % 16 == 0);
/* clamp the buf size before sending the command */
new_buf_size = MIN2(new_buf_size, SVGA3D_DX_MAX_CONSTBUF_BINDING_SIZE);
const struct svga_screen *screen = svga_screen(svga->pipe.screen);
const struct svga_winsys_screen *sws = screen->sws;
@ -850,11 +1015,42 @@ emit_constbuf_vgpu10(struct svga_context *svga, enum pipe_shader_type shader)
assert(size % 16 == 0);
ret = emit_constbuf(svga, index, shader, offset, size, buffer,
0, 0, NULL);
if (ret != PIPE_OK)
return ret;
/**
* If the buffer has been bound as an uav buffer, it will
* need to be bound as a shader resource raw buffer.
*/
if (svga->state.raw_constbufs[shader] & (1 << index)) {
ret = emit_rawbuf(svga, index, shader, offset, size, buffer);
if (ret != PIPE_OK) {
return ret;
}
ret = emit_constbuf(svga, index, shader, 0, 0, NULL,
0, 0, NULL);
if (ret != PIPE_OK) {
return ret;
}
/* Remove the rawbuf from the to-be-enabled constbuf list
* so the buffer will not be referenced again as constant buffer
* at resource validation time.
*/
enabled_constbufs &= ~(1 << index);
}
else {
if (svga->state.hw_draw.enabled_rawbufs[shader] & (1 << index)) {
ret = emit_rawbuf(svga, index, shader, offset, size, NULL);
if (ret != PIPE_OK) {
return ret;
}
}
ret = emit_constbuf(svga, index, shader, offset, size, buffer,
0, 0, NULL);
if (ret != PIPE_OK) {
return ret;
}
}
svga->hud.num_const_buf_updates++;
}
@ -909,7 +1105,8 @@ emit_fs_constbuf(struct svga_context *svga, uint64_t dirty)
struct svga_tracked_state svga_hw_fs_constants =
{
"hw fs params",
(SVGA_NEW_FS_CONSTS |
(SVGA_NEW_IMAGE_VIEW |
SVGA_NEW_FS_CONSTS |
SVGA_NEW_FS_VARIANT |
SVGA_NEW_TEXTURE_CONSTS),
emit_fs_consts
@ -972,6 +1169,7 @@ struct svga_tracked_state svga_hw_vs_constants =
{
"hw vs params",
(SVGA_NEW_PRESCALE |
SVGA_NEW_IMAGE_VIEW |
SVGA_NEW_VS_CONSTS |
SVGA_NEW_VS_VARIANT |
SVGA_NEW_TEXTURE_CONSTS),
@ -1040,6 +1238,7 @@ struct svga_tracked_state svga_hw_gs_constants =
{
"hw gs params",
(SVGA_NEW_PRESCALE |
SVGA_NEW_IMAGE_VIEW |
SVGA_NEW_GS_CONSTS |
SVGA_NEW_RAST |
SVGA_NEW_GS_VARIANT |
@ -1102,7 +1301,8 @@ emit_tcs_constbuf(struct svga_context *svga, uint64_t dirty)
struct svga_tracked_state svga_hw_tcs_constants =
{
"hw tcs params",
(SVGA_NEW_TCS_CONSTS |
(SVGA_NEW_IMAGE_VIEW |
SVGA_NEW_TCS_CONSTS |
SVGA_NEW_TCS_VARIANT),
emit_tcs_consts
};
@ -1161,6 +1361,7 @@ struct svga_tracked_state svga_hw_tes_constants =
{
"hw tes params",
(SVGA_NEW_PRESCALE |
SVGA_NEW_IMAGE_VIEW |
SVGA_NEW_TES_CONSTS |
SVGA_NEW_TES_VARIANT),
emit_tes_consts
@ -1173,3 +1374,169 @@ struct svga_tracked_state svga_hw_tes_constbufs =
SVGA_NEW_TES_CONST_BUFFER,
emit_tes_constbuf
};
/**
* Emit constant buffer for compute shader
*/
static enum pipe_error
emit_cs_consts(struct svga_context *svga, uint64_t dirty)
{
const struct svga_shader_variant *variant = svga->state.hw_draw.cs;
enum pipe_error ret = PIPE_OK;
assert(svga_have_sm5(svga));
/* SVGA_NEW_CS_VARIANT */
if (!variant)
return PIPE_OK;
/* SVGA_NEW_CS_CONST_BUFFER */
ret = emit_consts_vgpu10(svga, PIPE_SHADER_COMPUTE);
return ret;
}
static enum pipe_error
emit_cs_constbuf(struct svga_context *svga, uint64_t dirty)
{
const struct svga_shader_variant *variant = svga->state.hw_draw.cs;
enum pipe_error ret = PIPE_OK;
/* SVGA_NEW_CS_VARIANT
*/
if (!variant)
return PIPE_OK;
/* SVGA_NEW_CS_CONSTBUF
*/
assert(svga_have_vgpu10(svga));
ret = emit_constbuf_vgpu10(svga, PIPE_SHADER_COMPUTE);
return ret;
}
struct svga_tracked_state svga_hw_cs_constants =
{
"hw cs params",
(SVGA_NEW_IMAGE_VIEW |
SVGA_NEW_CS_CONSTS |
SVGA_NEW_CS_VARIANT |
SVGA_NEW_TEXTURE_CONSTS),
emit_cs_consts
};
struct svga_tracked_state svga_hw_cs_constbufs =
{
"hw cs params",
SVGA_NEW_CS_CONST_BUFFER,
emit_cs_constbuf
};
/**
* A helper function to update the rawbuf for constbuf mask
*/
static void
update_rawbuf_mask(struct svga_context *svga, enum pipe_shader_type shader)
{
unsigned dirty_constbufs;
unsigned enabled_constbufs;
enabled_constbufs = svga->state.hw_draw.enabled_constbufs[shader] | 1u;
dirty_constbufs = (svga->state.dirty_constbufs[shader]|enabled_constbufs) & ~1u;
while (dirty_constbufs) {
unsigned index = u_bit_scan(&dirty_constbufs);
struct svga_buffer *sbuf =
svga_buffer(svga->curr.constbufs[shader][index].buffer);
if (sbuf && sbuf->uav) {
svga->state.raw_constbufs[shader] |= (1 << index);
} else {
svga->state.raw_constbufs[shader] &= ~(1 << index);
}
}
}
/**
* update_rawbuf is called at hw state update time to determine
* if any of the bound constant buffers need to be bound as
* raw buffer srv. This function is called after uav state is
* updated and before shader variants are bound.
*/
static enum pipe_error
update_rawbuf(struct svga_context *svga, uint64 dirty)
{
uint64_t rawbuf_dirtybit[] = {
SVGA_NEW_VS_RAW_BUFFER, /* PIPE_SHADER_VERTEX */
SVGA_NEW_FS_RAW_BUFFER, /* PIPE_SHADER_FRAGMENT */
SVGA_NEW_GS_RAW_BUFFER, /* PIPE_SHADER_GEOMETRY */
SVGA_NEW_TCS_RAW_BUFFER, /* PIPE_SHADER_TESS_CTRL */
SVGA_NEW_TES_RAW_BUFFER, /* PIPE_SHADER_TESS_EVAL */
};
for (enum pipe_shader_type shader = PIPE_SHADER_VERTEX;
shader <= PIPE_SHADER_TESS_EVAL; shader++) {
unsigned rawbuf_mask = svga->state.raw_constbufs[shader];
update_rawbuf_mask(svga, shader);
/* If the rawbuf state is different for the shader stage,
* send SVGA_NEW_XX_RAW_BUFFER to trigger a new shader
* variant that will use srv for ubo access.
*/
if (svga->state.raw_constbufs[shader] != rawbuf_mask)
svga->dirty |= rawbuf_dirtybit[shader];
}
return PIPE_OK;
}
struct svga_tracked_state svga_need_rawbuf_srv =
{
"raw buffer srv",
(SVGA_NEW_IMAGE_VIEW |
SVGA_NEW_SHADER_BUFFER |
SVGA_NEW_CONST_BUFFER),
update_rawbuf
};
/**
* update_cs_rawbuf is called at compute dispatch time to determine
* if any of the bound constant buffers need to be bound as
* raw buffer srv. This function is called after uav state is
* updated and before a compute shader variant is bound.
*/
static enum pipe_error
update_cs_rawbuf(struct svga_context *svga, uint64 dirty)
{
unsigned rawbuf_mask = svga->state.raw_constbufs[PIPE_SHADER_COMPUTE];
update_rawbuf_mask(svga, PIPE_SHADER_COMPUTE);
/* if the rawbuf state is different for the shader stage,
* send SVGA_NEW_RAW_BUFFER to trigger a new shader
* variant to use srv for ubo access.
*/
if (svga->state.raw_constbufs[PIPE_SHADER_COMPUTE] != rawbuf_mask)
svga->dirty |= SVGA_NEW_CS_RAW_BUFFER;
return PIPE_OK;
}
struct svga_tracked_state svga_cs_need_rawbuf_srv =
{
"raw buffer srv",
(SVGA_NEW_IMAGE_VIEW |
SVGA_NEW_SHADER_BUFFER |
SVGA_NEW_CONST_BUFFER),
update_cs_rawbuf
};

1
src/gallium/drivers/svga/svga_state_cs.c
View file

@ -91,6 +91,7 @@ make_cs_key(struct svga_context *svga,
pipe_buffer_unmap(&svga->pipe, transfer);
}
key->image_size_used = cs->base.info.opcode_count[TGSI_OPCODE_RESQ] ? 1 : 0;
}

16
src/gallium/drivers/svga/svga_state_framebuffer.c
View file

@ -87,8 +87,7 @@ emit_fb_vgpu9(struct svga_context *svga)
/* Set the rendered-to flag */
struct pipe_surface *s = curr->cbufs[i];
if (s) {
svga_set_texture_rendered_to(svga_texture(s->texture),
s->u.tex.first_layer, s->u.tex.level);
svga_set_texture_rendered_to(svga_texture(s->texture));
}
}
@ -119,8 +118,7 @@ emit_fb_vgpu9(struct svga_context *svga)
/* Set the rendered-to flag */
struct pipe_surface *s = curr->zsbuf;
if (s) {
svga_set_texture_rendered_to(svga_texture(s->texture),
s->u.tex.first_layer, s->u.tex.level);
svga_set_texture_rendered_to(svga_texture(s->texture));
}
}
@ -225,8 +223,7 @@ emit_fb_vgpu10(struct svga_context *svga)
last_rtv = i;
/* Set the rendered-to flag */
svga_set_texture_rendered_to(svga_texture(s->texture),
s->u.tex.first_layer, s->u.tex.level);
svga_set_texture_rendered_to(svga_texture(s->texture));
}
else {
rtv[i] = NULL;
@ -247,8 +244,7 @@ emit_fb_vgpu10(struct svga_context *svga)
}
/* Set the rendered-to flag */
svga_set_texture_rendered_to(svga_texture(s->texture),
s->u.tex.first_layer, s->u.tex.level);
svga_set_texture_rendered_to(svga_texture(s->texture));
}
else {
dsv = NULL;
@ -614,6 +610,10 @@ get_viewport_prescale(struct svga_context *svga,
prescale->translate[2] -= 0.5f;
}
/* Clamp depth range, making sure it's between 0 and 1 */
range_min = CLAMP(range_min, 0.0f, 1.0f);
range_max = CLAMP(range_max, 0.0f, 1.0f);
if (prescale->enabled) {
float H[2];
float J[2];

6
src/gallium/drivers/svga/svga_state_fs.c
View file

@ -369,6 +369,9 @@ make_fs_key(const struct svga_context *svga,
key->fs.write_color0_to_n_cbufs = svga->curr.framebuffer.nr_cbufs;
}
if (svga_have_gl43(svga))
key->image_size_used = fs->base.info.opcode_count[TGSI_OPCODE_RESQ] ? 1 : 0;
return PIPE_OK;
}
@ -498,7 +501,8 @@ struct svga_tracked_state svga_hw_fs =
SVGA_NEW_SAMPLER |
SVGA_NEW_FRAME_BUFFER |
SVGA_NEW_DEPTH_STENCIL_ALPHA |
SVGA_NEW_BLEND),
SVGA_NEW_BLEND |
SVGA_NEW_FS_RAW_BUFFER),
emit_hw_fs
};

6
src/gallium/drivers/svga/svga_state_gs.c
View file

@ -135,6 +135,9 @@ make_gs_key(struct svga_context *svga, struct svga_compile_key *key)
/* Mark this as the last shader in the vertex processing stage */
key->last_vertex_stage = 1;
if (svga_have_gl43(svga))
key->image_size_used = gs->base.info.opcode_count[TGSI_OPCODE_RESQ] ? 1 : 0;
}
@ -235,6 +238,7 @@ struct svga_tracked_state svga_hw_gs =
SVGA_NEW_TEXTURE_BINDING |
SVGA_NEW_SAMPLER |
SVGA_NEW_RAST |
SVGA_NEW_NEED_SWTNL),
SVGA_NEW_NEED_SWTNL |
SVGA_NEW_GS_RAW_BUFFER),
emit_hw_gs
};

59
src/gallium/drivers/svga/svga_state_rss.c
View file

@ -321,10 +321,9 @@ emit_rss_vgpu9(struct svga_context *svga, uint64_t dirty)
static struct svga_rasterizer_state *
get_no_cull_rasterizer_state(struct svga_context *svga)
{
const struct svga_rasterizer_state *r = svga->curr.rast;
unsigned int aa_point = r->templ.point_smooth;
struct svga_rasterizer_state *r = svga->curr.rast;
if (!svga->rasterizer_no_cull[aa_point]) {
if (!r->no_cull_rasterizer) {
struct pipe_rasterizer_state rast;
memset(&rast, 0, sizeof(rast));
@ -341,10 +340,10 @@ get_no_cull_rasterizer_state(struct svga_context *svga)
rast.bottom_edge_rule = r->templ.bottom_edge_rule;
rast.clip_halfz = r->templ.clip_halfz;
svga->rasterizer_no_cull[aa_point] =
r->no_cull_rasterizer =
svga->pipe.create_rasterizer_state(&svga->pipe, &rast);
}
return svga->rasterizer_no_cull[aa_point];
return r->no_cull_rasterizer;
}
@ -362,6 +361,29 @@ get_no_depth_stencil_test_state(struct svga_context *svga)
}
/**
* A helper function to create an alternate svga rasterizer state object to use
* forcedSampleCount to support multisampled framebuffer without attachments.
*/
static SVGA3dRasterizerStateId
get_alt_rasterizer_state_id(struct svga_context *svga,
struct svga_rasterizer_state *rast,
unsigned samples)
{
assert(samples <= SVGA_MAX_FRAMEBUFFER_DEFAULT_SAMPLES);
assert(samples >= 0);
if (samples <= 1)
return rast->id;
if (rast->altRastIds[samples] == SVGA3D_INVALID_ID) {
rast->altRastIds[samples] = svga_define_rasterizer_object(svga, rast, samples);
}
return rast->altRastIds[samples];
}
static enum pipe_error
emit_rss_vgpu10(struct svga_context *svga, uint64_t dirty)
{
@ -457,8 +479,9 @@ emit_rss_vgpu10(struct svga_context *svga, uint64_t dirty)
}
}
if (dirty & (SVGA_NEW_REDUCED_PRIMITIVE | SVGA_NEW_RAST)) {
const struct svga_rasterizer_state *rast;
if (dirty & (SVGA_NEW_REDUCED_PRIMITIVE | SVGA_NEW_RAST |
SVGA_NEW_FRAME_BUFFER)) {
struct svga_rasterizer_state *rast = svga->curr.rast;
if (svga->curr.reduced_prim == PIPE_PRIM_POINTS &&
svga->curr.gs && svga->curr.gs->wide_point) {
@ -468,16 +491,28 @@ emit_rss_vgpu10(struct svga_context *svga, uint64_t dirty)
*/
rast = get_no_cull_rasterizer_state(svga);
}
else {
rast = svga->curr.rast;
int rastId = rast->id;
/* In the case of no-attachment framebuffer, the sample count will be
* specified in forcedSampleCount in the RasterizerState_v2 object.
*/
if ((svga->curr.framebuffer.nr_cbufs == 0) &&
(svga->curr.framebuffer.zsbuf == NULL)) {
rastId =
get_alt_rasterizer_state_id(svga, rast,
svga->curr.framebuffer.samples);
if (rastId == SVGA3D_INVALID_ID)
return PIPE_ERROR;
}
if (svga->state.hw_draw.rasterizer_id != rast->id) {
if (svga->state.hw_draw.rasterizer_id != rastId) {
/* Set/bind the rasterizer state object */
ret = SVGA3D_vgpu10_SetRasterizerState(svga->swc, rast->id);
ret = SVGA3D_vgpu10_SetRasterizerState(svga->swc, rastId);
if (ret != PIPE_OK)
return ret;
svga->state.hw_draw.rasterizer_id = rast->id;
svga->state.hw_draw.rasterizer_id = rastId;
}
}
svga->state.hw_draw.rasterizer_discard = FALSE;

272
src/gallium/drivers/svga/svga_state_sampler.c
View file

@ -136,6 +136,7 @@ svga_validate_pipe_sampler_view(struct svga_context *svga,
SVGA3dResourceType resourceDim;
SVGA3dShaderResourceViewDesc viewDesc;
enum pipe_format viewFormat = sv->base.format;
enum pipe_texture_target target = sv->base.target;
/* vgpu10 cannot create a BGRX view for a BGRA resource, so force it to
* create a BGRA view (and vice versa).
@ -149,8 +150,9 @@ svga_validate_pipe_sampler_view(struct svga_context *svga,
viewFormat = PIPE_FORMAT_B8G8R8X8_UNORM;
}
if (texture->target == PIPE_BUFFER) {
if (target == PIPE_BUFFER) {
unsigned pf_flags;
assert(texture->target == PIPE_BUFFER);
svga_translate_texture_buffer_view_format(viewFormat,
&format,
&pf_flags);
@ -168,7 +170,7 @@ svga_validate_pipe_sampler_view(struct svga_context *svga,
assert(format != SVGA3D_FORMAT_INVALID);
if (texture->target == PIPE_BUFFER) {
if (target == PIPE_BUFFER) {
unsigned elem_size = util_format_get_blocksize(sv->base.format);
viewDesc.buffer.firstElement = sv->base.u.buf.offset / elem_size;
@ -188,11 +190,10 @@ svga_validate_pipe_sampler_view(struct svga_context *svga,
* hence we need to set arraySize to 1 explicitly.
*/
viewDesc.tex.arraySize =
(texture->target == PIPE_TEXTURE_3D ||
texture->target == PIPE_BUFFER) ? 1 :
(target == PIPE_TEXTURE_3D || target == PIPE_BUFFER) ? 1 :
(sv->base.u.tex.last_layer - sv->base.u.tex.first_layer + 1);
switch (texture->target) {
switch (target) {
case PIPE_BUFFER:
resourceDim = SVGA3D_RESOURCE_BUFFER;
break;
@ -397,55 +398,100 @@ update_samplers(struct svga_context *svga, uint64_t dirty )
for (shader = PIPE_SHADER_VERTEX; shader <= PIPE_SHADER_TESS_EVAL; shader++) {
const unsigned count = svga->curr.num_samplers[shader];
SVGA3dSamplerId ids[PIPE_MAX_SAMPLERS];
SVGA3dSamplerId ids[PIPE_MAX_SAMPLERS*2];
unsigned i;
unsigned nsamplers;
unsigned nsamplers = 0;
boolean sampler_state_mapping =
svga_use_sampler_state_mapping(svga, count);
for (i = 0; i < count; i++) {
bool fs_shadow = false;
const struct svga_sampler_state *sampler = svga->curr.sampler[shader][i];
/* _NEW_FS */
if (shader == PIPE_SHADER_FRAGMENT) {
struct svga_fs_variant *fs =
svga_fs_variant(svga->state.hw_draw.fs);
/* If the fragment shader is doing the shadow comparison
* for this texture unit, don't enable shadow compare in
* the texture sampler state.
*/
if (fs && (fs->fs_shadow_compare_units & (1 << i))) {
/* Use the alternate sampler state with the compare
* bit disabled when comparison is done in the shader and
* sampler state mapping is not enabled.
*/
fs_shadow = true;
}
}
if (svga->curr.sampler[shader][i]) {
ids[i] = svga->curr.sampler[shader][i]->id[fs_shadow];
assert(ids[i] != SVGA3D_INVALID_ID);
if (!sampler_state_mapping) {
if (sampler) {
SVGA3dSamplerId id = sampler->id[fs_shadow];
assert(id != SVGA3D_INVALID_ID);
ids[i] = id;
}
else {
ids[i] = SVGA3D_INVALID_ID;
}
nsamplers++;
}
else {
ids[i] = SVGA3D_INVALID_ID;
if (sampler) {
SVGA3dSamplerId id = sampler->id[0];
assert(id != SVGA3D_INVALID_ID);
/* Check if the sampler id is already on the ids list */
unsigned k;
for (k = 0; k < nsamplers; k++) {
if (ids[k] == id)
break;
}
/* add the id to the list if it is not already on the list */
if (k == nsamplers) {
ids[nsamplers++] = id;
if (sampler->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
/*
* add the alternate sampler state as well as the shader
* might use this alternate sampler state which has comparison
* disabled when the comparison is done in the shader.
*/
ids[nsamplers++] = sampler->id[1];
}
}
}
}
}
for (; i < svga->state.hw_draw.num_samplers[shader]; i++) {
for (i = nsamplers; i < svga->state.hw_draw.num_samplers[shader]; i++) {
ids[i] = SVGA3D_INVALID_ID;
}
nsamplers = MAX2(svga->state.hw_draw.num_samplers[shader], count);
if (nsamplers > 0) {
if (count != svga->state.hw_draw.num_samplers[shader] ||
unsigned nsamplerIds =
MAX2(nsamplers, svga->state.hw_draw.num_samplers[shader]);
if (nsamplerIds > 0) {
if (nsamplers > SVGA3D_DX_MAX_SAMPLERS) {
debug_warn_once("Too many sampler states");
nsamplers = SVGA3D_DX_MAX_SAMPLERS;
}
if (nsamplers != svga->state.hw_draw.num_samplers[shader] ||
memcmp(ids, svga->state.hw_draw.samplers[shader],
count * sizeof(ids[0])) != 0) {
nsamplerIds * sizeof(ids[0])) != 0) {
/* HW state is really changing */
ret = SVGA3D_vgpu10_SetSamplers(svga->swc,
nsamplers,
nsamplerIds,
0, /* start */
svga_shader_type(shader), /* type */
ids);
if (ret != PIPE_OK)
return ret;
memcpy(svga->state.hw_draw.samplers[shader], ids,
nsamplers * sizeof(ids[0]));
svga->state.hw_draw.num_samplers[shader] = count;
nsamplerIds * sizeof(ids[0]));
svga->state.hw_draw.num_samplers[shader] = nsamplers;
}
}
}
@ -453,7 +499,7 @@ update_samplers(struct svga_context *svga, uint64_t dirty )
/* Handle polygon stipple sampler texture */
if (svga->curr.rast->templ.poly_stipple_enable) {
const unsigned unit =
svga_fs_variant(svga->state.hw_draw.fs)->pstipple_sampler_unit;
svga_fs_variant(svga->state.hw_draw.fs)->pstipple_sampler_state_index;
struct svga_sampler_state *sampler = svga->polygon_stipple.sampler;
assert(sampler);
@ -475,6 +521,7 @@ update_samplers(struct svga_context *svga, uint64_t dirty )
svga->state.hw_draw.samplers[PIPE_SHADER_FRAGMENT][unit] =
sampler->id[0];
}
svga->state.hw_draw.num_samplers[PIPE_SHADER_FRAGMENT]++;
}
return ret;
@ -488,3 +535,180 @@ struct svga_tracked_state svga_hw_sampler = {
SVGA_NEW_STIPPLE),
update_samplers
};
static enum pipe_error
update_cs_sampler_resources(struct svga_context *svga, uint64_t dirty)
{
enum pipe_error ret = PIPE_OK;
enum pipe_shader_type shader = PIPE_SHADER_COMPUTE;
assert(svga_have_sm5(svga));
SVGA3dShaderResourceViewId ids[PIPE_MAX_SAMPLERS];
struct svga_winsys_surface *surfaces[PIPE_MAX_SAMPLERS];
struct pipe_sampler_view *sampler_views[PIPE_MAX_SAMPLERS];
unsigned count;
unsigned nviews;
unsigned i;
count = svga->curr.num_sampler_views[shader];
for (i = 0; i < count; i++) {
struct svga_pipe_sampler_view *sv =
svga_pipe_sampler_view(svga->curr.sampler_views[shader][i]);
if (sv) {
surfaces[i] = svga_resource_handle(sv->base.texture);
ret = svga_validate_pipe_sampler_view(svga, sv);
if (ret != PIPE_OK)
return ret;
assert(sv->id != SVGA3D_INVALID_ID);
ids[i] = sv->id;
sampler_views[i] = &sv->base;
}
else {
surfaces[i] = NULL;
ids[i] = SVGA3D_INVALID_ID;
sampler_views[i] = NULL;
}
}
for (; i < svga->state.hw_draw.num_sampler_views[shader]; i++) {
ids[i] = SVGA3D_INVALID_ID;
surfaces[i] = NULL;
sampler_views[i] = NULL;
}
/* Number of ShaderResources that need to be modified. This includes
* the one that need to be unbound.
*/
nviews = MAX2(svga->state.hw_draw.num_sampler_views[shader], count);
if (nviews > 0) {
if (count != svga->state.hw_draw.num_sampler_views[shader] ||
memcmp(sampler_views, svga->state.hw_draw.sampler_views[shader],
count * sizeof(sampler_views[0])) != 0) {
SVGA3dShaderResourceViewId *pIds = ids;
struct svga_winsys_surface **pSurf = surfaces;
unsigned numSR = 0;
/* Loop through the sampler view list to only emit the sampler views
* that are not already in the corresponding entries in the device's
* shader resource list.
*/
for (i = 0; i < nviews; i++) {
boolean emit;
emit = sampler_views[i] ==
svga->state.hw_draw.sampler_views[shader][i];
if (!emit && i == nviews - 1) {
/* Include the last sampler view in the next emit
* if it is different.
*/
emit = TRUE;
numSR++;
i++;
}
if (emit) {
/* numSR can only be 0 if the first entry of the list
* is the same as the one in the device list.
* In this case, * there is nothing to send yet.
*/
if (numSR) {
ret = SVGA3D_vgpu10_SetShaderResources(svga->swc,
svga_shader_type(shader),
i - numSR, /* startView */
numSR,
pIds,
pSurf);
if (ret != PIPE_OK)
return ret;
}
pIds += (numSR + 1);
pSurf += (numSR + 1);
numSR = 0;
}
else
numSR++;
}
/* Save referenced sampler views in the hw draw state. */
svga->state.hw_draw.num_sampler_views[shader] = count;
for (i = 0; i < nviews; i++) {
pipe_sampler_view_reference(
&svga->state.hw_draw.sampler_views[shader][i],
sampler_views[i]);
}
}
}
return ret;
}
struct svga_tracked_state svga_hw_cs_sampler_bindings = {
"cs shader resources emit",
SVGA_NEW_TEXTURE_BINDING,
update_cs_sampler_resources
};
static enum pipe_error
update_cs_samplers(struct svga_context *svga, uint64_t dirty )
{
enum pipe_error ret = PIPE_OK;
enum pipe_shader_type shader = PIPE_SHADER_COMPUTE;
assert(svga_have_sm5(svga));
const unsigned count = svga->curr.num_samplers[shader];
SVGA3dSamplerId ids[PIPE_MAX_SAMPLERS];
unsigned i;
unsigned nsamplers;
for (i = 0; i < count; i++) {
if (svga->curr.sampler[shader][i]) {
ids[i] = svga->curr.sampler[shader][i]->id[0];
assert(ids[i] != SVGA3D_INVALID_ID);
}
else {
ids[i] = SVGA3D_INVALID_ID;
}
}
for (; i < svga->state.hw_draw.num_samplers[shader]; i++) {
ids[i] = SVGA3D_INVALID_ID;
}
nsamplers = MAX2(svga->state.hw_draw.num_samplers[shader], count);
if (nsamplers > 0) {
if (count != svga->state.hw_draw.num_samplers[shader] ||
memcmp(ids, svga->state.hw_draw.samplers[shader],
count * sizeof(ids[0])) != 0) {
/* HW state is really changing */
ret = SVGA3D_vgpu10_SetSamplers(svga->swc,
nsamplers,
0, /* start */
svga_shader_type(shader), /* type */
ids);
if (ret != PIPE_OK)
return ret;
memcpy(svga->state.hw_draw.samplers[shader], ids,
nsamplers * sizeof(ids[0]));
svga->state.hw_draw.num_samplers[shader] = count;
}
}
return ret;
}
struct svga_tracked_state svga_hw_cs_sampler = {
"texture cs sampler emit",
(SVGA_NEW_CS |
SVGA_NEW_SAMPLER),
update_cs_samplers
};

11
src/gallium/drivers/svga/svga_state_ts.c
View file

@ -104,6 +104,9 @@ make_tcs_key(struct svga_context *svga, struct svga_compile_key *key)
/* tcs is always followed by tes */
key->last_vertex_stage = 0;
if (svga_have_gl43(svga))
key->image_size_used = tcs->base.info.opcode_count[TGSI_OPCODE_RESQ] ? 1 : 0;
}
@ -178,7 +181,8 @@ struct svga_tracked_state svga_hw_tcs =
SVGA_NEW_TES |
SVGA_NEW_TEXTURE_BINDING |
SVGA_NEW_SAMPLER |
SVGA_NEW_RAST),
SVGA_NEW_RAST |
SVGA_NEW_TCS_RAW_BUFFER),
emit_hw_tcs
};
@ -276,6 +280,8 @@ make_tes_key(struct svga_context *svga, struct svga_compile_key *key)
}
}
if (svga_have_gl43(svga))
key->image_size_used = tes->base.info.opcode_count[TGSI_OPCODE_RESQ] ? 1 : 0;
}
@ -411,6 +417,7 @@ struct svga_tracked_state svga_hw_tes =
SVGA_NEW_TES |
SVGA_NEW_TEXTURE_BINDING |
SVGA_NEW_SAMPLER |
SVGA_NEW_RAST),
SVGA_NEW_RAST |
SVGA_NEW_TES_RAW_BUFFER),
emit_hw_tes
};

6
src/gallium/drivers/svga/svga_state_vs.c
View file

@ -214,6 +214,9 @@ make_vs_key(struct svga_context *svga, struct svga_compile_key *key)
*/
key->last_vertex_stage = !(svga->curr.gs ||
svga->curr.tcs || svga->curr.tes);
if (svga_have_gl43(svga))
key->image_size_used = vs->base.info.opcode_count[TGSI_OPCODE_RESQ] ? 1 : 0;
}
@ -434,6 +437,7 @@ struct svga_tracked_state svga_hw_vs =
SVGA_NEW_RAST |
SVGA_NEW_PRESCALE |
SVGA_NEW_VELEMENT |
SVGA_NEW_NEED_SWTNL),
SVGA_NEW_NEED_SWTNL |
SVGA_NEW_VS_RAW_BUFFER),
emit_hw_vs
};

74
src/gallium/drivers/svga/svga_surface.c
View file

@ -194,7 +194,7 @@ svga_texture_view_surface(struct svga_context *svga,
{
struct svga_screen *ss = svga_screen(svga->pipe.screen);
struct svga_winsys_surface *handle = NULL;
boolean validated;
boolean invalidated;
boolean needCopyResource;
SVGA_DBG(DEBUG_PERF,
@ -241,7 +241,7 @@ svga_texture_view_surface(struct svga_context *svga,
} else {
SVGA_DBG(DEBUG_DMA, "surface_create for texture view\n");
handle = svga_screen_surface_create(ss, bind_flags, PIPE_USAGE_DEFAULT,
&validated, key);
&invalidated, key);
needCopyResource = TRUE;
if (cacheable && !tex->backed_handle) {
@ -551,7 +551,7 @@ svga_validate_surface_view(struct svga_context *svga, struct svga_surface *s)
* associated resource. We will then use the cloned surface view for
* render target.
*/
for (shader = PIPE_SHADER_VERTEX; shader <= PIPE_SHADER_TESS_EVAL; shader++) {
for (shader = PIPE_SHADER_VERTEX; shader <= PIPE_SHADER_COMPUTE; shader++) {
if (svga_check_sampler_view_resource_collision(svga, s->handle, shader)) {
SVGA_DBG(DEBUG_VIEWS,
"same resource used in shaderResource and renderTarget 0x%x\n",
@ -582,7 +582,7 @@ svga_validate_surface_view(struct svga_context *svga, struct svga_surface *s)
SVGA3dRenderTargetViewDesc desc;
struct svga_texture *stex = svga_texture(s->base.texture);
if (stex->validated == FALSE) {
if (stex->surface_state < SVGA_SURFACE_STATE_INVALIDATED) {
assert(stex->handle);
/* We are about to render into a surface that has not been validated.
@ -591,7 +591,7 @@ svga_validate_surface_view(struct svga_context *svga, struct svga_surface *s)
* content when the associated mob is first bound to the surface.
*/
SVGA_RETRY(svga, SVGA3D_InvalidateGBSurface(svga->swc, stex->handle));
stex->validated = TRUE;
stex->surface_state = SVGA_SURFACE_STATE_INVALIDATED;
}
desc.tex.mipSlice = s->real_level;
@ -599,38 +599,48 @@ svga_validate_surface_view(struct svga_context *svga, struct svga_surface *s)
desc.tex.arraySize =
s->base.u.tex.last_layer - s->base.u.tex.first_layer + 1;
s->view_id = util_bitmask_add(svga->surface_view_id_bm);
resType = svga_resource_type(s->base.texture->target);
if (util_format_is_depth_or_stencil(s->base.format)) {
ret = SVGA3D_vgpu10_DefineDepthStencilView(svga->swc,
s->view_id,
s->handle,
s->key.format,
resType,
&desc);
/* Create depth stencil view only if the resource is created
* with depth stencil bind flag.
*/
if (stex->key.flags & SVGA3D_SURFACE_BIND_DEPTH_STENCIL) {
s->view_id = util_bitmask_add(svga->surface_view_id_bm);
ret = SVGA3D_vgpu10_DefineDepthStencilView(svga->swc,
s->view_id,
s->handle,
s->key.format,
resType,
&desc);
}
}
else {
SVGA3dSurfaceFormat view_format = s->key.format;
const struct svga_texture *stex = svga_texture(s->base.texture);
/* Can't create RGBA render target view of a RGBX surface so adjust
* the view format. We do something similar for texture samplers in
* svga_validate_pipe_sampler_view().
/* Create render target view only if the resource is created
* with render target bind flag.
*/
if (view_format == SVGA3D_B8G8R8A8_UNORM &&
(stex->key.format == SVGA3D_B8G8R8X8_UNORM ||
stex->key.format == SVGA3D_B8G8R8X8_TYPELESS)) {
view_format = SVGA3D_B8G8R8X8_UNORM;
}
if (stex->key.flags & SVGA3D_SURFACE_BIND_RENDER_TARGET) {
SVGA3dSurfaceFormat view_format = s->key.format;
ret = SVGA3D_vgpu10_DefineRenderTargetView(svga->swc,
s->view_id,
s->handle,
view_format,
resType,
&desc);
/* Can't create RGBA render target view of a RGBX surface so adjust
* the view format. We do something similar for texture samplers in
* svga_validate_pipe_sampler_view().
*/
if (view_format == SVGA3D_B8G8R8A8_UNORM &&
(stex->key.format == SVGA3D_B8G8R8X8_UNORM ||
stex->key.format == SVGA3D_B8G8R8X8_TYPELESS)) {
view_format = SVGA3D_B8G8R8X8_UNORM;
}
s->view_id = util_bitmask_add(svga->surface_view_id_bm);
ret = SVGA3D_vgpu10_DefineRenderTargetView(svga->swc,
s->view_id,
s->handle,
view_format,
resType,
&desc);
}
}
if (ret != PIPE_OK) {
@ -669,7 +679,9 @@ svga_surface_destroy(struct pipe_context *pipe,
*/
if (s->handle != t->handle && s->handle != t->backed_handle) {
SVGA_DBG(DEBUG_DMA, "unref sid %p (tex surface)\n", s->handle);
svga_screen_surface_destroy(ss, &s->key, &s->handle);
svga_screen_surface_destroy(ss, &s->key,
svga_was_texture_rendered_to(t),
&s->handle);
}
if (s->view_id != SVGA3D_INVALID_ID) {

92
src/gallium/drivers/svga/svga_tgsi_insn.c
View file

@ -1344,11 +1344,12 @@ emit_ssg(struct svga_shader_emitter *emit,
/**
* Translate/emit KILL_IF instruction (kill if any of X,Y,Z,W are negative).
* Translate/emit the conditional discard instruction (discard if
* any of X,Y,Z,W are negative).
*/
static boolean
emit_kill_if(struct svga_shader_emitter *emit,
const struct tgsi_full_instruction *insn)
emit_cond_discard(struct svga_shader_emitter *emit,
const struct tgsi_full_instruction *insn)
{
const struct tgsi_full_src_register *reg = &insn->Src[0];
struct src_register src0, srcIn;
@ -1375,7 +1376,7 @@ emit_kill_if(struct svga_shader_emitter *emit,
src0 = src( temp );
}
/* Do the texkill by checking if any of the XYZW components are < 0.
/* Do the discard by checking if any of the XYZW components are < 0.
* Note that ps_2_0 and later take XYZW in consideration, while ps_1_x
* only used XYZ. The MSDN documentation about this is incorrect.
*/
@ -1387,12 +1388,12 @@ emit_kill_if(struct svga_shader_emitter *emit,
/**
* Translate/emit unconditional kill instruction (usually found inside
* Translate/emit the unconditional discard instruction (usually found inside
* an IF/ELSE/ENDIF block).
*/
static boolean
emit_kill(struct svga_shader_emitter *emit,
const struct tgsi_full_instruction *insn)
emit_discard(struct svga_shader_emitter *emit,
const struct tgsi_full_instruction *insn)
{
SVGA3dShaderDestToken temp;
struct src_register one = get_one_immediate(emit);
@ -2043,6 +2044,73 @@ emit_mov(struct svga_shader_emitter *emit,
}
/**
* Translate TGSI SQRT instruction
* if src1 == 0
* mov dst, src1
* else
* rsq temp, src1
* rcp dst, temp
* endif
*/
static boolean
emit_sqrt(struct svga_shader_emitter *emit,
const struct tgsi_full_instruction *insn)
{
const struct src_register src1 = translate_src_register(emit, &insn->Src[0]);
const struct src_register zero = get_zero_immediate(emit);
SVGA3dShaderDestToken dst = translate_dst_register(emit, insn, 0);
SVGA3dShaderDestToken temp = get_temp(emit);
SVGA3dShaderInstToken if_token = inst_token(SVGA3DOP_IFC);
boolean ret = TRUE;
if_token.control = SVGA3DOPCOMP_EQ;
if (!(emit_instruction(emit, if_token) &&
emit_src(emit, src1) &&
emit_src(emit, zero))) {
ret = FALSE;
goto cleanup;
}
if (!submit_op1(emit,
inst_token(SVGA3DOP_MOV),
dst, src1)) {
ret = FALSE;
goto cleanup;
}
if (!emit_instruction(emit, inst_token(SVGA3DOP_ELSE))) {
ret = FALSE;
goto cleanup;
}
if (!submit_op1(emit,
inst_token(SVGA3DOP_RSQ),
temp, src1)) {
ret = FALSE;
goto cleanup;
}
if (!submit_op1(emit,
inst_token(SVGA3DOP_RCP),
dst, src(temp))) {
ret = FALSE;
goto cleanup;
}
if (!emit_instruction(emit, inst_token(SVGA3DOP_ENDIF))) {
ret = FALSE;
goto cleanup;
}
cleanup:
release_temp(emit, temp);
return ret;
}
/**
* Translate/emit TGSI DDX, DDY instructions.
*/
@ -2820,7 +2888,7 @@ svga_emit_instruction(struct svga_shader_emitter *emit,
return emit_end( emit );
case TGSI_OPCODE_KILL_IF:
return emit_kill_if( emit, insn );
return emit_cond_discard( emit, insn );
/* Selection opcodes. The underlying language is fairly
* non-orthogonal about these.
@ -2902,7 +2970,7 @@ svga_emit_instruction(struct svga_shader_emitter *emit,
return emit_brk( emit, insn );
case TGSI_OPCODE_KILL:
return emit_kill( emit, insn );
return emit_discard( emit, insn );
case TGSI_OPCODE_DST:
return emit_dst_insn( emit, insn );
@ -2919,6 +2987,9 @@ svga_emit_instruction(struct svga_shader_emitter *emit,
case TGSI_OPCODE_MOV:
return emit_mov( emit, insn );
case TGSI_OPCODE_SQRT:
return emit_sqrt( emit, insn );
default:
{
SVGA3dShaderOpCodeType opcode =
@ -3517,7 +3588,8 @@ needs_to_create_common_immediate(const struct svga_shader_emitter *emit)
emit->info.opcode_count[TGSI_OPCODE_SEQ] >= 1 ||
emit->info.opcode_count[TGSI_OPCODE_EXP] >= 1 ||
emit->info.opcode_count[TGSI_OPCODE_LOG] >= 1 ||
emit->info.opcode_count[TGSI_OPCODE_KILL] >= 1)
emit->info.opcode_count[TGSI_OPCODE_KILL] >= 1 ||
emit->info.opcode_count[TGSI_OPCODE_SQRT] >= 1)
return TRUE;
return FALSE;

9
src/gallium/drivers/svga/svga_tgsi_vgpu10.c
View file

@ -5915,6 +5915,10 @@ emit_constant_declaration(struct svga_shader_emitter_v10 *emit)
}
}
}
if (emit->key.image_size_used) {
emit->image_size_index = total_consts;
total_consts += emit->num_images;
}
if (total_consts > 0) {
if (total_consts > VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT) {
@ -10733,9 +10737,6 @@ emit_instruction(struct svga_shader_emitter_v10 *emit,
{
const enum tgsi_opcode opcode = inst->Instruction.Opcode;
if (emit->skip_instruction)
return TRUE;
switch (opcode) {
case TGSI_OPCODE_ADD:
case TGSI_OPCODE_AND:
@ -12802,6 +12803,8 @@ svga_tgsi_vgpu10_translate(struct svga_context *svga,
emit->current_loop_depth = 0;
emit->initialize_temp_index = INVALID_INDEX;
emit->image_size_index = INVALID_INDEX;
emit->max_vs_inputs = svgascreen->max_vs_inputs;
emit->max_vs_outputs = svgascreen->max_vs_outputs;
emit->max_gs_inputs = svgascreen->max_gs_inputs;

20
src/gallium/drivers/svga/svga_winsys.h
View file

@ -109,6 +109,7 @@ enum svga_stats_count {
SVGA_STATS_COUNT_BLITBLITTERCOPY,
SVGA_STATS_COUNT_DEPTHSTENCILSTATE,
SVGA_STATS_COUNT_RASTERIZERSTATE,
SVGA_STATS_COUNT_RAWBUFFERSRVIEW,
SVGA_STATS_COUNT_SAMPLER,
SVGA_STATS_COUNT_SAMPLERVIEW,
SVGA_STATS_COUNT_SURFACEWRITEFLUSH,
@ -131,6 +132,7 @@ enum svga_stats_time {
SVGA_STATS_TIME_CREATEBACKEDSURFACEVIEW,
SVGA_STATS_TIME_CREATEBUFFER,
SVGA_STATS_TIME_CREATECONTEXT,
SVGA_STATS_TIME_CREATECS,
SVGA_STATS_TIME_CREATEFS,
SVGA_STATS_TIME_CREATEGS,
SVGA_STATS_TIME_CREATESURFACE,
@ -144,8 +146,10 @@ enum svga_stats_time {
SVGA_STATS_TIME_DRAWVBO,
SVGA_STATS_TIME_DRAWARRAYS,
SVGA_STATS_TIME_DRAWELEMENTS,
SVGA_STATS_TIME_EMITCS,
SVGA_STATS_TIME_EMITFS,
SVGA_STATS_TIME_EMITGS,
SVGA_STATS_TIME_EMITRAWBUFFER,
SVGA_STATS_TIME_EMITTCS,
SVGA_STATS_TIME_EMITTES,
SVGA_STATS_TIME_EMITVS,
@ -156,6 +160,7 @@ enum svga_stats_time {
SVGA_STATS_TIME_HWTNLDRAWELEMENTS,
SVGA_STATS_TIME_HWTNLFLUSH,
SVGA_STATS_TIME_HWTNLPRIM,
SVGA_STATS_TIME_LAUNCHGRID,
SVGA_STATS_TIME_PROPAGATESURFACE,
SVGA_STATS_TIME_SETSAMPLERVIEWS,
SVGA_STATS_TIME_SURFACEFLUSH,
@ -166,7 +171,9 @@ enum svga_stats_time {
SVGA_STATS_TIME_TEXTRANSFERUNMAP,
SVGA_STATS_TIME_TGSIVGPU10TRANSLATE,
SVGA_STATS_TIME_TGSIVGPU9TRANSLATE,
SVGA_STATS_TIME_UPDATECSUAV,
SVGA_STATS_TIME_UPDATESTATE,
SVGA_STATS_TIME_UPDATEUAV,
SVGA_STATS_TIME_VALIDATESURFACEVIEW,
SVGA_STATS_TIME_VBUFDRAWARRAYS,
SVGA_STATS_TIME_VBUFDRAWELEMENTS,
@ -184,6 +191,7 @@ enum svga_stats_time {
SVGA_STATS_PREFIX "BlitBlitterCopy", \
SVGA_STATS_PREFIX "DepthStencilState", \
SVGA_STATS_PREFIX "RasterizerState", \
SVGA_STATS_PREFIX "RawBufferSRView", \
SVGA_STATS_PREFIX "Sampler", \
SVGA_STATS_PREFIX "SamplerView", \
SVGA_STATS_PREFIX "SurfaceWriteFlush", \
@ -204,6 +212,7 @@ enum svga_stats_time {
SVGA_STATS_PREFIX "CreateBackedSurfaceView", \
SVGA_STATS_PREFIX "CreateBuffer", \
SVGA_STATS_PREFIX "CreateContext", \
SVGA_STATS_PREFIX "CreateCS", \
SVGA_STATS_PREFIX "CreateFS", \
SVGA_STATS_PREFIX "CreateGS", \
SVGA_STATS_PREFIX "CreateSurface", \
@ -217,8 +226,10 @@ enum svga_stats_time {
SVGA_STATS_PREFIX "DrawVBO", \
SVGA_STATS_PREFIX "DrawArrays", \
SVGA_STATS_PREFIX "DrawElements", \
SVGA_STATS_PREFIX "EmitCS", \
SVGA_STATS_PREFIX "EmitFS", \
SVGA_STATS_PREFIX "EmitGS", \
SVGA_STATS_PREFIX "EmitRawBuffer", \
SVGA_STATS_PREFIX "EmitTCS", \
SVGA_STATS_PREFIX "EmitTES", \
SVGA_STATS_PREFIX "EmitVS", \
@ -229,6 +240,7 @@ enum svga_stats_time {
SVGA_STATS_PREFIX "HWtnlDrawElements", \
SVGA_STATS_PREFIX "HWtnlFlush", \
SVGA_STATS_PREFIX "HWtnlPrim", \
SVGA_STATS_PREFIX "LaunchGrid", \
SVGA_STATS_PREFIX "PropagateSurface", \
SVGA_STATS_PREFIX "SetSamplerViews", \
SVGA_STATS_PREFIX "SurfaceFlush", \
@ -239,7 +251,9 @@ enum svga_stats_time {
SVGA_STATS_PREFIX "TextureTransferUnmap", \
SVGA_STATS_PREFIX "TGSIVGPU10Translate", \
SVGA_STATS_PREFIX "TGSIVGPU9Translate", \
SVGA_STATS_PREFIX "UpdateCSUAV", \
SVGA_STATS_PREFIX "UpdateState", \
SVGA_STATS_PREFIX "UpdateUAV", \
SVGA_STATS_PREFIX "ValidateSurfaceView", \
SVGA_STATS_PREFIX "VbufDrawArrays", \
SVGA_STATS_PREFIX "VbufDrawElements", \
@ -803,6 +817,12 @@ struct svga_winsys_screen
boolean have_fence_fd;
boolean have_intra_surface_copy;
boolean have_constant_buffer_offset_cmd;
boolean have_index_vertex_buffer_offset_cmd;
/* Have rasterizer state v2 command support */
boolean have_rasterizer_state_v2_cmd;
/** Have GL43 capable device */
boolean have_gl43;
};

7
src/gallium/winsys/svga/drm/vmw_screen.c
View file

@ -158,7 +158,12 @@ vmw_winsys_create( int fd )
vws->base.have_gb_dma = !vws->force_coherent;
vws->base.need_to_rebind_resources = FALSE;
vws->base.have_transfer_from_buffer_cmd = vws->base.have_vgpu10;
vws->base.have_constant_buffer_offset_cmd = FALSE;
vws->base.have_constant_buffer_offset_cmd =
vws->ioctl.have_drm_2_20 && vws->base.have_sm5;
vws->base.have_index_vertex_buffer_offset_cmd = FALSE;
vws->base.have_rasterizer_state_v2_cmd =
vws->ioctl.have_drm_2_20 && vws->base.have_sm5;
getenv_val = getenv("SVGA_FORCE_KERNEL_UNMAPS");
vws->cache_maps = !getenv_val || strcmp(getenv_val, "0") == 0;
vws->fence_ops = vmw_fence_ops_create(vws);