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pan/va/disasm: Print 64 bit src/dest regs as reg pairs
This makes it clear that both registers are read/written, and aligns with DDK disassembly. For example: STORE.i128.istream.slot2.reconverge @r0:r1:r2:r3, r4^, offset:0 vs STORE.i128.istream.slot2.reconverge @r0:r1:r2:r3, [r4^:r5^], offset:0 Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com> Reviewed-by: Eric R. Smith <eric.smith@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41062>
This commit is contained in:
Lars-Ivar Hesselberg Simonsen
Marge Bot
parent
9f049032be
commit
829eafa076
4 changed files with 76 additions and 38 deletions
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@ -76,7 +76,24 @@ def parse_int(s, minimum, maximum):
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return number
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def encode_source(op, fau):
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if op[0] == 'r':
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# Reg tuple
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if op[0] == '[' and op[-1:] == ']':
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# Remove brackets and split on ":"
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unpacked = op[1:-1].split(":")
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die_if(len(unpacked) != 2, 'Invalid tuple')
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die_if(unpacked[0][0] != 'r', 'Invalid tuple')
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die_if(unpacked[1][0] != 'r', 'Invalid tuple')
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if (unpacked[0][-1:] == '^'):
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val0 = parse_int(unpacked[0][1:-1], 0, 63)
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val1 = parse_int(unpacked[1][1:-1], 0, 63)
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die_if(val1 != val0 + 1, 'Invalid tuple value')
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return val0 | 0x40
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else:
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val0 = parse_int(unpacked[0][1:], 0, 63)
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val1 = parse_int(unpacked[1][1:], 0, 63)
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die_if(val1 != val0 + 1, 'Invalid tuple value')
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return val0
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elif op[0] == 'r':
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if (op[-1:] == '^'):
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return parse_int(op[1:-1], 0, 63) | 0x40
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return parse_int(op[1:], 0, 63)
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@ -105,10 +122,27 @@ def encode_source(op, fau):
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def encode_dest(op):
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die_if(op[0] != 'r', f"Expected register destination {op}")
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# Reg tuple
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if op[0] == '[' and op[-1:] == ']':
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# Remove brackets and split on ":"
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unpacked = op[1:-1].split(":")
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die_if(len(unpacked) != 2, 'Invalid tuple')
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die_if(unpacked[0][0] != 'r', 'Invalid tuple')
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die_if(unpacked[1][0] != 'r', 'Invalid tuple')
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parts = op.split(".")
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reg = parts[0]
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parts = unpacked[0].split(".")
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reg = parts[0]
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value = parse_int(reg[1:], 0, 63)
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parts1 = unpacked[1].split(".")
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reg1 = parts1[0]
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val1 = parse_int(reg1[1:], 0, 63)
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die_if(val1 != value + 1, 'Invalid tuple value')
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else:
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die_if(op[0] != 'r', f"Expected register destination {op}")
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parts = op.split(".")
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reg = parts[0]
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value = parse_int(reg[1:], 0, 63)
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# Default to writing in full
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wrmask = 0x3
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@ -120,7 +154,7 @@ def encode_dest(op):
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die_if(mask not in WMASKS, "Expected a write mask")
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wrmask = 1 << WMASKS.index(mask)
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return parse_int(reg[1:], 0, 63) | (wrmask << 6)
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return value | (wrmask << 6)
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def parse_asm(line):
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global LINE
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@ -43,7 +43,7 @@ static const uint32_t va_immediates[32] = {
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};
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static inline void
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va_print_src(FILE *fp, unsigned type, unsigned value, unsigned fau_page)
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va_print_src(FILE *fp, unsigned type, unsigned value, unsigned size, unsigned fau_page)
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{
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if (type == VA_SRC_IMM_TYPE) {
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if (value >= 32) {
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@ -64,18 +64,22 @@ va_print_src(FILE *fp, unsigned type, unsigned value, unsigned fau_page)
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fprintf(fp, "u%u", value | (fau_page << 6));
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} else {
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bool discard = (type & 1);
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fprintf(fp, "r%u%s", value, discard ? "^" : "");
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char *dmark = discard ? "^" : "";
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if (size > 32)
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fprintf(fp, "[r%u%s:r%u%s]", value, dmark, value + 1, dmark);
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else
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fprintf(fp, "r%u%s", value, dmark);
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}
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}
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static inline void
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va_print_float_src(FILE *fp, unsigned type, unsigned value, unsigned fau_page, bool neg, bool abs)
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va_print_float_src(FILE *fp, unsigned type, unsigned value, unsigned size, unsigned fau_page, bool neg, bool abs)
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{
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if (type == VA_SRC_IMM_TYPE) {
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assert(value < 32 && "overflow in LUT");
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fprintf(fp, "0x%X", va_immediates[value]);
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} else {
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va_print_src(fp, type, value, fau_page);
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va_print_src(fp, type, value, size, fau_page);
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}
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if (neg)
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@ -86,13 +90,12 @@ va_print_float_src(FILE *fp, unsigned type, unsigned value, unsigned fau_page, b
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}
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static inline void
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va_print_dest(FILE *fp, unsigned mask, unsigned value, bool can_mask)
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va_print_dest(FILE *fp, unsigned mask, unsigned value, unsigned size)
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{
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fprintf(fp, "r%u", value);
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/* Should write at least one component */
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// assert(mask != 0);
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// assert(mask == 0x3 || can_mask);
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if (size > 32)
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fprintf(fp, "[r%u:r%u]", value, value + 1);
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else
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fprintf(fp, "r%u", value);
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if (mask != 0x3)
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fprintf(fp, ".h%u", (mask == 1) ? 0 : 1);
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@ -113,7 +116,7 @@ va_print_dest(FILE *fp, unsigned mask, unsigned value, bool can_mask)
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fprintf(fp, "%s ", valhall_flow[(instr >> ${op.offset['flow']}) & ${hex(op.mask['flow'])}]);
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% for i, dest in enumerate(op.dests):
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<% no_comma = False %>
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va_print_dest(fp, (instr >> ${dest.offset['mode']}) & ${hex(dest.mask['mode'])}, (instr >> ${dest.offset['value']}) & ${hex(dest.mask['value'])}, true);
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va_print_dest(fp, (instr >> ${dest.offset['mode']}) & ${hex(dest.mask['mode'])}, (instr >> ${dest.offset['value']}) & ${hex(dest.mask['value'])}, ${dest.size});
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% endfor
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% for index, sr in enumerate(op.staging):
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% if not no_comma:
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@ -145,15 +148,15 @@ va_print_dest(FILE *fp, unsigned mask, unsigned value, bool can_mask)
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<% no_comma = False %>
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% if src.absneg:
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va_print_float_src(fp, (instr >> ${src.offset['mode']}) & ${hex(src.mask['mode'])}, (instr >> ${src.offset['value']}) & ${hex(src.mask['value'])},
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(instr >> ${op.offset['fau_page']}) & ${hex(op.mask['fau_page'])},
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${src.size}, (instr >> ${op.offset['fau_page']}) & ${hex(op.mask['fau_page'])},
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instr & BIT(${src.offset['neg']}),
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instr & BIT(${src.offset['abs']}));
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% elif src.is_float:
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va_print_float_src(fp, (instr >> ${src.offset['mode']}) & ${src.mask['mode']}, (instr >> ${src.offset['value']}) & ${hex(src.mask['value'])},
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(instr >> ${op.offset['fau_page']}) & ${hex(op.mask['fau_page'])}, false, false);
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${src.size}, (instr >> ${op.offset['fau_page']}) & ${hex(op.mask['fau_page'])}, false, false);
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% else:
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va_print_src(fp, (instr >> ${src.offset['mode']}) & ${src.mask['mode']}, (instr >> ${src.offset['value']}) & ${hex(src.mask['value'])},
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(instr >> ${op.offset['fau_page']}) & ${hex(op.mask['fau_page'])});
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${src.size}, (instr >> ${op.offset['fau_page']}) & ${hex(op.mask['fau_page'])});
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% endif
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% if src.swizzle:
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% if src.size == 32:
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@ -25,13 +25,13 @@ e6 00 00 00 00 c1 91 06 MOV.i32 r1, core_id.w0
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01 02 00 0c 70 c0 a0 00 IADD.u32 r0, r1.b3, r2.h1
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01 c9 00 18 00 c0 a0 00 IADD.u32 r0, r1, 0x7060504.b2
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01 02 00 08 20 c0 a1 00 IADD.v2u16 r0, r1, r2
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82 3c 27 20 00 c0 a3 01 SHADDX.u64 r0, u2, r60.w0, shift:0x2
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40 00 00 18 82 80 60 08 LOAD.i32.unsigned.slot0.wait0 @r0, r0^, offset:0
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80 7c 47 20 00 c0 a3 01 SHADDX.u64 r0, u0, r60^.w0, shift:0x4
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40 00 00 38 08 44 61 78 STORE.i128.slot0.end @r4:r5:r6:r7, r0^, offset:0
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82 3c 27 20 00 c0 a3 01 SHADDX.u64 [r0:r1], u2, [r60:r61].w0, shift:0x2
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40 00 00 18 82 80 60 08 LOAD.i32.unsigned.slot0.wait0 @r0, [r0^:r1^], offset:0
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80 7c 47 20 00 c0 a3 01 SHADDX.u64 [r0:r1], u0, [r60^:r61^].w0, shift:0x4
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40 00 00 38 08 44 61 78 STORE.i128.slot0.end @r4:r5:r6:r7, [r0^:r1^], offset:0
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00 00 00 00 00 c0 00 78 NOP.end
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40 c4 c0 9c 01 c1 f0 00 ICMP_OR.u32.gt.m1 r1, r0^, 0x1000000.b3, 0x0
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42 00 00 18 02 40 61 50 STORE.i32.slot0.reconverge @r0, r2^, offset:0
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42 00 00 18 02 40 61 50 STORE.i32.slot0.reconverge @r0, [r2^:r3^], offset:0
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00 c9 8f 12 30 c0 a0 00 CLPER.i32.f1 r0, r0, 0x7060504.b00
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00 00 00 30 00 c7 90 00 S8_TO_S32 r7, r0.b3
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00 00 00 20 00 c6 90 00 S8_TO_S32 r6, r0.b2
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@ -55,8 +55,8 @@ f0 00 3c 33 04 40 7f 78 BLEND.slot0.v4.f16.end @r0:r1, blend_descriptor_0.w0,
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00 dd c0 08 14 c2 b2 00 FMA.f32 r2, r0, 0x44000000.neg.h1, 0x0.neg
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41 88 c0 00 04 c1 b2 00 FMA.f32 r1, r1^, u8, 0x0.neg
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40 88 c0 00 04 c0 b2 10 FMA.f32.wait1 r0, r0^, u8, 0x0.neg
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44 00 00 32 06 40 61 78 STORE.i96.estream.slot0.end @r0:r1:r2, r4^, offset:0
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44 00 00 39 08 48 61 78 STORE.i128.istream.slot0.end @r8:r9:r10:r11, r4^, offset:0
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44 00 00 32 06 40 61 78 STORE.i96.estream.slot0.end @r0:r1:r2, [r4^:r5^], offset:0
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44 00 00 39 08 48 61 78 STORE.i128.istream.slot0.end @r8:r9:r10:r11, [r4^:r5^], offset:0
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00 00 00 c0 01 c0 45 48 BARRIER.slot7.wait
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80 00 00 00 82 82 60 00 LOAD.i8.unsigned.slot0 @r2, u0, offset:0
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80 00 00 08 82 82 60 00 LOAD.i16.unsigned.slot0 @r2, u0, offset:0
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@ -97,18 +97,18 @@ f0 00 3c 33 04 40 7f 78 BLEND.slot0.v4.f16.end @r0:r1, blend_descriptor_0.w0,
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00 03 00 00 00 c0 1f 50 BRANCHZ.reconverge r0, offset:3
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c0 00 00 00 00 c0 10 01 IADD_IMM.i32 r0, 0x0, #0x0
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c0 01 00 00 00 c4 10 51 IADD_IMM.i32.reconverge r4, 0x0, #0x1
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80 00 27 20 00 c2 a3 01 SHADDX.u64 r2, u0, r0.w0, shift:0x2
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80 00 27 20 00 c2 a3 01 SHADDX.u64 [r2:r3], u0, [r0:r1].w0, shift:0x2
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40 c9 00 10 00 c0 a0 00 IADD.u32 r0, r0^, 0x7060504.b0
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00 82 c0 80 03 c1 f0 00 ICMP_OR.u32.ne.m1 r1, r0, u2, 0x0
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04 00 00 00 00 c5 91 00 MOV.i32 r5, r4
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04 00 00 00 00 c6 91 00 MOV.i32 r6, r4
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04 00 00 00 00 c7 91 08 MOV.i32.wait0 r7, r4
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42 00 00 38 08 44 61 00 STORE.i128.slot0 @r4:r5:r6:r7, r2^, offset:0
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42 00 00 38 08 44 61 00 STORE.i128.slot0 @r4:r5:r6:r7, [r2^:r3^], offset:0
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41 f8 ff ff 07 c0 1f 50 BRANCHZ.reconverge r1^, offset:-8
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7d c0 00 08 10 bc a1 00 IADD.v2u16 r60.h1, r61^.h10, 0x0
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44 00 46 32 28 40 71 78 ST_CVT.slot0.istream.v4.f32.end @r0:r1:r2:r3, r4^, r6^, offset:0x0
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44 00 46 34 28 40 71 78 ST_CVT.slot0.istream.v4.s32.end @r0:r1:r2:r3, r4^, r6^, offset:0x0
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44 00 46 36 28 40 71 78 ST_CVT.slot0.istream.v4.u32.end @r0:r1:r2:r3, r4^, r6^, offset:0x0
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44 00 46 32 28 40 71 78 ST_CVT.slot0.istream.v4.f32.end @r0:r1:r2:r3, [r4^:r5^], r6^, offset:0x0
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44 00 46 34 28 40 71 78 ST_CVT.slot0.istream.v4.s32.end @r0:r1:r2:r3, [r4^:r5^], r6^, offset:0x0
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44 00 46 36 28 40 71 78 ST_CVT.slot0.istream.v4.u32.end @r0:r1:r2:r3, [r4^:r5^], r6^, offset:0x0
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7c c0 12 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, r60^, 0x0, table:0x2, index:0x1
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7c c0 02 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, r60^, 0x0, table:0x2, index:0x0
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82 81 00 28 f4 82 6a 00 LD_PKA.i64.unsigned.slot0 @r2:r3, u2, u1
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@ -216,10 +216,10 @@ c0 f1 00 00 10 c1 2f 08 BRANCHZI.eq.absolute.wait0 0x0, blend_descriptor_0.w1
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80 00 c0 17 34 7c 25 01 TEX_FETCH.slot0.f.32.2d @r0:r1:r2:r3, @r60:r61, u0
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80 00 00 00 00 c1 91 02 MOV.i32 r1, u64
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81 00 00 00 00 c1 91 02 MOV.i32 r1, u65
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30 00 f7 1b 02 cc 20 09 ATOM_RETURN.i32.slot0.axchg.wait0 @r55, @r12, r48, offset:0x0
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32 00 80 18 02 4c 68 08 ATOM.i32.slot0.aadd.wait0 @r12, r50, offset:0x0
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32 00 00 18 02 8c 69 08 ATOM1_RETURN.i32.slot0.ainc.wait0 @r12, r50, offset:0x0
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32 00 00 18 00 80 69 08 ATOM1_RETURN.i32.slot0.ainc.wait0 @, r50, offset:0x0
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30 00 f7 1b 02 cc 20 09 ATOM_RETURN.i32.slot0.axchg.wait0 @r55, @r12, [r48:r49], offset:0x0
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32 00 80 18 02 4c 68 08 ATOM.i32.slot0.aadd.wait0 @r12, [r50:r51], offset:0x0
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32 00 00 18 02 8c 69 08 ATOM1_RETURN.i32.slot0.ainc.wait0 @r12, [r50:r51], offset:0x0
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32 00 00 18 00 80 69 08 ATOM1_RETURN.i32.slot0.ainc.wait0 @, [r50:r51], offset:0x0
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82 00 80 15 b4 80 38 49 VAR_TEX_SINGLE.slot0.skip.sample_store.f.32.2d.zero.wait @r0:r1:r2:r3, u2, u0
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82 20 80 15 b4 80 38 09 VAR_TEX_SINGLE.slot0.skip.sample_store.f.32.2d.computed.wait0 @r0:r1:r2:r3, u2, u0
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82 20 80 1d 84 80 38 41 VAR_TEX_SINGLE.slot0.skip.sample_store.s.32.2d.computed.wait0126 @r0, u2, u0
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@ -125,9 +125,10 @@ class Source:
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self.mask['combine'] = bitmask(3)
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class Dest:
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def __init__(self, name = ""):
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def __init__(self, size, name = ""):
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self.name = name
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self.start = 40
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self.size = size
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self.offset = {}
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self.mask = {}
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@ -292,11 +293,11 @@ def build_instr(el, overrides = {}):
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else:
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i = i + 1
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dests = [Dest(dest.text or '') for dest in el.findall('dest')]
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dests = [Dest(int(tsize), dest.text or '') for dest in el.findall('dest')]
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# Get implicit ones
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sources = sources + ([Source(i, int(tsize)) for i in range(int(el.attrib.get('srcs', 0)))])
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dests = dests + ([Dest()] * int(el.attrib.get('dests', 0)))
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dests = dests + ([Dest(int(tsize))] * int(el.attrib.get('dests', 0)))
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# Get staging registers
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staging = [build_staging(i, el) for i, el in enumerate(el.findall('sr'))]
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