anv/brw: fix output tcs vertices

brw_prog_tcs_data::instances can be divided by vertices per threads on
earlier generations.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a91e0e0d61 ("brw: add support for separate tessellation shader compilation")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
(cherry picked from commit e450297ea9)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>
This commit is contained in:
Lionel Landwerlin 2025-10-23 20:27:21 +03:00 committed by Dylan Baker
parent 6a7effe059
commit 159d397437
4 changed files with 6 additions and 2 deletions

View file

@ -494,7 +494,7 @@
"description": "anv/brw: fix output tcs vertices",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "a91e0e0d616f857144c8cadfaed734ac5be8e729",
"notes": null

View file

@ -224,6 +224,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
prog_data->input_vertices = key->input_vertices;
prog_data->output_vertices = nir->info.tess.tcs_vertices_out;
prog_data->patch_count_threshold = get_patch_count_threshold(key->input_vertices);
if (compiler->use_tcs_multi_patch) {

View file

@ -1175,6 +1175,9 @@ struct brw_tcs_prog_data
/** Number of input vertices, 0 means dynamic */
unsigned input_vertices;
/** Number of output vertices */
unsigned output_vertices;
/** Should the non-SINGLE_PATCH payload provide primitive ID? */
bool include_primitive_id;

View file

@ -2550,7 +2550,7 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
SET(TESS_CONFIG, tess_config,
intel_tess_config(dyn->ts.patch_control_points,
tcs_prog_data->instances,
tcs_prog_data->output_vertices,
brw_tess_info_domain(tess_info),
tcs_prog_data->base.vue_map.num_per_patch_slots,
tcs_prog_data->base.vue_map.num_per_vertex_slots,