From 14da2444a969234b7bf306ed9824ff57d8c370b5 Mon Sep 17 00:00:00 2001
From: Danylo Piliaiev <dpiliaiev@igalia.com>
Date: Fri, 7 May 2021 12:45:47 +0300
Subject: [PATCH] turnip,freedreno/a6xx: SP_BLEND_CNTL has per-mrt blend enable
 bit

Blending in SP_BLEND_CNTL is not a binary flag but the same
mask as in RB_BLEND_CNTL. It is a per-mrt enable bit for blending.

Example SP_BLEND_CNTL produced by blob on a630 and different MRT
blendings:
  SP_BLEND_CNTL: { UNK8 | 0x6 }
  SP_BLEND_CNTL: { ENABLED | UNK8 | 0xe }
(Decoded before this commit)

Fixes mis-rendering with D3D11 game "Spelunky 2".

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10682>
---
 src/freedreno/registers/adreno/a6xx.xml        | 3 ++-
 src/freedreno/vulkan/tu_pipeline.c             | 2 +-
 src/gallium/drivers/freedreno/a6xx/fd6_blend.c | 4 ++--
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 5643c5e20a4..15a1b8f2e36 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -2987,7 +2987,8 @@ to upconvert to 32b float internally?
 	<reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
 
 	<reg32 offset="0xa989" name="SP_BLEND_CNTL">
-		<bitfield name="ENABLED" pos="0" type="boolean"/>
+		<!-- per-mrt enable bit -->
+		<bitfield name="ENABLE_BLEND" low="0" high="7"/>
 		<bitfield name="UNK8" pos="8" type="boolean"/>
 		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
 		<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index ccfa9eb34e3..c974eac4826 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -1998,7 +1998,7 @@ tu6_emit_blend_control(struct tu_cs *cs,
                              : ((1 << msaa_info->rasterizationSamples) - 1);
 
    tu_cs_emit_regs(cs,
-                   A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
+                   A6XX_SP_BLEND_CNTL(.enable_blend = blend_enable_mask,
                                       .dual_color_in_enable = dual_src_blend,
                                       .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
                                       .unk8 = true));
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blend.c b/src/gallium/drivers/freedreno/a6xx/fd6_blend.c
index 92f55b1a978..7c2f2193d76 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_blend.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_blend.c
@@ -125,9 +125,9 @@ __fd6_setup_blend_variant(struct fd6_blend_stateobj *blend,
             .dither_mode_mrt7 =
                cso->dither ? DITHER_ALWAYS : DITHER_DISABLE, ));
 
-   OUT_REG(ring, A6XX_SP_BLEND_CNTL(.unk8 = true,
+   OUT_REG(ring, A6XX_SP_BLEND_CNTL(.enable_blend = mrt_blend,
+                                    .unk8 = true,
                                     .alpha_to_coverage = cso->alpha_to_coverage,
-                                    .enabled = !!mrt_blend,
                                     .dual_color_in_enable =
                                        blend->use_dual_src_blend, ));