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anv: update some of the indirect invalidations

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31915>
This commit is contained in:
Lionel Landwerlin 2024-10-30 20:09:22 +02:00 • committed by Marge Bot
parent cb224370b6
commit 1485b5659a
1 changed files with 6 additions and 6 deletions
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12
src/intel/vulkan/genX_cmd_buffer.c
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@ -3805,15 +3805,15 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_cmd_buffer *cmd_buffer,
*/
pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
}
/* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
* UBO from the buffer, so we need to invalidate constant cache.
/* For CmdDipatchIndirect, we load indirect gl_NumWorkGroups through
* an A64 message, so we need to invalidate constant cache.
*/
pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
/* Tile cache flush needed For CmdDipatchIndirect since command
* streamer and vertex fetch aren't L3 coherent.
/* Tile & Data cache flush needed For Cmd*Indirect* commands since
* command streamer is not L3 coherent.
*/
pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT |
ANV_PIPE_DATA_CACHE_FLUSH_BIT;
break;
case VK_ACCESS_2_INDEX_READ_BIT:
case VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT: