From 1485b5659ab9f9ac3b27962c91173000ce79cad0 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Wed, 30 Oct 2024 20:09:22 +0200 Subject: [PATCH] anv: update some of the indirect invalidations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Lionel Landwerlin Reviewed-by: Nanley Chery Reviewed-by: Tapani Pälli Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 41960712d26..3f7a50d9e96 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -3805,15 +3805,15 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_cmd_buffer *cmd_buffer, */ pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT; } - /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a - * UBO from the buffer, so we need to invalidate constant cache. + /* For CmdDipatchIndirect, we load indirect gl_NumWorkGroups through + * an A64 message, so we need to invalidate constant cache. */ pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT; - pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT; - /* Tile cache flush needed For CmdDipatchIndirect since command - * streamer and vertex fetch aren't L3 coherent. + /* Tile & Data cache flush needed For Cmd*Indirect* commands since + * command streamer is not L3 coherent. */ - pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT; + pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT | + ANV_PIPE_DATA_CACHE_FLUSH_BIT; break; case VK_ACCESS_2_INDEX_READ_BIT: case VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT: