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intel/isl: Simplify Z-buffer tiling config during emit

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For SNB and prior, assert that the surface is Y-tiled and use constants
when configuring the tiling parameters. This makes a follow-on commit
clearer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
This commit is contained in:
Nanley Chery 2022-02-01 13:51:06 -05:00 • committed by Marge Bot
parent 06aaa2cead
commit 146213d0ee
1 changed files with 3 additions and 3 deletions
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6
src/intel/isl/isl_emit_depth_stencil.c
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@ -129,9 +129,9 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
db.RenderCompressionFormat =
isl_get_render_compression_format(info->depth_surf->format);
#elif GFX_VER <= 6
db.TiledSurface = info->depth_surf->tiling != ISL_TILING_LINEAR;
db.TileWalk = info->depth_surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
TILEWALK_XMAJOR;
assert(info->depth_surf->tiling == ISL_TILING_Y0);
db.TiledSurface = true;
db.TileWalk = TILEWALK_YMAJOR;
db.MIPMapLayoutMode = MIPLAYOUT_BELOW;
#endif