From 146213d0ee0b95a951e76b6493c7bb3ed92481a8 Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Tue, 1 Feb 2022 13:51:06 -0500 Subject: [PATCH] intel/isl: Simplify Z-buffer tiling config during emit For SNB and prior, assert that the surface is Y-tiled and use constants when configuring the tiling parameters. This makes a follow-on commit clearer. Reviewed-by: Lionel Landwerlin Reviewed-by: Kenneth Graunke Part-of: --- src/intel/isl/isl_emit_depth_stencil.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index 1bc9b72acb7..b72ed25d3e6 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -129,9 +129,9 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, db.RenderCompressionFormat = isl_get_render_compression_format(info->depth_surf->format); #elif GFX_VER <= 6 - db.TiledSurface = info->depth_surf->tiling != ISL_TILING_LINEAR; - db.TileWalk = info->depth_surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR : - TILEWALK_XMAJOR; + assert(info->depth_surf->tiling == ISL_TILING_Y0); + db.TiledSurface = true; + db.TileWalk = TILEWALK_YMAJOR; db.MIPMapLayoutMode = MIPLAYOUT_BELOW; #endif