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radeonsi: fix a GS hang on VI

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Broken by one of the cleanups: 0d46c3bc9d
Not applicable to stable.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák 2015-10-02 19:21:54 +02:00
parent 5749676d03
commit 13e69805ea
2 changed files with 19 additions and 0 deletions
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1
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -192,6 +192,7 @@ struct si_context {
/* Precomputed states. */
struct si_pm4_state *init_config;
bool init_config_has_vgt_flush;
struct si_pm4_state *vgt_shader_config[4];
/* With rasterizer discard, there doesn't have to be a pixel shader.
* In that case, we bind this one: */

18
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -1136,6 +1136,20 @@ static void si_emit_spi_ps_input(struct si_context *sctx, struct r600_atom *atom
sctx->force_persample_interp);
}
/**
* Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
*/
static void si_init_config_add_vgt_flush(struct si_context *sctx)
{
if (sctx->init_config_has_vgt_flush)
return;
si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
si_pm4_cmd_end(sctx->init_config, false);
sctx->init_config_has_vgt_flush = true;
}
/* Initialize state related to ESGS / GSVS ring buffers */
static void si_init_gs_rings(struct si_context *sctx)
{
@ -1156,6 +1170,8 @@ static void si_init_gs_rings(struct si_context *sctx)
return;
}
si_init_config_add_vgt_flush(sctx);
/* Append these registers to the init config state. */
if (sctx->b.chip_class >= CIK) {
if (sctx->b.chip_class >= VI) {
@ -1402,6 +1418,8 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
si_init_config_add_vgt_flush(sctx);
/* Append these registers to the init config state. */
if (sctx->b.chip_class >= CIK) {
si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,