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radeonsi: remove TC L2 cache flush for index buffers on VI

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Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák 2015-09-06 15:43:23 +02:00
parent 6ed8fd3d67
commit 5749676d03
1 changed files with 3 additions and 3 deletions
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6
src/gallium/drivers/radeonsi/si_state_draw.c
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@ -813,9 +813,9 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
}
}
/* TODO: VI should read index buffers through TC, so this shouldn't be
* needed on VI. */
if (info->indexed && r600_resource(ib.buffer)->TC_L2_dirty) {
/* VI reads index buffers through TC L2. */
if (info->indexed && sctx->b.chip_class <= CIK &&
r600_resource(ib.buffer)->TC_L2_dirty) {
sctx->b.flags |= SI_CONTEXT_INV_TC_L2;
r600_resource(ib.buffer)->TC_L2_dirty = false;
}