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brw: fix task/mesh push constant loading

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The InlineData passed to the shader is a fixed size unrelated to the
register size. It happens to match pre-Xe2, but by considering it the
same in Xe2, we ended up reading pushed constants from the wrong place
when they didn't fit in the InlineData.

Fixes: 97b17aa0b1 ("brw/nir: rework inline_data_intel to work with compute")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31856>
This commit is contained in:
Iván Briano 2024-10-25 14:30:50 -07:00 • committed by Marge Bot
parent b7560fa048
commit 13db5fad27
1 changed files with 1 additions and 4 deletions
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5
src/intel/compiler/brw_compile_mesh.cpp
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@ -49,9 +49,6 @@ static nir_def *
brw_nir_lower_load_uniforms_impl(nir_builder *b, nir_instr *instr,
void *data)
{
const struct intel_device_info *devinfo =
(const struct intel_device_info *)data;
assert(instr->type == nir_instr_type_intrinsic);
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
assert(intrin->intrinsic == nir_intrinsic_load_uniform);
@ -62,7 +59,7 @@ brw_nir_lower_load_uniforms_impl(nir_builder *b, nir_instr *instr,
BRW_TASK_MESH_PUSH_CONSTANTS_START_DW * 4 +
nir_intrinsic_base(intrin) + nir_src_as_uint(intrin->src[0]);
int range = intrin->def.num_components * intrin->def.bit_size / 8;
if ((offset + range) <= (int)(REG_SIZE * reg_unit(devinfo))) {
if ((offset + range) <= (int)(BRW_TASK_MESH_INLINE_DATA_SIZE_DW * 4)) {
return nir_load_inline_data_intel(b,
intrin->def.num_components,
intrin->def.bit_size,