From 13db5fad2788f68f13990a11241611b587b62fcb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Iv=C3=A1n=20Briano?= Date: Fri, 25 Oct 2024 14:30:50 -0700 Subject: [PATCH] brw: fix task/mesh push constant loading The InlineData passed to the shader is a fixed size unrelated to the register size. It happens to match pre-Xe2, but by considering it the same in Xe2, we ended up reading pushed constants from the wrong place when they didn't fit in the InlineData. Fixes: 97b17aa0b1b ("brw/nir: rework inline_data_intel to work with compute") Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_compile_mesh.cpp | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_compile_mesh.cpp b/src/intel/compiler/brw_compile_mesh.cpp index 84c46255f9d..b1261edf405 100644 --- a/src/intel/compiler/brw_compile_mesh.cpp +++ b/src/intel/compiler/brw_compile_mesh.cpp @@ -49,9 +49,6 @@ static nir_def * brw_nir_lower_load_uniforms_impl(nir_builder *b, nir_instr *instr, void *data) { - const struct intel_device_info *devinfo = - (const struct intel_device_info *)data; - assert(instr->type == nir_instr_type_intrinsic); nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); assert(intrin->intrinsic == nir_intrinsic_load_uniform); @@ -62,7 +59,7 @@ brw_nir_lower_load_uniforms_impl(nir_builder *b, nir_instr *instr, BRW_TASK_MESH_PUSH_CONSTANTS_START_DW * 4 + nir_intrinsic_base(intrin) + nir_src_as_uint(intrin->src[0]); int range = intrin->def.num_components * intrin->def.bit_size / 8; - if ((offset + range) <= (int)(REG_SIZE * reg_unit(devinfo))) { + if ((offset + range) <= (int)(BRW_TASK_MESH_INLINE_DATA_SIZE_DW * 4)) { return nir_load_inline_data_intel(b, intrin->def.num_components, intrin->def.bit_size,