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i965/blorp: Let program data tell if push constants are needed

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Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Topi Pohjolainen 2016-05-16 10:18:53 +03:00
parent 874f2e9523
commit 12783aac50
3 changed files with 35 additions and 15 deletions
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8
src/mesa/drivers/dri/i965/gen6_blorp.c
View file

@ -1022,7 +1022,11 @@ gen6_blorp_exec(struct brw_context *brw,
if (params->wm_prog_data) {
uint32_t wm_surf_offset_renderbuffer;
uint32_t wm_surf_offset_texture = 0;
wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
if (params->wm_prog_data->nr_params) {
wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
}
intel_miptree_used_for_rendering(params->dst.mt);
wm_surf_offset_renderbuffer =
gen6_blorp_emit_surface_state(brw, params, &params->dst,
@ -1048,7 +1052,7 @@ gen6_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_gs_disable(brw, params);
gen6_blorp_emit_clip_disable(brw);
gen6_blorp_emit_sf_config(brw, params);
if (params->wm_prog_data)
if (params->wm_prog_data && params->wm_prog_data->nr_params)
gen6_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
else
gen6_blorp_emit_constant_ps_disable(brw, params);

16
src/mesa/drivers/dri/i965/gen7_blorp.c
View file

@ -543,7 +543,8 @@ gen7_blorp_emit_ps_config(struct brw_context *brw,
if (brw->is_haswell)
dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
if (params->wm_prog_data) {
dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
if (params->wm_prog_data->nr_params)
dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
dw5 |= prog_data->first_curbe_grf_0 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
dw5 |= prog_data->first_curbe_grf_2 << GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
@ -847,7 +848,11 @@ gen7_blorp_exec(struct brw_context *brw,
if (params->wm_prog_data) {
uint32_t wm_surf_offset_renderbuffer;
uint32_t wm_surf_offset_texture = 0;
wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
if (params->wm_prog_data->nr_params) {
wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
}
intel_miptree_used_for_rendering(params->dst.mt);
wm_surf_offset_renderbuffer =
gen7_blorp_emit_surface_state(brw, &params->dst,
@ -874,12 +879,13 @@ gen7_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_clip_disable(brw);
gen7_blorp_emit_sf_config(brw, params);
gen7_blorp_emit_wm_config(brw, params);
if (params->wm_prog_data) {
if (params->wm_prog_data)
gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
if (params->wm_prog_data && params->wm_prog_data->nr_params)
gen7_blorp_emit_constant_ps(brw, wm_push_const_offset);
} else {
else
gen7_blorp_emit_constant_ps_disable(brw);
}
if (params->src.mt) {
const uint32_t sampler_offset =

26
src/mesa/drivers/dri/i965/gen8_blorp.c
View file

@ -393,7 +393,9 @@ gen8_blorp_emit_ps_config(struct brw_context *brw,
dw3 |= 1 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT; /* One surface */
}
dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
if (prog_data->nr_params)
dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
dw7 |= prog_data->first_curbe_grf_0 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
dw7 |= prog_data->first_curbe_grf_2 << GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
@ -563,6 +565,7 @@ gen8_blorp_emit_depth_stencil_state(struct brw_context *brw,
static void
gen8_blorp_emit_constant_ps(struct brw_context *brw,
const struct brw_blorp_params *params,
uint32_t wm_push_const_offset)
{
const int dwords = brw->gen >= 8 ? 11 : 7;
@ -571,9 +574,9 @@ gen8_blorp_emit_constant_ps(struct brw_context *brw,
if (brw->gen >= 9) {
OUT_BATCH(0);
OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
OUT_BATCH(params->wm_prog_data->nr_params);
} else {
OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
OUT_BATCH(params->wm_prog_data->nr_params);
OUT_BATCH(0);
}
@ -582,8 +585,15 @@ gen8_blorp_emit_constant_ps(struct brw_context *brw,
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_RENDER, 0,
wm_push_const_offset);
if (params->wm_prog_data->nr_params) {
OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_RENDER, 0,
wm_push_const_offset);
} else {
OUT_BATCH(0);
OUT_BATCH(0);
}
OUT_BATCH(0);
OUT_BATCH(0);
} else {
@ -681,9 +691,9 @@ gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params)
gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_DS);
gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_GS);
const uint32_t wm_push_const_offset =
gen6_blorp_emit_wm_constants(brw, params);
gen8_blorp_emit_constant_ps(brw, wm_push_const_offset);
const uint32_t wm_push_const_offset = params->wm_prog_data->nr_params ?
gen6_blorp_emit_wm_constants(brw, params) : 0;
gen8_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
wm_bind_bo_offset = gen8_blorp_emit_surface_states(brw, params);
gen8_blorp_emit_disable_binding_table(brw,