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i965/blorp: Use prog data counters to guide wm/ps setup

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just as core upload logic does.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Topi Pohjolainen 2016-05-18 16:09:49 +03:00
parent f5e8575ab4
commit 874f2e9523
3 changed files with 8 additions and 3 deletions
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4
src/mesa/drivers/dri/i965/gen6_blorp.c
View file

@ -656,7 +656,9 @@ gen6_blorp_emit_wm_config(struct brw_context *brw,
dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
dw6 |= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
dw6 |= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT; /* No inputs from SF */
dw6 |= (params->wm_prog_data ? prog_data->num_varying_inputs : 0) <<
GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
if (params->wm_prog_data) {
dw5 |= GEN6_WM_DISPATCH_ENABLE; /* We are rendering */

2
src/mesa/drivers/dri/i965/gen7_blorp.c
View file

@ -555,6 +555,8 @@ gen7_blorp_emit_ps_config(struct brw_context *brw,
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
if (params->wm_prog_data->dispatch_16)
dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
if (params->wm_prog_data->num_varying_inputs)
dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
} else {
/* The hardware gets angry if we don't enable at least one dispatch
* mode, so just enable 16-pixel dispatch if we don't have a program.

5
src/mesa/drivers/dri/i965/gen8_blorp.c
View file

@ -452,10 +452,11 @@ gen8_blorp_emit_ps_extra(struct brw_context *brw,
dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
if (params->src.mt) {
if (params->src.mt)
dw1 |= GEN8_PSX_KILL_ENABLE;
if (params->wm_prog_data->num_varying_inputs)
dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
}
if (params->dst.num_samples > 1 && prog_data &&
prog_data->persample_msaa_dispatch)