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r300g: add r4xx fragment shader registers

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In case anyone needs it, it's here.
This commit is contained in:
Marek Olšák 2010-02-21 18:22:18 +01:00
parent 6eb892cc12
commit 116c99768e
1 changed files with 47 additions and 1 deletions
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48
src/gallium/drivers/r300/r300_reg.h
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@ -1740,6 +1740,10 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 13)
# define R300_PFS_CNTL_TEX_END_SHIFT 18
# define R300_PFS_CNTL_TEX_END_MASK (31 << 18)
# define R400_PFS_CNTL_TEX_OFFSET_MSB_SHIFT 24
# define R400_PFS_CNTL_TEX_OFFSET_MSB_MASK (0xf << 24)
# define R400_PFS_CNTL_TEX_END_MSB_SHIFT 28
# define R400_PFS_CNTL_TEX_END_MSB_MASK (0xf << 28)
/* gap */
@ -1764,6 +1768,10 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_TEX_SIZE_MASK (31 << 17)
# define R300_RGBA_OUT (1 << 22)
# define R300_W_OUT (1 << 23)
# define R400_TEX_START_MSB_SHIFT 24
# define R400_TEX_START_MSG_MASK (0xf << 24)
# define R400_TEX_SIZE_MSB_SHIFT 28
# define R400_TEX_SIZE_MSG_MASK (0xf << 28)
/* TEX
* As far as I can tell, texture instructions cannot write into output
@ -1784,6 +1792,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_TEX_OP_TXP 3
# define R300_TEX_OP_TXB 4
# define R300_TEX_INST_MASK (7 << 15)
# define R400_SRC_ADDR_EXT_BIT (1 << 19)
# define R400_DST_ADDR_EXT_BIT (1 << 20)
/* Output format from the unfied shader */
#define R300_US_OUT_FMT_0 0x46A4
@ -2092,6 +2102,43 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_ALU_OUTA_CLAMP (1 << 30)
/* END: Fragment program instruction set */
/* R4xx extended fragment shader registers. */
#define R400_US_ALU_EXT_ADDR_0 0x4ac0 /* up to 63 (0x4bbc) */
# define R400_ADDR0_EXT_RGB_MSB_BIT 0x01
# define R400_ADDR1_EXT_RGB_MSB_BIT 0x02
# define R400_ADDR2_EXT_RGB_MSB_BIT 0x04
# define R400_ADDRD_EXT_RGB_MSB_BIT 0x08
# define R400_ADDR0_EXT_A_MSB_BIT 0x10
# define R400_ADDR1_EXT_A_MSB_BIT 0x20
# define R400_ADDR2_EXT_A_MSB_BIT 0x40
# define R400_ADDRD_EXT_A_MSB_BIT 0x80
#define R400_US_CODE_BANK 0x46b8
# define R400_BANK_SHIFT 0
# define R400_BANK_MASK 0xf
# define R400_R390_MODE_ENABLE (1 << 4)
#define R400_US_CODE_EXT 0x46bc
# define R400_ALU_OFFSET_MSB_SHIFT 0
# define R400_ALU_OFFSET_MSB_MASK (0x7 << 0)
# define R400_ALU_SIZE_MSB_SHIFT 3
# define R400_ALU_SIZE_MSB_MASK (0x7 << 3)
# define R400_ALU_START0_MSB_SHIFT 6
# define R400_ALU_START0_MSB_MASK (0x7 << 6)
# define R400_ALU_SIZE0_MSB_SHIFT 9
# define R400_ALU_SIZE0_MSB_MASK (0x7 << 9)
# define R400_ALU_START1_MSB_SHIFT 12
# define R400_ALU_START1_MSB_MASK (0x7 << 12)
# define R400_ALU_SIZE1_MSB_SHIFT 15
# define R400_ALU_SIZE1_MSB_MASK (0x7 << 15)
# define R400_ALU_START2_MSB_SHIFT 18
# define R400_ALU_START2_MSB_MASK (0x7 << 18)
# define R400_ALU_SIZE2_MSB_SHIFT 21
# define R400_ALU_SIZE2_MSB_MASK (0x7 << 21)
# define R400_ALU_START3_MSB_SHIFT 24
# define R400_ALU_START3_MSB_MASK (0x7 << 24)
# define R400_ALU_SIZE3_MSB_SHIFT 27
# define R400_ALU_SIZE3_MSB_MASK (0x7 << 27)
/* END: R4xx extended fragment shader registers. */
/* Fog: Fog Blending Enable */
#define R300_FG_FOG_BLEND 0x4bc0
# define R300_FG_FOG_BLEND_DISABLE (0 << 0)
@ -3290,7 +3337,6 @@ enum {
# define R300_W_SRC_US (0 << 2)
# define R300_W_SRC_RAS (1 << 2)
/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
* Two parameter dwords:
* 0. VAP_VTX_FMT: The first parameter is not written to hardware