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https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-04-25 13:30:38 +02:00
r600/sfn: lower tg4 to backend in NIR
Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
This commit is contained in:
Gert Wollny
Marge Bot
parent
1dca2b8ae9
commit
10ddbf50bb
2 changed files with 112 additions and 117 deletions
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@ -350,8 +350,6 @@ bool TexInstr::from_nir(nir_tex_instr *tex, Shader& shader)
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return emit_tex_lod(tex, src, shader);
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case nir_texop_query_levels:
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return emit_tex_txs(tex, src, {3,7,7,7}, shader);
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case nir_texop_tg4:
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return emit_tex_tg4(tex, src, shader);
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case nir_texop_texture_samples:
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return emit_tex_texture_samples(tex, src, shader);
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default:
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@ -401,6 +399,57 @@ get_sampler_id(int sampler_id, const nir_variable *deref)
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return result;
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}
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void TexInstr::emit_set_gradients(nir_tex_instr* tex, int sampler_id,
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Inputs& src, TexInstr *irt, Shader& shader)
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{
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TexInstr *grad[2] = {nullptr, nullptr};
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RegisterVec4 empty_dst(0, false, {0,0,0,0}, pin_group);
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grad[0] = new TexInstr(set_gradient_h, empty_dst, {7,7,7,7}, src.ddx,
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sampler_id,
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sampler_id + R600_MAX_CONST_BUFFERS,
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src.sampler_offset);
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grad[0]->set_rect_coordinate_flags(tex);
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grad[0]->set_always_keep();
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grad[1] = new TexInstr(set_gradient_v, empty_dst, {7,7,7,7}, src.ddy,
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sampler_id, sampler_id + R600_MAX_CONST_BUFFERS,
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src.sampler_offset);
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grad[1]->set_rect_coordinate_flags(tex);
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grad[1]->set_always_keep();
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irt->add_prepare_instr(grad[0]);
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irt->add_prepare_instr(grad[1]);
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if (shader.last_txd())
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irt->add_required_instr(shader.last_txd());
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shader.set_last_txd(irt);
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}
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void TexInstr::emit_set_offsets(nir_tex_instr* tex, int sampler_id,
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Inputs& src, TexInstr *irt, Shader& shader)
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{
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RegisterVec4::Swizzle swizzle = {4,4,4,4};
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int src_components = tex->coord_components;
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if (tex->is_array)
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--src_components;
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for (int i = 0; i < src_components; ++i)
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swizzle[i] = i;
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int noffsets = tex->coord_components;
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if (tex->is_array)
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--noffsets;
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auto ofs = shader.value_factory().src_vec4(*src.offset, pin_group, swizzle);
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RegisterVec4 empty_dst(0, false, {0,0,0,0}, pin_group);
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auto set_ofs = new TexInstr(TexInstr::set_offsets, empty_dst, {7,7,7,7},
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ofs, sampler_id,
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sampler_id + R600_MAX_CONST_BUFFERS,
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src.sampler_offset);
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set_ofs->set_always_keep();
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irt->add_prepare_instr(set_ofs);
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}
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bool TexInstr::emit_lowered_tex(nir_tex_instr* tex, Inputs& src, Shader& shader)
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{
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assert(src.backend1);
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@ -418,8 +467,7 @@ bool TexInstr::emit_lowered_tex(nir_tex_instr* tex, Inputs& src, Shader& shader)
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int32_t coord_mask = params[0].i32;
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int32_t flags = params[1].i32;
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int32_t inst_mode = params[2].i32;
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TexInstr *grad[2] = {nullptr, nullptr};
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uint32_t dst_swz_packed = params[3].u32;
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auto dst = vf.dest_vec4(tex->dest, pin_group);
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@ -429,29 +477,23 @@ bool TexInstr::emit_lowered_tex(nir_tex_instr* tex, Inputs& src, Shader& shader)
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auto src_coord = vf.src_vec4(*src.backend1, pin_group, src_swizzle);
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auto irt = new TexInstr(src.opcode, dst, {0,1,2,3}, src_coord, sampler.id,
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RegisterVec4::Swizzle dst_swz = {0,1,2,3};
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if (dst_swz_packed) {
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for (int i = 0; i < 4; ++i) {
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dst_swz[i] = (dst_swz_packed >> (8 * i)) & 0xff;
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}
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}
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auto irt = new TexInstr(src.opcode, dst, dst_swz, src_coord, sampler.id,
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sampler.id + R600_MAX_CONST_BUFFERS,
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src.sampler_offset);
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if (tex->op == nir_texop_txd) {
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RegisterVec4 empty_dst(0, false, {0,0,0,0}, pin_group);
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grad[0] = new TexInstr(set_gradient_h, empty_dst, {7,7,7,7}, src.ddx,
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sampler.id,
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sampler.id + R600_MAX_CONST_BUFFERS,
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src.sampler_offset);
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grad[0]->set_rect_coordinate_flags(tex);
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grad[0]->set_always_keep();
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if (tex->op == nir_texop_txd)
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emit_set_gradients(tex, sampler.id, src, irt, shader);
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grad[1] = new TexInstr(set_gradient_v, empty_dst, {7,7,7,7}, src.ddy,
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sampler.id, sampler.id + R600_MAX_CONST_BUFFERS,
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src.sampler_offset);
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grad[1]->set_rect_coordinate_flags(tex);
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grad[1]->set_always_keep();
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irt->add_prepare_instr(grad[0]);
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irt->add_prepare_instr(grad[1]);
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if (shader.last_txd())
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irt->add_required_instr(shader.last_txd());
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shader.set_last_txd(irt);
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if (!irt->set_coord_offsets(src.offset)) {
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assert(tex->op == nir_texop_tg4);
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emit_set_offsets(tex, sampler.id, src, irt, shader);
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}
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for (const auto f : TexFlags) {
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@ -459,7 +501,7 @@ bool TexInstr::emit_lowered_tex(nir_tex_instr* tex, Inputs& src, Shader& shader)
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irt->set_tex_flag(f);
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}
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irt->set_coord_offsets(src.offset);
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irt->set_inst_mode(inst_mode);
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shader.emit_instruction(irt);
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@ -575,89 +617,6 @@ bool TexInstr::emit_tex_txs(nir_tex_instr *tex, Inputs& src,
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return true;
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}
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bool TexInstr::emit_tex_tg4(nir_tex_instr* tex, Inputs& src , Shader& shader)
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{
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auto& vf = shader.value_factory();
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r600::sfn_log << SfnLog::instr << "emit '"
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<< *reinterpret_cast<nir_instr*>(tex)
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<< "' (" << __func__ << ")\n";
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TexInstr *set_ofs = nullptr;
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auto src_coord = prepare_source(tex, src, shader);
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r600::sfn_log << SfnLog::instr << "emit '"
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<< *reinterpret_cast<nir_instr*>(tex)
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<< "' (" << __func__ << ")\n";
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auto dst = vf.dest_vec4(tex->dest, pin_group);
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RegisterVec4 empty_dst(125, false, {7,7,7,7}, pin_group);
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/* pre CAYMAN needs swizzle */
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auto dest_swizzle = shader.chip_class() <= ISA_CC_EVERGREEN ?
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RegisterVec4::Swizzle{1, 2, 0, 3} :
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RegisterVec4::Swizzle{0, 1, 2, 3};
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auto sampler = get_sampler_id(tex->sampler_index, src.sampler_deref);
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assert(!sampler.indirect && "Indirect sampler selection not yet supported");
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bool literal_offset = false;
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if (src.offset) {
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literal_offset = nir_src_as_const_value(*src.offset) != 0;
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r600::sfn_log << SfnLog::tex << " really have offsets and they are " <<
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(literal_offset ? "l" : "varying") <<
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"\n";
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if (!literal_offset) {
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RegisterVec4::Swizzle swizzle = {4,4,4,4};
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int src_components = tex->coord_components;
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if (tex->is_array)
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--src_components;
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for (int i = 0; i < src_components; ++i)
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swizzle[i] = i;
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int noffsets = tex->coord_components;
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if (tex->is_array)
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--noffsets;
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auto ofs = vf.src_vec4(*src.offset, pin_group, swizzle);
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RegisterVec4 dummy(0, true, {7,7,7,7});
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set_ofs = new TexInstr(TexInstr::set_offsets, dummy, {7,7,7,7},
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ofs, sampler.id,
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sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
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} else {
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src.opcode = src.opcode == gather4_o ? gather4 : gather4_c;
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}
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}
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auto irt = new TexInstr(src.opcode, dst, dest_swizzle, src_coord, sampler.id,
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sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
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irt->set_gather_comp(tex->component);
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if (tex->is_array)
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irt->set_tex_flag(z_unnormalized);
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if (literal_offset) {
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r600::sfn_log << SfnLog::tex << "emit literal offsets\n";
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irt->set_coord_offsets(src.offset);
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}
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irt->set_rect_coordinate_flags(tex);
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if (set_ofs) {
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set_ofs->set_always_keep();
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irt->add_prepare_instr(set_ofs);
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}
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shader.emit_instruction(irt);
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return true;
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}
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auto TexInstr::prepare_source(nir_tex_instr *tex, const Inputs& inputs, Shader& shader) -> RegisterVec4
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{
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RegisterVec4::Swizzle target{7,7,7,7};
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@ -806,11 +765,12 @@ auto TexInstr::Inputs::get_opcode(const nir_tex_instr& instr) -> Opcode
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return get_resinfo;
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case nir_texop_txd:
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return instr.is_shadow ? sample_c_g : sample_g;
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case nir_texop_tg4:
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case nir_texop_tg4: {
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auto var_offset = offset && nir_src_as_const_value(*offset) == nullptr;
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return instr.is_shadow ?
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(offset ? gather4_c_o : gather4_c) :
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(offset ? gather4_o : gather4);
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(var_offset ? gather4_c_o : gather4_c) :
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(var_offset ? gather4_o : gather4);
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}
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case nir_texop_txf_ms:
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return ld;
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case nir_texop_query_levels:
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@ -860,17 +820,21 @@ RegisterVec4::Swizzle TexInstr::Inputs::swizzle_from_ncomps(int comps) const
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return swz;
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}
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void TexInstr::set_coord_offsets(nir_src *offset)
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bool TexInstr::set_coord_offsets(nir_src *offset)
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{
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if (!offset)
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return;
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return true;
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if (!offset->is_ssa)
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return false;
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assert(offset->is_ssa);
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auto literal = nir_src_as_const_value(*offset);
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assert(literal);
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if (!literal)
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return false;
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for (int i = 0; i < offset->ssa->num_components; ++i)
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set_offset(i, literal[i].i32);
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return true;
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}
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void TexInstr::set_rect_coordinate_flags(nir_tex_instr* instr)
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@ -890,6 +854,7 @@ private:
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nir_ssa_def *lower_tex(nir_tex_instr *tex);
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nir_ssa_def *lower_txf(nir_tex_instr *tex);
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nir_ssa_def *lower_tg4(nir_tex_instr *tex);
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nir_ssa_def *lower_txf_ms(nir_tex_instr *tex);
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nir_ssa_def *lower_txf_ms_direct(nir_tex_instr *tex);
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@ -931,6 +896,7 @@ bool LowerTexToBackend::filter(const nir_instr *instr) const
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case nir_texop_txl:
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case nir_texop_txf:
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case nir_texop_txd:
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case nir_texop_tg4:
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case nir_texop_txf_ms:
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break;
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default:
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@ -953,6 +919,8 @@ nir_ssa_def *LowerTexToBackend::lower(nir_instr *instr)
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return lower_tex(tex);
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case nir_texop_txf:
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return lower_txf(tex);
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case nir_texop_tg4:
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return lower_tg4(tex);
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case nir_texop_txf_ms:
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if (m_chip_class < EVERGREEN)
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return lower_txf_ms_direct(tex);
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@ -998,6 +966,30 @@ nir_ssa_def *LowerTexToBackend::lower_txf(nir_tex_instr *tex)
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return finalize(tex, backend1, backend2);
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}
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nir_ssa_def *LowerTexToBackend::lower_tg4(nir_tex_instr *tex)
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{
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std::array<nir_ssa_def *, 4> new_coord = {
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nullptr,
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nullptr,
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nullptr,
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nullptr
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};
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get_src_coords(tex, new_coord, false);
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uint32_t dest_swizzle = m_chip_class <= EVERGREEN ?
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1 | (2 << 8) | (0 << 16) | (3 << 24) : 0;
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int used_coord_mask = 0;
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int unnormalized_mask = 0;
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nir_ssa_def *backend1 = prepare_coord(tex, unnormalized_mask, used_coord_mask);
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nir_ssa_def *backend2 = nir_imm_ivec4(b, used_coord_mask,
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unnormalized_mask,
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tex->component,
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dest_swizzle);
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return finalize(tex, backend1, backend2);
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}
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nir_ssa_def *LowerTexToBackend::lower_txf_ms(nir_tex_instr *tex)
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{
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std::array<nir_ssa_def *, 4> new_coord = {
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@ -174,11 +174,14 @@ private:
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static bool emit_tex_txs(nir_tex_instr *tex, Inputs& src,
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RegisterVec4::Swizzle dest_swz, Shader& shader);
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static bool emit_tex_lod(nir_tex_instr* tex, Inputs& src, Shader& shader);
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static bool emit_tex_tg4(nir_tex_instr* instr, Inputs& src , Shader& shader);
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static bool emit_tex_texture_samples(nir_tex_instr* instr, Inputs& src, Shader& shader);
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static bool emit_lowered_tex(nir_tex_instr* instr, Inputs& src, Shader& shader);
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static void emit_set_gradients(nir_tex_instr* tex, int sampler_id,
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Inputs& src, TexInstr *irt, Shader& shader);
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static void emit_set_offsets(nir_tex_instr* tex, int sampler_id,
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Inputs& src, TexInstr *irt, Shader& shader);
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void set_coord_offsets(nir_src *offset);
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bool set_coord_offsets(nir_src *offset);
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void set_rect_coordinate_flags(nir_tex_instr* instr);
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void add_prepare_instr(TexInstr *ir) {m_prepare_instr.push_back(ir);};
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