mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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radeonsi: remove si_get_param and si_get_paramf
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32955>
This commit is contained in:
Qiang Yu
Marge Bot
parent
22516c4a71
commit
10c9129139
1 changed files with 0 additions and 407 deletions
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@ -56,411 +56,6 @@ si_is_compute_copy_faster(struct pipe_screen *pscreen,
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return false;
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}
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static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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{
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struct si_screen *sscreen = (struct si_screen *)pscreen;
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/* Gfx8 (Polaris11) hangs, so don't enable this on Gfx8 and older chips. */
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bool enable_sparse = sscreen->info.gfx_level >= GFX9 && sscreen->info.gfx_level < GFX12 &&
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sscreen->info.has_sparse_vm_mappings;
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switch (param) {
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/* Supported features (boolean caps). */
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case PIPE_CAP_ACCELERATED:
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case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
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case PIPE_CAP_ANISOTROPIC_FILTER:
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case PIPE_CAP_OCCLUSION_QUERY:
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
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case PIPE_CAP_TEXTURE_SHADOW_LOD:
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
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case PIPE_CAP_BLEND_EQUATION_SEPARATE:
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case PIPE_CAP_TEXTURE_SWIZZLE:
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case PIPE_CAP_DEPTH_CLIP_DISABLE:
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case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
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case PIPE_CAP_SHADER_STENCIL_EXPORT:
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case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
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case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
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case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
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case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
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case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
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case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
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case PIPE_CAP_PRIMITIVE_RESTART:
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case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
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case PIPE_CAP_CONDITIONAL_RENDER:
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case PIPE_CAP_TEXTURE_BARRIER:
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case PIPE_CAP_INDEP_BLEND_ENABLE:
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case PIPE_CAP_INDEP_BLEND_FUNC:
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case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
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case PIPE_CAP_START_INSTANCE:
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case PIPE_CAP_NPOT_TEXTURES:
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case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
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case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
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case PIPE_CAP_VERTEX_COLOR_CLAMPED:
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case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
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case PIPE_CAP_VS_INSTANCEID:
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case PIPE_CAP_COMPUTE:
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case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
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case PIPE_CAP_VS_LAYER_VIEWPORT:
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case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
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case PIPE_CAP_SAMPLE_SHADING:
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case PIPE_CAP_DRAW_INDIRECT:
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case PIPE_CAP_CLIP_HALFZ:
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case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
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case PIPE_CAP_POLYGON_OFFSET_CLAMP:
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case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
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case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
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case PIPE_CAP_TGSI_TEXCOORD:
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case PIPE_CAP_FS_FINE_DERIVATIVE:
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case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
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case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
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case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
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case PIPE_CAP_DEPTH_BOUNDS_TEST:
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case PIPE_CAP_SAMPLER_VIEW_TARGET:
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case PIPE_CAP_TEXTURE_QUERY_LOD:
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case PIPE_CAP_TEXTURE_GATHER_SM5:
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case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
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case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
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case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
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case PIPE_CAP_FS_POSITION_IS_SYSVAL:
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case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
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case PIPE_CAP_INVALIDATE_BUFFER:
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case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
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case PIPE_CAP_QUERY_BUFFER_OBJECT:
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case PIPE_CAP_QUERY_MEMORY_INFO:
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case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
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case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
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case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
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case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
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case PIPE_CAP_STRING_MARKER:
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case PIPE_CAP_CULL_DISTANCE:
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case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
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case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
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case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
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case PIPE_CAP_DOUBLES:
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case PIPE_CAP_TGSI_TEX_TXF_LZ:
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case PIPE_CAP_TES_LAYER_VIEWPORT:
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case PIPE_CAP_BINDLESS_TEXTURE:
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case PIPE_CAP_QUERY_TIMESTAMP:
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case PIPE_CAP_QUERY_TIME_ELAPSED:
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case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
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case PIPE_CAP_MEMOBJ:
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case PIPE_CAP_LOAD_CONSTBUF:
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case PIPE_CAP_INT64:
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case PIPE_CAP_SHADER_CLOCK:
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case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
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case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_SHADER_BALLOT:
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case PIPE_CAP_SHADER_GROUP_VOTE:
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case PIPE_CAP_FBFETCH:
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case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
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case PIPE_CAP_IMAGE_LOAD_FORMATTED:
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case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
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case PIPE_CAP_TGSI_DIV:
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case PIPE_CAP_PACKED_UNIFORMS:
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case PIPE_CAP_GL_SPIRV:
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case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
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case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE:
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case PIPE_CAP_NO_CLIP_ON_COPY_TEX:
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case PIPE_CAP_SHADER_ATOMIC_INT64:
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case PIPE_CAP_FRONTEND_NOOP:
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case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
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case PIPE_CAP_PREFER_REAL_BUFFER_IN_CONSTBUF0:
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case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
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case PIPE_CAP_IMAGE_ATOMIC_INC_WRAP:
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case PIPE_CAP_IMAGE_STORE_FORMATTED:
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case PIPE_CAP_ALLOW_DRAW_OUT_OF_ORDER:
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case PIPE_CAP_QUERY_SO_OVERFLOW:
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case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
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case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
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case PIPE_CAP_TEXTURE_MULTISAMPLE:
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case PIPE_CAP_ALLOW_GLTHREAD_BUFFER_SUBDATA_OPT: /* TODO: remove if it's slow */
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case PIPE_CAP_NULL_TEXTURES:
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case PIPE_CAP_HAS_CONST_BW:
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case PIPE_CAP_CL_GL_SHARING:
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case PIPE_CAP_CALL_FINALIZE_NIR_IN_LINKER:
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return 1;
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/* Tahiti and Verde only: reduction mode is unsupported due to a bug
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* (it might work sometimes, but that's not enough)
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*/
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case PIPE_CAP_SAMPLER_REDUCTION_MINMAX:
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case PIPE_CAP_SAMPLER_REDUCTION_MINMAX_ARB:
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return !(sscreen->info.family == CHIP_TAHITI || sscreen->info.family == CHIP_VERDE);
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case PIPE_CAP_TEXTURE_TRANSFER_MODES:
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return PIPE_TEXTURE_TRANSFER_BLIT | PIPE_TEXTURE_TRANSFER_COMPUTE;
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case PIPE_CAP_DRAW_VERTEX_STATE:
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return !(sscreen->debug_flags & DBG(NO_FAST_DISPLAY_LIST));
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case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
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return sscreen->info.gfx_level < GFX11 && !(sscreen->debug_flags & DBG(NO_FMASK));
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case PIPE_CAP_GLSL_ZERO_INIT:
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return 2;
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case PIPE_CAP_GENERATE_MIPMAP:
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case PIPE_CAP_SEAMLESS_CUBE_MAP:
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case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
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case PIPE_CAP_CUBE_MAP_ARRAY:
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return sscreen->info.has_3d_cube_border_color_mipmap;
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case PIPE_CAP_POST_DEPTH_COVERAGE:
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return sscreen->info.gfx_level >= GFX10;
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case PIPE_CAP_GRAPHICS:
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return sscreen->info.has_graphics;
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case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
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return !UTIL_ARCH_BIG_ENDIAN && sscreen->info.has_userptr;
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case PIPE_CAP_DEVICE_PROTECTED_SURFACE:
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return sscreen->info.has_tmz_support;
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case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
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return SI_MAP_BUFFER_ALIGNMENT;
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case PIPE_CAP_MAX_VERTEX_BUFFERS:
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return SI_MAX_ATTRIBS;
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case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
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case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
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case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
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case PIPE_CAP_MAX_VERTEX_STREAMS:
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case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
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case PIPE_CAP_MAX_WINDOW_RECTANGLES:
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return 4;
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case PIPE_CAP_GLSL_FEATURE_LEVEL:
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case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
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return 460;
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case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
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/* Optimal number for good TexSubImage performance on Polaris10. */
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return 64 * 1024 * 1024;
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case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
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return 4096 * 1024;
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case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT: {
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unsigned max_texels =
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pscreen->get_param(pscreen, PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT);
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/* FYI, BUF_RSRC_WORD2.NUM_RECORDS field limit is UINT32_MAX. */
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/* Gfx8 and older use the size in bytes for bounds checking, and the max element size
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* is 16B. Gfx9 and newer use the VGPR index for bounds checking.
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*/
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if (sscreen->info.gfx_level <= GFX8)
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max_texels = MIN2(max_texels, UINT32_MAX / 16);
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else
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/* Gallium has a limitation that it can only bind UINT32_MAX bytes, not texels.
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* TODO: Remove this after the gallium interface is changed. */
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max_texels = MIN2(max_texels, UINT32_MAX / 16);
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return max_texels;
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}
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case PIPE_CAP_MAX_CONSTANT_BUFFER_SIZE_UINT:
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case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT: {
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/* Return 1/4th of the heap size as the maximum because the max size is not practically
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* allocatable. Also, this can only return UINT32_MAX at most.
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*/
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unsigned max_size = MIN2((sscreen->info.max_heap_size_kb * 1024ull) / 4, UINT32_MAX);
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/* Allow max 512 MB to pass CTS with a 32-bit build. */
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if (sizeof(void*) == 4)
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max_size = MIN2(max_size, 512 * 1024 * 1024);
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return max_size;
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}
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case PIPE_CAP_MAX_TEXTURE_MB:
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/* Allow 1/4th of the heap size. */
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return sscreen->info.max_heap_size_kb / 1024 / 4;
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case PIPE_CAP_PREFER_BACK_BUFFER_REUSE:
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case PIPE_CAP_UMA:
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case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
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return 0;
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case PIPE_CAP_PERFORMANCE_MONITOR:
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return sscreen->info.gfx_level >= GFX7 && sscreen->info.gfx_level <= GFX10_3;
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case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
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return enable_sparse ? RADEON_SPARSE_PAGE_SIZE : 0;
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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if (!sscreen->info.is_amdgpu)
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return 0;
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return PIPE_CONTEXT_PRIORITY_LOW |
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PIPE_CONTEXT_PRIORITY_MEDIUM |
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PIPE_CONTEXT_PRIORITY_HIGH;
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case PIPE_CAP_FENCE_SIGNAL:
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return sscreen->info.has_syncobj;
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case PIPE_CAP_CONSTBUF0_FLAGS:
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return SI_RESOURCE_FLAG_32BIT;
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case PIPE_CAP_NATIVE_FENCE_FD:
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return sscreen->info.has_fence_to_handle;
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case PIPE_CAP_DRAW_PARAMETERS:
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case PIPE_CAP_MULTI_DRAW_INDIRECT:
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case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
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return sscreen->has_draw_indirect_multi;
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case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
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return 30;
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case PIPE_CAP_MAX_VARYINGS:
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case PIPE_CAP_MAX_GS_INVOCATIONS:
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return 32;
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case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
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return sscreen->info.gfx_level <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
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/* Stream output. */
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case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
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case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
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return 32 * 4;
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/* Geometry shader output. */
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case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
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/* gfx9 has to report 256 to make piglit/gs-max-output pass.
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* gfx8 and earlier can do 1024.
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*/
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return 256;
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case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
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return 4095;
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case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
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return 2048;
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/* Texturing. */
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case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
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/* TODO: Gfx12 supports 64K textures, but Gallium can't represent them at the moment. */
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return sscreen->info.gfx_level >= GFX12 ? 32768 : 16384;
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case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
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if (!sscreen->info.has_3d_cube_border_color_mipmap)
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return 0;
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return sscreen->info.gfx_level >= GFX12 ? 16 : 15; /* 32K : 16K */
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case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
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if (!sscreen->info.has_3d_cube_border_color_mipmap)
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return 0;
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/* This is limited by maximums that both the texture unit and layered rendering support. */
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return sscreen->info.gfx_level >= GFX12 ? 15 : /* 16K */
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sscreen->info.gfx_level >= GFX10 ? 14 : 12; /* 8K : 2K */
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case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
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/* This is limited by maximums that both the texture unit and layered rendering support. */
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return sscreen->info.gfx_level >= GFX10 ? 8192 : 2048;
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/* Sparse texture */
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case PIPE_CAP_MAX_SPARSE_TEXTURE_SIZE:
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return enable_sparse ?
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si_get_param(pscreen, PIPE_CAP_MAX_TEXTURE_2D_SIZE) : 0;
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case PIPE_CAP_MAX_SPARSE_3D_TEXTURE_SIZE:
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return enable_sparse ?
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(1 << (si_get_param(pscreen, PIPE_CAP_MAX_TEXTURE_3D_LEVELS) - 1)) : 0;
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case PIPE_CAP_MAX_SPARSE_ARRAY_TEXTURE_LAYERS:
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return enable_sparse ?
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si_get_param(pscreen, PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS) : 0;
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case PIPE_CAP_SPARSE_TEXTURE_FULL_ARRAY_CUBE_MIPMAPS:
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case PIPE_CAP_QUERY_SPARSE_TEXTURE_RESIDENCY:
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case PIPE_CAP_CLAMP_SPARSE_TEXTURE_LOD:
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return enable_sparse;
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/* Viewports and render targets. */
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case PIPE_CAP_MAX_VIEWPORTS:
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return SI_MAX_VIEWPORTS;
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case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
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case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
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case PIPE_CAP_MAX_RENDER_TARGETS:
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return 8;
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case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
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return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
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case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
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case PIPE_CAP_MIN_TEXEL_OFFSET:
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return -32;
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case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
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case PIPE_CAP_MAX_TEXEL_OFFSET:
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return 31;
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case PIPE_CAP_ENDIANNESS:
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return PIPE_ENDIAN_LITTLE;
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case PIPE_CAP_VENDOR_ID:
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return ATI_VENDOR_ID;
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case PIPE_CAP_DEVICE_ID:
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return sscreen->info.pci_id;
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case PIPE_CAP_VIDEO_MEMORY:
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return sscreen->info.vram_size_kb >> 10;
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case PIPE_CAP_PCI_GROUP:
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return sscreen->info.pci.domain;
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case PIPE_CAP_PCI_BUS:
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return sscreen->info.pci.bus;
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case PIPE_CAP_PCI_DEVICE:
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return sscreen->info.pci.dev;
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case PIPE_CAP_PCI_FUNCTION:
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return sscreen->info.pci.func;
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case PIPE_CAP_TIMER_RESOLUTION:
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/* Conversion to nanos from cycles per millisecond */
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return DIV_ROUND_UP(1000000, sscreen->info.clock_crystal_freq);
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case PIPE_CAP_SHADER_SUBGROUP_SIZE:
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return 64;
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case PIPE_CAP_SHADER_SUBGROUP_SUPPORTED_STAGES:
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return BITFIELD_MASK(PIPE_SHADER_TYPES);
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case PIPE_CAP_SHADER_SUBGROUP_SUPPORTED_FEATURES:
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return BITFIELD_MASK(PIPE_SHADER_SUBGROUP_NUM_FEATURES);
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case PIPE_CAP_SHADER_SUBGROUP_QUAD_ALL_STAGES:
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return true;
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default:
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return u_pipe_screen_get_param_defaults(pscreen, param);
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}
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}
|
||||
|
||||
static float si_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
|
||||
{
|
||||
switch (param) {
|
||||
case PIPE_CAPF_MIN_LINE_WIDTH:
|
||||
case PIPE_CAPF_MIN_LINE_WIDTH_AA:
|
||||
return 1; /* due to axis-aligned end caps at line width 1 */
|
||||
case PIPE_CAPF_MIN_POINT_SIZE:
|
||||
case PIPE_CAPF_MIN_POINT_SIZE_AA:
|
||||
case PIPE_CAPF_POINT_SIZE_GRANULARITY:
|
||||
case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
|
||||
return 1.0 / 8.0; /* due to the register field precision */
|
||||
case PIPE_CAPF_MAX_LINE_WIDTH:
|
||||
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
|
||||
/* This depends on the quant mode, though the precise interactions
|
||||
* are unknown. */
|
||||
return 2048;
|
||||
case PIPE_CAPF_MAX_POINT_SIZE:
|
||||
case PIPE_CAPF_MAX_POINT_SIZE_AA:
|
||||
return SI_MAX_POINT_SIZE;
|
||||
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
|
||||
return 16.0f;
|
||||
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
|
||||
/* The hw can do 31, but this test fails if we use that:
|
||||
* KHR-GL46.texture_lod_bias.texture_lod_bias_all
|
||||
*/
|
||||
return 16;
|
||||
case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
|
||||
case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
|
||||
case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
|
||||
return 0.0f;
|
||||
}
|
||||
return 0.0f;
|
||||
}
|
||||
|
||||
static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader,
|
||||
enum pipe_shader_cap param)
|
||||
{
|
||||
|
|
@ -1513,10 +1108,8 @@ void si_init_screen_get_functions(struct si_screen *sscreen)
|
|||
sscreen->b.get_vendor = si_get_vendor;
|
||||
sscreen->b.get_device_vendor = si_get_device_vendor;
|
||||
sscreen->b.get_screen_fd = si_get_screen_fd;
|
||||
sscreen->b.get_param = si_get_param;
|
||||
sscreen->b.is_compute_copy_faster = si_is_compute_copy_faster;
|
||||
sscreen->b.driver_thread_add_job = si_driver_thread_add_job;
|
||||
sscreen->b.get_paramf = si_get_paramf;
|
||||
sscreen->b.get_compute_param = si_get_compute_param;
|
||||
sscreen->b.get_timestamp = si_get_timestamp;
|
||||
sscreen->b.get_shader_param = si_get_shader_param;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue