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anv: Fix CmdResetEvent2() with RESOURCE_BARRIER::Wait stage == none

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CmdResetEvent2() was calling anv_add_pending_pipe_bits() with no dst_stages
stages causing RESOURCE_BARRIER::Wait stage == none, what causes a GPU hang in
NVL-P simulator.

So here setting dst_stages to VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT and adding
an assert in resource_barrier_wait_stage() to catch hw_stage == 0.

This fixes crucible func.event.cmd_buffer.q0 in simulator.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40445>
This commit is contained in:
José Roberto de Souza 2026-03-16 12:06:40 -07:00 • committed by Marge Bot
parent 53706931bc
commit 10b5b279a4
1 changed files with 5 additions and 2 deletions
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7
src/intel/vulkan/genX_cmd_buffer.c
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@ -1824,8 +1824,9 @@ ALWAYS_INLINE static enum GENX(RESOURCE_BARRIER_STAGE)
resource_barrier_wait_stage(enum intel_engine_class engine_class,
const VkPipelineStageFlags2 vk_stages)
{
enum GENX(RESOURCE_BARRIER_STAGE) hw_stage = 0;
enum GENX(RESOURCE_BARRIER_STAGE) hw_stage = RESOURCE_BARRIER_STAGE_NONE;
assert(vk_stages != 0);
/* BSpec 56054, Wait Stage:
* "Hardware is only able to stall at the following stages:
* Top of the pipe (command parser)
@ -1876,6 +1877,7 @@ resource_barrier_wait_stage(enum intel_engine_class engine_class,
VK_PIPELINE_STAGE_2_CLEAR_BIT_KHR))
hw_stage = RESOURCE_BARRIER_STAGE_PIXEL;
assert(hw_stage != RESOURCE_BARRIER_STAGE_NONE);
return hw_stage;
}
@ -6914,7 +6916,8 @@ void genX(CmdResetEvent2)(
case INTEL_ENGINE_CLASS_RENDER:
case INTEL_ENGINE_CLASS_COMPUTE: {
anv_add_pending_pipe_bits(cmd_buffer,
stageMask, 0,
stageMask,
VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT,
ANV_PIPE_POST_SYNC_BIT,
"event reset");
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);