diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index c861ca7ff68..f73a74a47eb 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1824,8 +1824,9 @@ ALWAYS_INLINE static enum GENX(RESOURCE_BARRIER_STAGE)
 resource_barrier_wait_stage(enum intel_engine_class engine_class,
                             const VkPipelineStageFlags2 vk_stages)
 {
-   enum GENX(RESOURCE_BARRIER_STAGE) hw_stage = 0;
+   enum GENX(RESOURCE_BARRIER_STAGE) hw_stage = RESOURCE_BARRIER_STAGE_NONE;
 
+   assert(vk_stages != 0);
    /* BSpec 56054, Wait Stage:
     *   "Hardware is only able to stall at the following stages:
     *       Top of the pipe (command parser)
@@ -1876,6 +1877,7 @@ resource_barrier_wait_stage(enum intel_engine_class engine_class,
                          VK_PIPELINE_STAGE_2_CLEAR_BIT_KHR))
       hw_stage = RESOURCE_BARRIER_STAGE_PIXEL;
 
+   assert(hw_stage != RESOURCE_BARRIER_STAGE_NONE);
    return hw_stage;
 }
 
@@ -6914,7 +6916,8 @@ void genX(CmdResetEvent2)(
    case INTEL_ENGINE_CLASS_RENDER:
    case INTEL_ENGINE_CLASS_COMPUTE: {
       anv_add_pending_pipe_bits(cmd_buffer,
-                                stageMask, 0,
+                                stageMask,
+                                VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT,
                                 ANV_PIPE_POST_SYNC_BIT,
                                 "event reset");
       genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);