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iris: remove shader and compute get param
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33176>
This commit is contained in:
Qiang Yu
parent
5a3ac70015
commit
0f9f7152f7
1 changed files with 0 additions and 159 deletions
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@ -198,163 +198,6 @@ iris_get_video_memory(struct iris_screen *screen)
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}
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}
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static int
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iris_get_shader_param(struct pipe_screen *pscreen,
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enum pipe_shader_type p_stage,
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enum pipe_shader_cap param)
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{
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gl_shader_stage stage = stage_from_pipe(p_stage);
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if (p_stage == PIPE_SHADER_MESH ||
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p_stage == PIPE_SHADER_TASK)
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return 0;
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/* this is probably not totally correct.. but it's a start: */
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switch (param) {
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case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
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return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
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case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
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case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
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case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
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return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
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case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
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return UINT_MAX;
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case PIPE_SHADER_CAP_MAX_INPUTS:
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return stage == MESA_SHADER_VERTEX ? 16 : 32;
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case PIPE_SHADER_CAP_MAX_OUTPUTS:
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return 32;
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case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
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return 16 * 1024 * sizeof(float);
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case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
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return 16;
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case PIPE_SHADER_CAP_MAX_TEMPS:
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return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
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case PIPE_SHADER_CAP_CONT_SUPPORTED:
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return 0;
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case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
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case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
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/* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
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* which we don't want. Our compiler backend will check brw_compiler's
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* options and call nir_lower_indirect_derefs appropriately anyway.
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*/
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return true;
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case PIPE_SHADER_CAP_SUBROUTINES:
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return 0;
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case PIPE_SHADER_CAP_INTEGERS:
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return 1;
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case PIPE_SHADER_CAP_INT64_ATOMICS:
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case PIPE_SHADER_CAP_FP16:
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case PIPE_SHADER_CAP_FP16_DERIVATIVES:
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case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
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case PIPE_SHADER_CAP_INT16:
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case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
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return 0;
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case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
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return IRIS_MAX_SAMPLERS;
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case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
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return IRIS_MAX_TEXTURES;
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case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
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return IRIS_MAX_IMAGES;
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case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
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return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
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case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
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case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
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return 0;
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case PIPE_SHADER_CAP_SUPPORTED_IRS:
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return 1 << PIPE_SHADER_IR_NIR;
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case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
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case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
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return 0;
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default:
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unreachable("unknown shader param");
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}
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}
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static int
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iris_get_compute_param(struct pipe_screen *pscreen,
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enum pipe_compute_cap param,
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void *ret)
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{
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struct iris_screen *screen = (struct iris_screen *)pscreen;
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const struct intel_device_info *devinfo = screen->devinfo;
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const uint32_t max_invocations =
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MIN2(1024, 32 * devinfo->max_cs_workgroup_threads);
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#define RET(x) do { \
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if (ret) \
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memcpy(ret, x, sizeof(x)); \
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return sizeof(x); \
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} while (0)
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switch (param) {
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case PIPE_COMPUTE_CAP_ADDRESS_BITS:
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/* This gets queried on OpenCL device init and is never queried by the
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* OpenGL state tracker.
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*/
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iris_warn_cl();
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RET((uint32_t []){ 64 });
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case PIPE_COMPUTE_CAP_IR_TARGET:
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if (ret)
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strcpy(ret, "gen");
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return 4;
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case PIPE_COMPUTE_CAP_GRID_DIMENSION:
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RET((uint64_t []) { 3 });
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case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
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RET(((uint64_t []) { UINT32_MAX, UINT32_MAX, UINT32_MAX }));
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case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
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/* MaxComputeWorkGroupSize[0..2] */
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RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
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case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
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/* MaxComputeWorkGroupInvocations */
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case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
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/* MaxComputeVariableGroupInvocations */
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RET((uint64_t []) { max_invocations });
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case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
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/* MaxComputeSharedMemorySize */
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RET((uint64_t []) { 64 * 1024 });
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case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
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RET((uint32_t []) { 1 });
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case PIPE_COMPUTE_CAP_SUBGROUP_SIZES:
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RET((uint32_t []) { 32 | 16 | 8 });
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case PIPE_COMPUTE_CAP_MAX_SUBGROUPS:
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RET((uint32_t []) { devinfo->max_cs_workgroup_threads });
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case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
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case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
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RET((uint64_t []) { 1 << 30 }); /* TODO */
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case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
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RET((uint32_t []) { 400 }); /* TODO */
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case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: {
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RET((uint32_t []) { intel_device_info_subslice_total(devinfo) });
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}
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case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
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/* MaxComputeSharedMemorySize */
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RET((uint64_t []) { 64 * 1024 });
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case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
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/* We could probably allow more; this is the OpenCL minimum */
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RET((uint64_t []) { 1024 });
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default:
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unreachable("unknown compute param");
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}
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}
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static void
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iris_init_shader_caps(struct iris_screen *screen)
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{
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@ -927,8 +770,6 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
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pscreen->get_device_vendor = iris_get_device_vendor;
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pscreen->get_cl_cts_version = iris_get_cl_cts_version;
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pscreen->get_screen_fd = iris_screen_get_fd;
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pscreen->get_shader_param = iris_get_shader_param;
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pscreen->get_compute_param = iris_get_compute_param;
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pscreen->get_compiler_options = iris_get_compiler_options;
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pscreen->get_device_uuid = iris_get_device_uuid;
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pscreen->get_driver_uuid = iris_get_driver_uuid;
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