From 0f9f7152f79fe6a396f0fa789d9114ddf6267157 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 21 Jan 2025 19:00:36 +0800 Subject: [PATCH] iris: remove shader and compute get param MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Acked-by: Alyssa Rosenzweig Acked-by: Marek Olšák Part-of: --- src/gallium/drivers/iris/iris_screen.c | 159 ------------------------- 1 file changed, 159 deletions(-) diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c index 6dd154d7e9c..b0c84de20d7 100644 --- a/src/gallium/drivers/iris/iris_screen.c +++ b/src/gallium/drivers/iris/iris_screen.c @@ -198,163 +198,6 @@ iris_get_video_memory(struct iris_screen *screen) } } -static int -iris_get_shader_param(struct pipe_screen *pscreen, - enum pipe_shader_type p_stage, - enum pipe_shader_cap param) -{ - gl_shader_stage stage = stage_from_pipe(p_stage); - - if (p_stage == PIPE_SHADER_MESH || - p_stage == PIPE_SHADER_TASK) - return 0; - - /* this is probably not totally correct.. but it's a start: */ - switch (param) { - case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: - return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384; - case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: - case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: - case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: - return stage == MESA_SHADER_FRAGMENT ? 1024 : 0; - - case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: - return UINT_MAX; - - case PIPE_SHADER_CAP_MAX_INPUTS: - return stage == MESA_SHADER_VERTEX ? 16 : 32; - case PIPE_SHADER_CAP_MAX_OUTPUTS: - return 32; - case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE: - return 16 * 1024 * sizeof(float); - case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: - return 16; - case PIPE_SHADER_CAP_MAX_TEMPS: - return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */ - case PIPE_SHADER_CAP_CONT_SUPPORTED: - return 0; - case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: - case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: - /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects, - * which we don't want. Our compiler backend will check brw_compiler's - * options and call nir_lower_indirect_derefs appropriately anyway. - */ - return true; - case PIPE_SHADER_CAP_SUBROUTINES: - return 0; - case PIPE_SHADER_CAP_INTEGERS: - return 1; - case PIPE_SHADER_CAP_INT64_ATOMICS: - case PIPE_SHADER_CAP_FP16: - case PIPE_SHADER_CAP_FP16_DERIVATIVES: - case PIPE_SHADER_CAP_FP16_CONST_BUFFERS: - case PIPE_SHADER_CAP_INT16: - case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: - return 0; - case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: - return IRIS_MAX_SAMPLERS; - case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: - return IRIS_MAX_TEXTURES; - case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: - return IRIS_MAX_IMAGES; - case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: - return IRIS_MAX_ABOS + IRIS_MAX_SSBOS; - case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: - case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: - return 0; - case PIPE_SHADER_CAP_SUPPORTED_IRS: - return 1 << PIPE_SHADER_IR_NIR; - case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: - case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: - return 0; - default: - unreachable("unknown shader param"); - } -} - -static int -iris_get_compute_param(struct pipe_screen *pscreen, - enum pipe_compute_cap param, - void *ret) -{ - struct iris_screen *screen = (struct iris_screen *)pscreen; - const struct intel_device_info *devinfo = screen->devinfo; - - const uint32_t max_invocations = - MIN2(1024, 32 * devinfo->max_cs_workgroup_threads); - -#define RET(x) do { \ - if (ret) \ - memcpy(ret, x, sizeof(x)); \ - return sizeof(x); \ -} while (0) - - switch (param) { - case PIPE_COMPUTE_CAP_ADDRESS_BITS: - /* This gets queried on OpenCL device init and is never queried by the - * OpenGL state tracker. - */ - iris_warn_cl(); - RET((uint32_t []){ 64 }); - - case PIPE_COMPUTE_CAP_IR_TARGET: - if (ret) - strcpy(ret, "gen"); - return 4; - - case PIPE_COMPUTE_CAP_GRID_DIMENSION: - RET((uint64_t []) { 3 }); - - case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: - RET(((uint64_t []) { UINT32_MAX, UINT32_MAX, UINT32_MAX })); - - case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: - /* MaxComputeWorkGroupSize[0..2] */ - RET(((uint64_t []) {max_invocations, max_invocations, max_invocations})); - - case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: - /* MaxComputeWorkGroupInvocations */ - case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: - /* MaxComputeVariableGroupInvocations */ - RET((uint64_t []) { max_invocations }); - - case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: - /* MaxComputeSharedMemorySize */ - RET((uint64_t []) { 64 * 1024 }); - - case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED: - RET((uint32_t []) { 1 }); - - case PIPE_COMPUTE_CAP_SUBGROUP_SIZES: - RET((uint32_t []) { 32 | 16 | 8 }); - - case PIPE_COMPUTE_CAP_MAX_SUBGROUPS: - RET((uint32_t []) { devinfo->max_cs_workgroup_threads }); - - case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE: - case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: - RET((uint64_t []) { 1 << 30 }); /* TODO */ - - case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY: - RET((uint32_t []) { 400 }); /* TODO */ - - case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: { - RET((uint32_t []) { intel_device_info_subslice_total(devinfo) }); - } - - case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: - /* MaxComputeSharedMemorySize */ - RET((uint64_t []) { 64 * 1024 }); - - case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: - /* We could probably allow more; this is the OpenCL minimum */ - RET((uint64_t []) { 1024 }); - - default: - unreachable("unknown compute param"); - } -} - static void iris_init_shader_caps(struct iris_screen *screen) { @@ -927,8 +770,6 @@ iris_screen_create(int fd, const struct pipe_screen_config *config) pscreen->get_device_vendor = iris_get_device_vendor; pscreen->get_cl_cts_version = iris_get_cl_cts_version; pscreen->get_screen_fd = iris_screen_get_fd; - pscreen->get_shader_param = iris_get_shader_param; - pscreen->get_compute_param = iris_get_compute_param; pscreen->get_compiler_options = iris_get_compiler_options; pscreen->get_device_uuid = iris_get_device_uuid; pscreen->get_driver_uuid = iris_get_driver_uuid;