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freedreno/a6xx: Fix layered lrz

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Don't hard-code to a single layer, and fix lrz (slow) clear path to
account for the # of layers.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5582
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38930>
This commit is contained in:
Rob Clark 2025-12-16 10:13:44 -08:00 • committed by Marge Bot
parent 14a23e8b3e
commit 0e82a8d759
4 changed files with 16 additions and 8 deletions
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4
src/freedreno/ci/freedreno-a618-fails.txt
View file

@ -2,10 +2,6 @@ KHR-GL46.shader_image_load_store.basic-allFormats-store,Fail
KHR-GL46.shader_image_load_store.basic-allTargets-store,Fail
KHR-GL46.shading_language_420pack.binding_images,Fail
# https://gitlab.freedesktop.org/mesa/mesa/-/issues/5582
KHR-GLES31.core.texture_cube_map_array.color_depth_attachments,Fail
KHR-GL46.texture_cube_map_array.color_depth_attachments,Fail
#
# new fails with gl45:
#

2
src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc
View file

@ -808,7 +808,7 @@ clear_lrz_setup(fd_cs &cs, struct fd_resource *zsbuf, struct fd_bo *lrz, double
ncrb.add(GRAS_A2D_DEST_TL(CHIP, .x = 0, .y = 0));
ncrb.add(GRAS_A2D_DEST_BR(CHIP,
.x = zsbuf->lrz_layout.lrz_pitch - 1,
.y = zsbuf->lrz_layout.lrz_height - 1,
.y = zsbuf->lrz_layout.lrz_height * zsbuf->b.b.array_size - 1,
));
union pipe_color_union clear_color = { .f = {depth} };

11
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -237,10 +237,11 @@ emit_lrz(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *subpass)
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
if (!subpass->lrz) {
fd_crb crb(cs, 7);
fd_crb crb(cs, 8);
crb.add(GRAS_LRZ_BUFFER_BASE(CHIP));
crb.add(GRAS_LRZ_BUFFER_PITCH(CHIP));
crb.add(A6XX_GRAS_LRZ_VIEW_INFO());
crb.add(A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE());
if (CHIP >= A7XX) {
@ -259,7 +260,7 @@ emit_lrz(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *subpass)
*/
fd6_event_write<CHIP>(batch->ctx, cs, FD_LRZ_FLUSH);
fd_crb crb(cs, 7);
fd_crb crb(cs, 8);
struct fd_resource *zsbuf = fd_resource(pfb->zsbuf.texture);
@ -268,6 +269,12 @@ emit_lrz(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *subpass)
crb.add(GRAS_LRZ_BUFFER_BASE(CHIP, .bo = subpass->lrz));
crb.add(GRAS_LRZ_BUFFER_PITCH(CHIP,
.pitch = zsbuf->lrz_layout.lrz_pitch * sizeof(uint16_t),
.array_pitch = zsbuf->lrz_layout.lrz_layer_size,
));
crb.add(A6XX_GRAS_LRZ_VIEW_INFO(
.base_layer = pfb->zsbuf.first_layer,
.layer_count = pfb->zsbuf.last_layer - pfb->zsbuf.first_layer + 1,
.base_mip_level = pfb->zsbuf.level,
));
crb.add(A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(
.bo = zsbuf->lrz_layout.lrz_fc_size ? subpass->lrz : NULL,

7
src/gallium/drivers/freedreno/a6xx/fd6_resource.cc
View file

@ -234,10 +234,15 @@ static void
setup_lrz(struct fd_resource *rsc)
{
struct fd_screen *screen = fd_screen(rsc->b.b.screen);
uint32_t nr_layers = 1;
uint32_t nr_layers = rsc->b.b.array_size;
assert(nr_layers);
fdl6_lrz_layout_init<CHIP>(&rsc->lrz_layout, &rsc->layout, 0, 0,
screen->info, 0, nr_layers);
if (!rsc->lrz_layout.lrz_total_size)
return;
rsc->lrz = fd_bo_new(screen->dev, rsc->lrz_layout.lrz_total_size,
FD_BO_NOMAP, "lrz");
}