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nir: Add nir_texop_resinfo_intel

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This is a combination of txs and query_levels in a single vec4 result.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40451>
This commit is contained in:
Kenneth Graunke 2026-03-14 02:51:15 -07:00 • committed by Marge Bot
parent e7077e8f5c
commit 0e143ae663
5 changed files with 14 additions and 0 deletions
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5
src/compiler/nir/nir.c
View file

@ -3381,6 +3381,7 @@ nir_tex_instr_need_sampler(const nir_tex_instr *instr)
case nir_texop_image_min_lod_agx:
case nir_texop_fragment_mask_fetch_amd:
case nir_texop_fragment_fetch_amd:
case nir_texop_resinfo_intel:
return false;
default:
return true;
@ -3450,6 +3451,9 @@ nir_tex_instr_result_size(const nir_tex_instr *instr)
case nir_texop_block_match_ssd_qcom:
return 4;
case nir_texop_resinfo_intel:
return 4;
default:
if (instr->is_shadow && instr->is_new_style_shadow)
return 1;
@ -3475,6 +3479,7 @@ nir_tex_instr_is_query(const nir_tex_instr *instr)
case nir_texop_hdr_dim_nv:
case nir_texop_tex_type_nv:
case nir_texop_sample_pos_nv:
case nir_texop_resinfo_intel:
return true;
case nir_texop_tex:
case nir_texop_txb:

2
src/compiler/nir/nir.h
View file

@ -2490,6 +2490,8 @@ typedef enum nir_texop {
*/
nir_texop_block_match_sad_qcom,
nir_texop_block_match_ssd_qcom,
/** txs in .xyz and query_levels in .w */
nir_texop_resinfo_intel,
} nir_texop;
/** Represents a texture instruction */

1
src/compiler/nir/nir_builder.c
View file

@ -310,6 +310,7 @@ nir_build_tex_struct(nir_builder *build, nir_texop op, struct nir_tex_builder f)
case nir_texop_txf_ms_mcs_intel:
case nir_texop_fragment_mask_fetch_amd:
case nir_texop_descriptor_amd:
case nir_texop_resinfo_intel:
tex->dest_type = nir_type_int32;
break;
case nir_texop_lod:

3
src/compiler/nir/nir_print.c
View file

@ -1981,6 +1981,9 @@ print_tex_instr(nir_tex_instr *instr, print_state *state)
case nir_texop_block_match_ssd_qcom:
fprintf(fp, "block_match_ssd_qcom ");
break;
case nir_texop_resinfo_intel:
fprintf(fp, "resinfo_intel ");
break;
default:
UNREACHABLE("Invalid texture operation");
break;

3
src/compiler/spirv/spirv_to_nir.c
View file

@ -3651,6 +3651,9 @@ vtn_handle_texture(struct vtn_builder *b, SpvOp opcode,
case nir_texop_sample_pos_nv:
vtn_fail("unexpected nir_texop_*_nv");
break;
case nir_texop_resinfo_intel:
vtn_fail("unexpected nir_texop_resinfo_intel");
break;
}
unsigned idx = 4;