From 0e143ae663cd9a3cb5e7031ef829048cc8089805 Mon Sep 17 00:00:00 2001
From: Kenneth Graunke <kenneth@whitecape.org>
Date: Sat, 14 Mar 2026 02:51:15 -0700
Subject: [PATCH] nir: Add nir_texop_resinfo_intel

This is a combination of txs and query_levels in a single vec4 result.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40451>
---
 src/compiler/nir/nir.c            | 5 +++++
 src/compiler/nir/nir.h            | 2 ++
 src/compiler/nir/nir_builder.c    | 1 +
 src/compiler/nir/nir_print.c      | 3 +++
 src/compiler/spirv/spirv_to_nir.c | 3 +++
 5 files changed, 14 insertions(+)

diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index 0e5693b0cb4..5c9515aff76 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -3381,6 +3381,7 @@ nir_tex_instr_need_sampler(const nir_tex_instr *instr)
    case nir_texop_image_min_lod_agx:
    case nir_texop_fragment_mask_fetch_amd:
    case nir_texop_fragment_fetch_amd:
+   case nir_texop_resinfo_intel:
       return false;
    default:
       return true;
@@ -3450,6 +3451,9 @@ nir_tex_instr_result_size(const nir_tex_instr *instr)
    case nir_texop_block_match_ssd_qcom:
       return 4;
 
+   case nir_texop_resinfo_intel:
+      return 4;
+
    default:
       if (instr->is_shadow && instr->is_new_style_shadow)
          return 1;
@@ -3475,6 +3479,7 @@ nir_tex_instr_is_query(const nir_tex_instr *instr)
    case nir_texop_hdr_dim_nv:
    case nir_texop_tex_type_nv:
    case nir_texop_sample_pos_nv:
+   case nir_texop_resinfo_intel:
       return true;
    case nir_texop_tex:
    case nir_texop_txb:
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index d37a521c543..16dde94de74 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2490,6 +2490,8 @@ typedef enum nir_texop {
    */
    nir_texop_block_match_sad_qcom,
    nir_texop_block_match_ssd_qcom,
+   /** txs in .xyz and query_levels in .w */
+   nir_texop_resinfo_intel,
 } nir_texop;
 
 /** Represents a texture instruction */
diff --git a/src/compiler/nir/nir_builder.c b/src/compiler/nir/nir_builder.c
index 8ccc7c47381..b9753017b9a 100644
--- a/src/compiler/nir/nir_builder.c
+++ b/src/compiler/nir/nir_builder.c
@@ -310,6 +310,7 @@ nir_build_tex_struct(nir_builder *build, nir_texop op, struct nir_tex_builder f)
    case nir_texop_txf_ms_mcs_intel:
    case nir_texop_fragment_mask_fetch_amd:
    case nir_texop_descriptor_amd:
+   case nir_texop_resinfo_intel:
       tex->dest_type = nir_type_int32;
       break;
    case nir_texop_lod:
diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c
index 31cb16de822..8cdfcdb6cb0 100644
--- a/src/compiler/nir/nir_print.c
+++ b/src/compiler/nir/nir_print.c
@@ -1981,6 +1981,9 @@ print_tex_instr(nir_tex_instr *instr, print_state *state)
    case nir_texop_block_match_ssd_qcom:
       fprintf(fp, "block_match_ssd_qcom ");
       break;
+   case nir_texop_resinfo_intel:
+      fprintf(fp, "resinfo_intel ");
+      break;
    default:
       UNREACHABLE("Invalid texture operation");
       break;
diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c
index 6d855db38fd..847c11062f5 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -3651,6 +3651,9 @@ vtn_handle_texture(struct vtn_builder *b, SpvOp opcode,
    case nir_texop_sample_pos_nv:
       vtn_fail("unexpected nir_texop_*_nv");
       break;
+   case nir_texop_resinfo_intel:
+      vtn_fail("unexpected nir_texop_resinfo_intel");
+      break;
    }
 
    unsigned idx = 4;