fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-04 02:40:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: move radv_hash_shaders() to radv_graphics_pipeline.c

Browse source 
And rename it for consistency with compute/RT hash functions.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30045>
This commit is contained in:
Samuel Pitoiset 2024-07-04 15:13:34 +02:00 • committed by Marge Bot
parent b51af513dd
commit 0c0ecc90c4
3 changed files with 26 additions and 30 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

24
src/amd/vulkan/radv_pipeline_cache.c
View file

@ -22,30 +22,6 @@
#include "vk_pipeline.h"
#include "vk_util.h"
void
radv_hash_shaders(const struct radv_device *device, unsigned char *hash, const struct radv_shader_stage *stages,
uint32_t stage_count, const struct radv_pipeline_layout *layout,
const struct radv_graphics_state_key *gfx_state)
{
struct mesa_sha1 ctx;
_mesa_sha1_init(&ctx);
radv_pipeline_hash(device, layout, &ctx);
if (gfx_state)
_mesa_sha1_update(&ctx, gfx_state, sizeof(*gfx_state));
for (unsigned s = 0; s < stage_count; s++) {
if (!stages[s].entrypoint)
continue;
_mesa_sha1_update(&ctx, stages[s].shader_sha1, sizeof(stages[s].shader_sha1));
_mesa_sha1_update(&ctx, &stages[s].key, sizeof(stages[s].key));
}
_mesa_sha1_final(&ctx, hash);
}
void
radv_hash_graphics_spirv_to_nir(blake3_hash hash, const struct radv_shader_stage *stage,
const struct radv_spirv_to_nir_options *options)

4
src/amd/vulkan/radv_pipeline_cache.h
View file

@ -30,10 +30,6 @@ struct radv_shader_binary;
struct radv_shader_stage;
struct radv_spirv_to_nir_options;
void radv_hash_shaders(const struct radv_device *device, unsigned char *hash, const struct radv_shader_stage *stages,
uint32_t stage_count, const struct radv_pipeline_layout *layout,
const struct radv_graphics_state_key *gfx_state);
void radv_hash_graphics_spirv_to_nir(blake3_hash hash, const struct radv_shader_stage *stage,
const struct radv_spirv_to_nir_options *options);

28
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -2559,6 +2559,30 @@ radv_should_compute_pipeline_hash(const struct radv_device *device, const struct
((instance->vk.trace_mode & RADV_TRACE_MODE_RGP) && pipeline->base.type == RADV_PIPELINE_GRAPHICS);
}
static void
radv_graphics_pipeline_hash(const struct radv_device *device, const struct radv_shader_stage *stages,
uint32_t stage_count, const struct radv_pipeline_layout *layout,
const struct radv_graphics_state_key *gfx_state, unsigned char *hash)
{
struct mesa_sha1 ctx;
_mesa_sha1_init(&ctx);
radv_pipeline_hash(device, layout, &ctx);
if (gfx_state)
_mesa_sha1_update(&ctx, gfx_state, sizeof(*gfx_state));
for (unsigned s = 0; s < stage_count; s++) {
if (!stages[s].entrypoint)
continue;
_mesa_sha1_update(&ctx, stages[s].shader_sha1, sizeof(stages[s].shader_sha1));
_mesa_sha1_update(&ctx, &stages[s].key, sizeof(stages[s].key));
}
_mesa_sha1_final(&ctx, hash);
}
static VkResult
radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo,
struct radv_pipeline_layout *pipeline_layout, struct radv_device *device,
@ -2603,8 +2627,8 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk
radv_pipeline_load_retained_shaders(device, pCreateInfo, stages);
if (radv_should_compute_pipeline_hash(device, pipeline, fast_linking_enabled)) {
radv_hash_shaders(device, pipeline->base.sha1, stages, MESA_VULKAN_SHADER_STAGES, pipeline_layout,
&pipeline_key->gfx_state);
radv_graphics_pipeline_hash(device, stages, MESA_VULKAN_SHADER_STAGES, pipeline_layout, &pipeline_key->gfx_state,
pipeline->base.sha1);
pipeline->base.pipeline_hash = *(uint64_t *)pipeline->base.sha1;
}