From 0c0ecc90c46dfcdebf489cf5528eb53a67036efa Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 4 Jul 2024 15:13:34 +0200 Subject: [PATCH] radv: move radv_hash_shaders() to radv_graphics_pipeline.c And rename it for consistency with compute/RT hash functions. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_pipeline_cache.c | 24 --------------------- src/amd/vulkan/radv_pipeline_cache.h | 4 ---- src/amd/vulkan/radv_pipeline_graphics.c | 28 +++++++++++++++++++++++-- 3 files changed, 26 insertions(+), 30 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline_cache.c b/src/amd/vulkan/radv_pipeline_cache.c index 24dee875009..fd339154895 100644 --- a/src/amd/vulkan/radv_pipeline_cache.c +++ b/src/amd/vulkan/radv_pipeline_cache.c @@ -22,30 +22,6 @@ #include "vk_pipeline.h" #include "vk_util.h" -void -radv_hash_shaders(const struct radv_device *device, unsigned char *hash, const struct radv_shader_stage *stages, - uint32_t stage_count, const struct radv_pipeline_layout *layout, - const struct radv_graphics_state_key *gfx_state) -{ - struct mesa_sha1 ctx; - - _mesa_sha1_init(&ctx); - - radv_pipeline_hash(device, layout, &ctx); - - if (gfx_state) - _mesa_sha1_update(&ctx, gfx_state, sizeof(*gfx_state)); - - for (unsigned s = 0; s < stage_count; s++) { - if (!stages[s].entrypoint) - continue; - - _mesa_sha1_update(&ctx, stages[s].shader_sha1, sizeof(stages[s].shader_sha1)); - _mesa_sha1_update(&ctx, &stages[s].key, sizeof(stages[s].key)); - } - _mesa_sha1_final(&ctx, hash); -} - void radv_hash_graphics_spirv_to_nir(blake3_hash hash, const struct radv_shader_stage *stage, const struct radv_spirv_to_nir_options *options) diff --git a/src/amd/vulkan/radv_pipeline_cache.h b/src/amd/vulkan/radv_pipeline_cache.h index b93ff517096..747ff5bacdc 100644 --- a/src/amd/vulkan/radv_pipeline_cache.h +++ b/src/amd/vulkan/radv_pipeline_cache.h @@ -30,10 +30,6 @@ struct radv_shader_binary; struct radv_shader_stage; struct radv_spirv_to_nir_options; -void radv_hash_shaders(const struct radv_device *device, unsigned char *hash, const struct radv_shader_stage *stages, - uint32_t stage_count, const struct radv_pipeline_layout *layout, - const struct radv_graphics_state_key *gfx_state); - void radv_hash_graphics_spirv_to_nir(blake3_hash hash, const struct radv_shader_stage *stage, const struct radv_spirv_to_nir_options *options); diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index cb2d993285f..76c7da8f61d 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -2559,6 +2559,30 @@ radv_should_compute_pipeline_hash(const struct radv_device *device, const struct ((instance->vk.trace_mode & RADV_TRACE_MODE_RGP) && pipeline->base.type == RADV_PIPELINE_GRAPHICS); } +static void +radv_graphics_pipeline_hash(const struct radv_device *device, const struct radv_shader_stage *stages, + uint32_t stage_count, const struct radv_pipeline_layout *layout, + const struct radv_graphics_state_key *gfx_state, unsigned char *hash) +{ + struct mesa_sha1 ctx; + + _mesa_sha1_init(&ctx); + radv_pipeline_hash(device, layout, &ctx); + + if (gfx_state) + _mesa_sha1_update(&ctx, gfx_state, sizeof(*gfx_state)); + + for (unsigned s = 0; s < stage_count; s++) { + if (!stages[s].entrypoint) + continue; + + _mesa_sha1_update(&ctx, stages[s].shader_sha1, sizeof(stages[s].shader_sha1)); + _mesa_sha1_update(&ctx, &stages[s].key, sizeof(stages[s].key)); + } + + _mesa_sha1_final(&ctx, hash); +} + static VkResult radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo, struct radv_pipeline_layout *pipeline_layout, struct radv_device *device, @@ -2603,8 +2627,8 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk radv_pipeline_load_retained_shaders(device, pCreateInfo, stages); if (radv_should_compute_pipeline_hash(device, pipeline, fast_linking_enabled)) { - radv_hash_shaders(device, pipeline->base.sha1, stages, MESA_VULKAN_SHADER_STAGES, pipeline_layout, - &pipeline_key->gfx_state); + radv_graphics_pipeline_hash(device, stages, MESA_VULKAN_SHADER_STAGES, pipeline_layout, &pipeline_key->gfx_state, + pipeline->base.sha1); pipeline->base.pipeline_hash = *(uint64_t *)pipeline->base.sha1; }