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intel/dev/xe: Fix access to eu_per_dss_mask

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DRM_XE_TOPO_EU_PER_DSS and DRM_XE_TOPO_SIMD16_EU_PER_DSS can be any
number of bytes long but it was assuming it was always 4 bytes long.
That was not a issue because Xe KMD return 4 bytes even if only needs
1 or 2 bytes but that is a problem with our HW simulator that was
returning 2 bytes.

Fixes: a24d93aa89 ("intel/dev: Query and compute hardware topology for Xe")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32307>
This commit is contained in:
José Roberto de Souza 2024-11-22 09:06:21 -08:00 • committed by Marge Bot
parent 371b7a9b0d
commit 04bdbeec31
1 changed files with 7 additions and 5 deletions
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12
src/intel/dev/xe/intel_device_info.c
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@ -186,7 +186,7 @@ static void
xe_compute_topology(struct intel_device_info * devinfo, xe_compute_topology(struct intel_device_info * devinfo,
const uint8_t *geo_dss_mask, const uint8_t *geo_dss_mask,
const uint32_t geo_dss_num_bytes, const uint32_t geo_dss_num_bytes,
const uint32_t *eu_per_dss_mask, const uint32_t eu_per_dss_mask,
const unsigned l3_banks) const unsigned l3_banks)
{ {
intel_device_info_topology_reset_masks(devinfo); intel_device_info_topology_reset_masks(devinfo);
@ -201,7 +201,7 @@ xe_compute_topology(struct intel_device_info * devinfo,
devinfo->max_slices = 1; devinfo->max_slices = 1;
devinfo->max_subslices_per_slice = 6; devinfo->max_subslices_per_slice = 6;
} }
devinfo->max_eus_per_subslice = __builtin_popcount(*eu_per_dss_mask); devinfo->max_eus_per_subslice = __builtin_popcount(eu_per_dss_mask);
devinfo->subslice_slice_stride = DIV_ROUND_UP(devinfo->max_slices, 8); devinfo->subslice_slice_stride = DIV_ROUND_UP(devinfo->max_slices, 8);
devinfo->eu_slice_stride = DIV_ROUND_UP(devinfo->max_eus_per_subslice * devinfo->max_subslices_per_slice, 8); devinfo->eu_slice_stride = DIV_ROUND_UP(devinfo->max_eus_per_subslice * devinfo->max_subslices_per_slice, 8);
devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->max_eus_per_subslice, 8); devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->max_eus_per_subslice, 8);
@ -236,7 +236,7 @@ xe_compute_topology(struct intel_device_info * devinfo,
for (uint32_t dss = 0; dss < devinfo->max_subslices_per_slice; dss++) { for (uint32_t dss = 0; dss < devinfo->max_subslices_per_slice; dss++) {
if ((1u << dss) & slices[s].dss_mask) { if ((1u << dss) & slices[s].dss_mask) {
slices[s].dual_subslice[dss].enabled = true; slices[s].dual_subslice[dss].enabled = true;
slices[s].dual_subslice[dss].eu_mask = *eu_per_dss_mask; slices[s].dual_subslice[dss].eu_mask = eu_per_dss_mask;
} }
} }
} }
@ -285,7 +285,7 @@ xe_query_topology(int fd, struct intel_device_info *devinfo)
if (!topology) if (!topology)
return false; return false;
uint32_t geo_dss_num_bytes = 0, *eu_per_dss_mask = NULL; uint32_t geo_dss_num_bytes = 0, eu_per_dss_mask = 0;
uint8_t *geo_dss_mask = NULL, *tmp; uint8_t *geo_dss_mask = NULL, *tmp;
unsigned l3_banks = 0; unsigned l3_banks = 0;
const struct drm_xe_query_topology_mask *head = topology; const struct drm_xe_query_topology_mask *head = topology;
@ -306,7 +306,9 @@ xe_query_topology(int fd, struct intel_device_info *devinfo)
break; break;
case DRM_XE_TOPO_EU_PER_DSS: case DRM_XE_TOPO_EU_PER_DSS:
case DRM_XE_TOPO_SIMD16_EU_PER_DSS: case DRM_XE_TOPO_SIMD16_EU_PER_DSS:
eu_per_dss_mask = (uint32_t *)topology->mask; assert(topology->num_bytes <= sizeof(uint32_t));
for (int i = 0; i < topology->num_bytes; i++)
eu_per_dss_mask |= topology->mask[i] << (8 * i);
break; break;
} }
} }