2015-04-28 17:43:16 -07:00
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/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef _NIR_SPIRV_H_
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#define _NIR_SPIRV_H_
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2020-10-06 11:26:07 -05:00
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#include "util/disk_cache.h"
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2017-12-06 09:57:18 +01:00
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#include "compiler/nir/nir.h"
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2017-12-07 09:38:41 +01:00
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#include "compiler/shader_info.h"
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2015-04-28 17:43:16 -07:00
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2015-06-24 19:01:10 -07:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2016-01-12 16:28:28 -08:00
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struct nir_spirv_specialization {
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uint32_t id;
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2020-04-22 14:05:13 -05:00
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nir_const_value value;
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2018-01-18 12:31:52 +01:00
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bool defined_on_module;
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2016-01-12 16:28:28 -08:00
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};
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2017-08-16 16:04:08 -07:00
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enum nir_spirv_debug_level {
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2021-06-17 10:17:26 +01:00
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NIR_SPIRV_DEBUG_LEVEL_INVALID = -1,
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2017-08-16 16:04:08 -07:00
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NIR_SPIRV_DEBUG_LEVEL_INFO,
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NIR_SPIRV_DEBUG_LEVEL_WARNING,
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NIR_SPIRV_DEBUG_LEVEL_ERROR,
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};
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2019-03-21 22:37:50 -07:00
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enum nir_spirv_execution_environment {
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NIR_SPIRV_VULKAN = 0,
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NIR_SPIRV_OPENCL,
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NIR_SPIRV_OPENGL,
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};
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2017-10-18 17:28:19 -07:00
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struct spirv_to_nir_options {
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2019-03-21 22:37:50 -07:00
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enum nir_spirv_execution_environment environment;
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2020-06-30 13:47:22 +02:00
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/* Whether to keep ViewIndex as an input instead of rewriting to a sysval.
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*/
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bool view_index_is_input;
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2019-11-18 16:39:09 +10:00
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/* Create a nir library. */
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bool create_library;
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2020-11-13 15:08:10 -08:00
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/* Initial value for shader_info::float_controls_execution_mode,
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* indicates hardware requirements rather than shader author intent
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*/
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2023-09-20 14:44:28 -04:00
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uint32_t float_controls_execution_mode;
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2020-11-13 15:08:10 -08:00
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2022-07-07 13:29:08 -05:00
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/* Initial subgroup size. This may be overwritten for CL kernels */
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enum gl_subgroup_size subgroup_size;
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2022-04-26 16:29:04 -07:00
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/* True if RelaxedPrecision-decorated ALU result values should be performed
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* with 16-bit math.
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*/
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bool mediump_16bit_alu;
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/* When mediump_16bit_alu is set, determines whether nir_op_fddx/fddy can be
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* performed in 16-bit math.
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*/
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bool mediump_16bit_derivatives;
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2024-04-24 09:16:31 -05:00
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/* These really early AMD extensions don't have capabilities */
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bool amd_gcn_shader;
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bool amd_shader_ballot;
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bool amd_trinary_minmax;
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bool amd_shader_explicit_vertex_parameter;
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2017-12-07 09:38:41 +01:00
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struct spirv_supported_capabilities caps;
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2017-08-16 16:04:08 -07:00
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2019-05-01 14:15:32 -07:00
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/* Address format for various kinds of pointers. */
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nir_address_format ubo_addr_format;
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nir_address_format ssbo_addr_format;
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nir_address_format phys_ssbo_addr_format;
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nir_address_format push_const_addr_format;
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nir_address_format shared_addr_format;
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2022-02-08 02:59:31 +01:00
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nir_address_format task_payload_addr_format;
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2019-05-01 14:15:32 -07:00
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nir_address_format global_addr_format;
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nir_address_format temp_addr_format;
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2020-08-18 15:30:26 -05:00
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nir_address_format constant_addr_format;
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2018-11-28 15:20:03 -06:00
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2023-01-31 17:48:52 -06:00
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/** Minimum UBO alignment.
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*
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* This should match VkPhysicalDeviceLimits::minUniformBufferOffsetAlignment
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*/
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uint32_t min_ubo_alignment;
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/** Minimum SSBO alignment.
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*
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* This should match VkPhysicalDeviceLimits::minStorageBufferOffsetAlignment
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*/
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uint32_t min_ssbo_alignment;
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2020-10-05 19:21:29 -05:00
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const nir_shader *clc_shader;
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2020-08-18 07:16:32 -07:00
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2017-08-16 16:04:08 -07:00
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struct {
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void (*func)(void *private_data,
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enum nir_spirv_debug_level level,
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size_t spirv_offset,
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const char *message);
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void *private_data;
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} debug;
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2022-12-10 12:36:57 +01:00
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/* Force texture sampling to be non-uniform. */
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bool force_tex_non_uniform;
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2023-11-29 01:20:54 +01:00
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/* Force SSBO accesses to be non-uniform. */
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bool force_ssbo_non_uniform;
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2023-02-23 19:24:24 -08:00
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/* In Debug Builds, instead of emitting an OS break on failure, just return NULL from
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* spirv_to_nir(). This is useful for the unit tests that want to report a test failed
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* but continue executing other tests.
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*/
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bool skip_os_break_in_debug_build;
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2023-08-01 14:37:28 +02:00
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/* Shader index provided by VkPipelineShaderStageNodeCreateInfoAMDX */
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uint32_t shader_index;
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2016-12-27 23:27:14 +00:00
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};
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2023-05-11 15:36:55 -07:00
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enum spirv_verify_result {
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SPIRV_VERIFY_OK = 0,
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SPIRV_VERIFY_PARSER_ERROR = 1,
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SPIRV_VERIFY_ENTRY_POINT_NOT_FOUND = 2,
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SPIRV_VERIFY_UNKNOWN_SPEC_INDEX = 3,
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};
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enum spirv_verify_result spirv_verify_gl_specialization_constants(
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const uint32_t *words, size_t word_count,
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struct nir_spirv_specialization *spec, unsigned num_spec,
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gl_shader_stage stage, const char *entry_point_name);
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2018-01-18 12:31:52 +01:00
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2019-05-19 00:22:17 -07:00
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nir_shader *spirv_to_nir(const uint32_t *words, size_t word_count,
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struct nir_spirv_specialization *specializations,
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unsigned num_specializations,
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gl_shader_stage stage, const char *entry_point_name,
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const struct spirv_to_nir_options *options,
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const nir_shader_compiler_options *nir_options);
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2015-04-28 17:43:16 -07:00
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2023-10-01 19:45:39 -04:00
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bool
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spirv_library_to_nir_builder(FILE *fp, const uint32_t *words, size_t word_count,
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const struct spirv_to_nir_options *options);
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2015-06-24 19:01:10 -07:00
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#ifdef __cplusplus
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}
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#endif
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2015-04-28 17:43:16 -07:00
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#endif /* _NIR_SPIRV_H_ */
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