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mesa/src/broadcom/Makefile.sources

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vc4: Introduce XML-based packet header generation like Intel's. I really liked this idea, as it should help with management of packet parsing tools like the CL dump. The python script is forked off of theirs because our packets are byte-based instead of dwords, and the changes to do so while avoiding performance regressions due to unaligned accesses were quite invasive. v2: Fix Android.mk paths, drop shebang for python script, fix overlap detection. Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Rob Herring <robh@kernel.org>
2016-10-26 10:14:37 -07:00
BROADCOM_GENXML_GENERATED_FILES = \
cle/v3d_packet_v21_pack.h \
broadcom/genxml: Add V3D 3.3 packet definitions. This will be used by the new vc5 gallium driver, and a future Vulkan driver.
2017-02-02 16:20:15 -08:00
cle/v3d_packet_v33_pack.h \
broadcom/vc5: Add XML for V3D v4.1 (BCM7278)
2017-12-27 16:18:02 -08:00
cle/v3d_packet_v41_pack.h \
broadcom/vc5: Add XML for V3D 4.2.
2018-01-27 18:05:58 +11:00
cle/v3d_packet_v42_pack.h \
broadcom/genxml: Introduce a V3D packet/struct decoder. This is copied from Intel's XML decoder, modified to handle V3D's byte-oriented packets. v2: Squash in robher's fixes for Android
2017-07-12 13:15:34 -07:00
cle/v3d_xml.h \
vc4: Introduce XML-based packet header generation like Intel's. I really liked this idea, as it should help with management of packet parsing tools like the CL dump. The python script is forked off of theirs because our packets are byte-based instead of dwords, and the changes to do so while avoiding performance regressions due to unaligned accesses were quite invasive. v2: Fix Android.mk paths, drop shebang for python script, fix overlap detection. Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Rob Herring <robh@kernel.org>
2016-10-26 10:14:37 -07:00
$()
BROADCOM_GENXML_XML_FILES = \
cle/v3d_packet_v21.xml \
broadcom/genxml: Add V3D 3.3 packet definitions. This will be used by the new vc5 gallium driver, and a future Vulkan driver.
2017-02-02 16:20:15 -08:00
cle/v3d_packet_v33.xml \
vc4: Introduce XML-based packet header generation like Intel's. I really liked this idea, as it should help with management of packet parsing tools like the CL dump. The python script is forked off of theirs because our packets are byte-based instead of dwords, and the changes to do so while avoiding performance regressions due to unaligned accesses were quite invasive. v2: Fix Android.mk paths, drop shebang for python script, fix overlap detection. Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Rob Herring <robh@kernel.org>
2016-10-26 10:14:37 -07:00
$()
BROADCOM_FILES = \
cle/v3d_packet_helpers.h \
broadcom: add missing headers to the tarball Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-17 16:27:52 +00:00
cle/v3dx_pack.h\
broadcom: Add vc5 CLIF dumping This will be usable with "VC5_DEBUG=cl" on the vc5 driver to stream a CLIF file (the Broadcom equivalent of i965's AUB) to stderr. I haven't tested that this is actually usable with the internal CLIF-consuming tools, but is close enough as a baseline and is useful for visually inspecting the command stream.
2017-02-02 16:25:12 -08:00
clif/clif_dump.c \
clif/clif_dump.h \
broadcom: add missing headers to the tarball Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-17 16:27:52 +00:00
clif/clif_private.h \
vc4: Move the utile load/store functions to a header for reuse by v3d. These implementations of whole-utile load/stores would be the same for v3d, though the layouts of blocks of utiles has changed.
2018-12-17 11:10:11 -08:00
common/v3d_cpu_tiling.h \
broadcom: add missing headers to the tarball Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-17 16:27:52 +00:00
common/v3d_debug.c \
common/v3d_debug.h \
broadcom: correct header file in BROADCOM_FILES This fixes `make distcheck` > make[3]: *** No rule to make target 'common/v3d_devinfo.h', needed by 'distdir'. Stop. > make[3]: Leaving directory '/home/local/mesa/src/broadcom' > Makefile:945: recipe for target 'distdir' failed > make[2]: Leaving directory '/home/local/mesa/src' > make[2]: *** [distdir] Error 1 > make[1]: *** [distdir] Error 1 Fixes: 427bbbb99c ("broadcom: Introduce a header for talking about chip revisions.") Cc: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-20 01:44:58 +03:00
common/v3d_device_info.h \
v3d: Avoid duplicating limits defines between gallium and v3d core. We don't want to pull the compiler into every include in the gallium driver, so just make a new little header to store the limits.
2019-01-18 15:36:15 -08:00
common/v3d_limits.h \
broadcom: add missing headers to the tarball Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-17 16:27:52 +00:00
common/v3d_macros.h \
broadcom: Add VC5 NIR compiler. This is a pretty straightforward fork of VC4's NIR compiler to VC5. The condition codes, registers, and I/O have all changed, making the backend hard to share, though their heritage is still recognizable. v2: Move to src/broadcom/compiler to match intel's layout, rename more "vc5" to "v3d", rename QIR to VIR ("V3D IR") to avoid symbol conflicts with vc4, use new v3d_debug header, add compiler init/free functions, do texture swizzling in NIR to allow optimization.
2017-02-03 10:24:14 -08:00
compiler/nir_to_vir.c \
compiler/vir.c \
compiler/vir_dump.c \
compiler/vir_live_variables.c \
compiler/vir_opt_copy_propagate.c \
compiler/vir_opt_dead_code.c \
v3d: Add an optimization pass for redundant flags updates. Our exec masking introduces lots of redundant flags updates, and even without that there will be cases where NIR comparisons on the same sources for different reasons may generate the same comparison instruction before the selection. total instructions in shared programs: 6492930 -> 6460934 (-0.49%) total uniforms in shared programs: 2117460 -> 2115106 (-0.11%) total spills in shared programs: 4983 -> 4987 (0.08%) total fills in shared programs: 6408 -> 6416 (0.12%)
2019-02-22 14:26:26 -08:00
compiler/vir_opt_redundant_flags.c \
v3d: Implement a small immediates optimization, based on VC4's. We can do one per instruction, and we have to be careful not to overwrite raddr_b, but this greatly reduces the pressure on uniform loads (particularly around ldvpm/stvpm instructions). total instructions in shared programs: 90768 -> 88220 (-2.81%) instructions in affected programs: 82711 -> 80163 (-3.08%)
2018-07-20 14:27:09 -07:00
compiler/vir_opt_small_immediates.c \
broadcom: Add VC5 NIR compiler. This is a pretty straightforward fork of VC4's NIR compiler to VC5. The condition codes, registers, and I/O have all changed, making the backend hard to share, though their heritage is still recognizable. v2: Move to src/broadcom/compiler to match intel's layout, rename more "vc5" to "v3d", rename QIR to VIR ("V3D IR") to avoid symbol conflicts with vc4, use new v3d_debug header, add compiler init/free functions, do texture swizzling in NIR to allow optimization.
2017-02-03 10:24:14 -08:00
compiler/vir_register_allocate.c \
compiler/vir_to_qpu.c \
compiler/qpu_schedule.c \
compiler/qpu_validate.c \
broadcom/vc5: Move V3D 3.3 texturing to a separate file. V3D 4.x texturing changes enough that #ifdefs would just make a mess of it.
2018-01-10 12:48:05 -08:00
compiler/v3d33_tex.c \
broadcom/vc5: Move V3D 3.3 VPM write setup to a separate file. For V4.1 texturing, I need the V4.1 XML, so the main compiler needs to stop including V3.3 XML.
2018-01-10 12:22:38 -08:00
compiler/v3d33_vpm_setup.c \
broadcom/vc5: Add compiler support for V3D 4.x texturing.
2018-01-10 12:51:08 -08:00
compiler/v3d40_tex.c \
broadcom: Add VC5 NIR compiler. This is a pretty straightforward fork of VC4's NIR compiler to VC5. The condition codes, registers, and I/O have all changed, making the backend hard to share, though their heritage is still recognizable. v2: Move to src/broadcom/compiler to match intel's layout, rename more "vc5" to "v3d", rename QIR to VIR ("V3D IR") to avoid symbol conflicts with vc4, use new v3d_debug header, add compiler init/free functions, do texture swizzling in NIR to allow optimization.
2017-02-03 10:24:14 -08:00
compiler/v3d_compiler.h \
v3d: Add support for shader_image_load_store. This is only exposed on V3D 4.1+, because we didn't have the TMU write operations for images on 3.3 (To do GLES 3.1 there, you have to lower it to SSBO load/stores, which is a problem to solve later).
2017-12-11 12:52:27 -08:00
compiler/v3d_nir_lower_image_load_store.c \
broadcom: Add VC5 NIR compiler. This is a pretty straightforward fork of VC4's NIR compiler to VC5. The condition codes, registers, and I/O have all changed, making the backend hard to share, though their heritage is still recognizable. v2: Move to src/broadcom/compiler to match intel's layout, rename more "vc5" to "v3d", rename QIR to VIR ("V3D IR") to avoid symbol conflicts with vc4, use new v3d_debug header, add compiler init/free functions, do texture swizzling in NIR to allow optimization.
2017-02-03 10:24:14 -08:00
compiler/v3d_nir_lower_io.c \
v3d: Add a lowering pass for line smoothing When line smoothing is enabled, the driver now increases the width of the line so that it can add some semi-transparent pixels to either side of the line. A lowering pass is added which modifies the alpha component of every write to fragment output 0 so that if the fragment is outside the width of the line then the alpha is reduced. It additionally discards fragments that are completely invisible. It might seem bad to use discard on a tiled renderer but the assumption is that any bad effects from using discard will also happen anyway because of enabling alpha blending. v2: Disable the line smoothing pass entirely when the framebuffer contains an integer colour output or one with no alpha channel. Calculate the coverage once upfront and store in a global variable instead of calculating each time an output write is modified. Also do the conditional discard once upfront. v3: Don’t check whether the output buffer has an alpha channel. Only look at output 0. Use aa_line_width intrinsic instead of calculating the real line width in the shader. Clamp the coverage as part of the global variable, not per output write. Reviewed-by: Eric Anholt <eric@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5624>
2020-06-22 14:26:02 +02:00
compiler/v3d_nir_lower_line_smooth.c \
v3d: Use the new lower_to_scratch implementation for indirects on temps. We can use the same register spilling infrastructure for our loads/stores of indirect access of temp variables, instead of doing an if ladder. Cuts 50% of instructions and max-temps from 2 KSP shaders in shader-db. Also causes several other KSP shaders with large bodies and large loop counts to not be force-unrolled. The change was originally motivated by NOLTIS slightly modifying register pressure in piglit temp mat4 array read/write tests, triggering register allocation failures.
2019-04-11 11:12:01 -07:00
compiler/v3d_nir_lower_scratch.c \
broadcom/vc5: Add lowering for txf_ms to a txf on a 2x2-scaled texture. The HW has no native sampler support for multisample textures, but since we only need to support txf_ms and the layout is UIF, we just need to scale up the texcoords and then add in the sample. This drops the old TEXTURE_MSAA_ADDR special uniform, since we're treating MSAA textures as textures, rather than basically texbos like VC4 had to.
2017-10-24 12:16:50 -07:00
compiler/v3d_nir_lower_txf_ms.c \
broadcom: Add V3D 3.3 QPU instruction pack, unpack, and disasm. Unlike VC4, I've defined an unpacked instruction format with pack/unpack functions to convert to 64-bit encoded instructions. This will let us incrementally put together our instructions and validate them in a more natural way than the QPU_GET_FIELD/QPU_SET_FIELD used to. The pack/unpack unfortuantely are written by hand. While I could define genxml for parts of it, there are many special cases (like operand order of commutative binops choosing which binop is being performed!) and it probably wouldn't come out much cleaner. The disasm unit test ensures that we have the same assembly format as Broadcom's internal tools, other than whitespace changes. v2: Fix automake variable redefinition complaints, add test to .gitignore
2017-02-02 16:15:18 -08:00
qpu/qpu_disasm.c \
qpu/qpu_disasm.h \
qpu/qpu_instr.c \
qpu/qpu_instr.h \
qpu/qpu_pack.c \
vc4: Introduce XML-based packet header generation like Intel's. I really liked this idea, as it should help with management of packet parsing tools like the CL dump. The python script is forked off of theirs because our packets are byte-based instead of dwords, and the changes to do so while avoiding performance regressions due to unaligned accesses were quite invasive. v2: Fix Android.mk paths, drop shebang for python script, fix overlap detection. Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Rob Herring <robh@kernel.org>
2016-10-26 10:14:37 -07:00
$()
broadcom/vc5: Move the body of CLIF dumping to a per-version file. I want the library's entrypoints to still be unversioned, but the actual packet dumping needs to be per-version.
2018-01-09 15:13:27 -08:00
BROADCOM_PER_VERSION_SOURCES = \
clif/v3dx_dump.c \
$()
broadcom/genxml: Introduce a V3D packet/struct decoder. This is copied from Intel's XML decoder, modified to handle V3D's byte-oriented packets. v2: Squash in robher's fixes for Android
2017-07-12 13:15:34 -07:00
BROADCOM_DECODER_FILES = \
cle/v3d_decoder.c \
cle/v3d_decoder.h \
$()
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