2018-01-19 18:57:30 -08:00
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/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <time.h>
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#include "pipe/p_defines.h"
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#include "pipe/p_state.h"
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2018-01-20 02:47:04 -08:00
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#include "util/ralloc.h"
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2018-01-19 18:57:30 -08:00
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#include "util/u_inlines.h"
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#include "util/u_format.h"
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#include "util/u_upload_mgr.h"
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2018-01-20 23:11:37 -08:00
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#include "i915_drm.h"
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2018-01-19 18:57:30 -08:00
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#include "iris_context.h"
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#include "iris_resource.h"
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#include "iris_screen.h"
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static void
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iris_flush(struct pipe_context *ctx,
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struct pipe_fence_handle **fence,
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unsigned flags)
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{
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2018-01-21 17:44:08 -08:00
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struct iris_context *ice = (struct iris_context *)ctx;
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iris_batch_flush(&ice->render_batch);
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2018-01-19 18:57:30 -08:00
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if (fence)
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*fence = NULL;
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}
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/**
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* For debugging purposes, this returns a time in seconds.
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*/
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double
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get_time(void)
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{
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struct timespec tp;
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clock_gettime(CLOCK_MONOTONIC, &tp);
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return tp.tv_sec + tp.tv_nsec / 1000000000.0;
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}
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static void
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iris_set_debug_callback(struct pipe_context *ctx,
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const struct pipe_debug_callback *cb)
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{
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struct iris_context *ice = (struct iris_context *)ctx;
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if (cb)
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ice->dbg = *cb;
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else
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memset(&ice->dbg, 0, sizeof(ice->dbg));
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}
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static void
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iris_destroy_context(struct pipe_context *ctx)
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{
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2018-01-20 02:47:04 -08:00
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struct iris_context *ice = (struct iris_context *)ctx;
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2018-01-19 18:57:30 -08:00
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if (ctx->stream_uploader)
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u_upload_destroy(ctx->stream_uploader);
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2018-01-25 19:43:45 -08:00
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iris_destroy_program_cache(ice);
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2018-04-06 11:44:59 -07:00
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iris_destroy_binder(&ice->state.binder);
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2018-04-05 21:48:33 -07:00
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u_upload_destroy(ice->state.surface_uploader);
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u_upload_destroy(ice->state.dynamic_uploader);
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2018-01-25 19:43:45 -08:00
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2018-01-23 01:23:54 -08:00
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iris_batch_free(&ice->render_batch);
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2018-01-20 02:47:04 -08:00
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ralloc_free(ice);
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2018-01-19 18:57:30 -08:00
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}
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2018-01-25 01:36:49 -08:00
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#define genX_call(devinfo, func, ...) \
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switch (devinfo->gen) { \
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case 10: \
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gen10_##func(__VA_ARGS__); \
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break; \
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case 9: \
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gen9_##func(__VA_ARGS__); \
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break; \
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default: \
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unreachable("Unknown hardware generation"); \
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}
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2018-01-19 18:57:30 -08:00
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struct pipe_context *
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2018-01-19 21:55:32 -08:00
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iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
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2018-01-19 18:57:30 -08:00
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{
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2018-01-19 21:55:32 -08:00
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struct iris_screen *screen = (struct iris_screen*)pscreen;
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2018-01-25 01:36:49 -08:00
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const struct gen_device_info *devinfo = &screen->devinfo;
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2018-01-20 02:47:04 -08:00
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struct iris_context *ice = rzalloc(NULL, struct iris_context);
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2018-01-19 18:57:30 -08:00
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if (!ice)
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return NULL;
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struct pipe_context *ctx = &ice->ctx;
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2018-01-19 21:55:32 -08:00
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ctx->screen = pscreen;
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2018-01-19 18:57:30 -08:00
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ctx->priv = priv;
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ctx->stream_uploader = u_upload_create_default(ctx);
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if (!ctx->stream_uploader) {
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free(ctx);
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return NULL;
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}
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ctx->const_uploader = ctx->stream_uploader;
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ctx->destroy = iris_destroy_context;
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ctx->flush = iris_flush;
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ctx->set_debug_callback = iris_set_debug_callback;
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2018-01-25 21:23:45 -08:00
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ice->shaders.urb_size = devinfo->urb.size;
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2018-01-19 18:57:30 -08:00
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iris_init_blit_functions(ctx);
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iris_init_clear_functions(ctx);
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iris_init_program_functions(ctx);
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iris_init_resource_functions(ctx);
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iris_init_query_functions(ctx);
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2018-01-20 02:47:04 -08:00
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iris_init_program_cache(ice);
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2018-04-06 11:44:59 -07:00
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iris_init_binder(&ice->state.binder, screen->bufmgr);
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2018-04-05 21:48:33 -07:00
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ice->state.surface_uploader =
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u_upload_create(&ice->ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
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IRIS_RESOURCE_FLAG_SURFACE_MEMZONE);
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ice->state.dynamic_uploader =
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u_upload_create(&ice->ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
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IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE);
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2018-01-25 01:36:49 -08:00
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genX_call(devinfo, init_state, ice);
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2018-04-20 23:28:03 -07:00
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ice->vtbl.init_render_context(screen, &ice->render_batch, &ice->vtbl,
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&ice->dbg);
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2018-01-19 21:55:32 -08:00
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2018-01-19 18:57:30 -08:00
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return ctx;
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}
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