2023-09-05 16:11:56 +03:00
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/*
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2026-01-23 17:03:58 -08:00
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* Copyright © 2024 Intel Corporation
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* SPDX-License-Identifier: MIT
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2023-09-05 16:11:56 +03:00
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*/
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#include "intel_nir.h"
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2025-10-06 16:11:46 -07:00
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#include "intel_shader_enums.h"
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2023-09-05 16:11:56 +03:00
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#include "compiler/nir/nir_builder.h"
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static bool
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2025-02-04 13:06:08 -05:00
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lower_printf_intrinsics(nir_builder *b, nir_intrinsic_instr *intrin, void *_)
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2023-09-05 16:11:56 +03:00
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{
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2025-02-04 13:06:08 -05:00
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b->cursor = nir_before_instr(&intrin->instr);
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2023-09-05 16:11:56 +03:00
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_printf_buffer_address:
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nir_def_replace(
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2023-09-05 16:11:56 +03:00
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&intrin->def,
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nir_pack_64_2x32_split(
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b,
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nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_PRINTF_BUFFER_ADDR_LOW),
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nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_PRINTF_BUFFER_ADDR_HIGH)));
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return true;
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2025-01-17 15:51:33 +02:00
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case nir_intrinsic_load_printf_buffer_size:
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2025-02-04 13:06:08 -05:00
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nir_def_replace(
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2025-01-17 15:51:33 +02:00
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&intrin->def,
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nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_PRINTF_BUFFER_SIZE));
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return true;
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2023-09-05 16:11:56 +03:00
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default:
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return false;
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}
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}
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bool
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intel_nir_lower_printf(nir_shader *nir)
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{
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2025-02-04 13:06:08 -05:00
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return nir_shader_intrinsics_pass(nir, lower_printf_intrinsics,
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nir_metadata_control_flow, NULL);
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2023-09-05 16:11:56 +03:00
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}
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