2015-09-24 00:54:52 -04:00
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/*
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* Copyright © 2014 Connor Abbott
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "nir_instr_set.h"
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2015-09-24 01:57:04 -04:00
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#include "nir_vla.h"
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2018-05-24 11:37:51 -07:00
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#include "util/half_float.h"
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2015-09-24 01:57:04 -04:00
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2019-06-20 13:47:30 -05:00
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static bool
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src_is_ssa(nir_src *src, void *data)
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{
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(void) data;
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return src->is_ssa;
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}
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static bool
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dest_is_ssa(nir_dest *dest, void *data)
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{
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(void) data;
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return dest->is_ssa;
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}
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2020-02-18 14:40:00 -08:00
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ASSERTED static inline bool
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2019-06-20 13:47:30 -05:00
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instr_each_src_and_dest_is_ssa(const nir_instr *instr)
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{
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if (!nir_foreach_dest((nir_instr *)instr, dest_is_ssa, NULL) ||
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!nir_foreach_src((nir_instr *)instr, src_is_ssa, NULL))
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return false;
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return true;
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}
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/* This function determines if uses of an instruction can safely be rewritten
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* to use another identical instruction instead. Note that this function must
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* be kept in sync with hash_instr() and nir_instrs_equal() -- only
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* instructions that pass this test will be handed on to those functions, and
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* conversely they must handle everything that this function returns true for.
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*/
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static bool
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instr_can_rewrite(const nir_instr *instr)
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{
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/* We only handle SSA. */
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assert(instr_each_src_and_dest_is_ssa(instr));
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switch (instr->type) {
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case nir_instr_type_alu:
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case nir_instr_type_deref:
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case nir_instr_type_tex:
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case nir_instr_type_load_const:
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case nir_instr_type_phi:
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return true;
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case nir_instr_type_intrinsic:
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return nir_intrinsic_can_reorder(nir_instr_as_intrinsic(instr));
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case nir_instr_type_call:
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case nir_instr_type_jump:
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case nir_instr_type_ssa_undef:
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return false;
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case nir_instr_type_parallel_copy:
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default:
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unreachable("Invalid instruction type");
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}
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return false;
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}
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2020-02-27 15:04:25 +02:00
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#define HASH(hash, data) XXH32(&(data), sizeof(data), hash)
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2015-09-24 01:57:04 -04:00
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static uint32_t
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hash_src(uint32_t hash, const nir_src *src)
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{
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assert(src->is_ssa);
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hash = HASH(hash, src->ssa);
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return hash;
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}
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static uint32_t
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hash_alu_src(uint32_t hash, const nir_alu_src *src, unsigned num_components)
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{
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hash = HASH(hash, src->abs);
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hash = HASH(hash, src->negate);
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for (unsigned i = 0; i < num_components; i++)
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hash = HASH(hash, src->swizzle[i]);
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hash = hash_src(hash, &src->src);
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return hash;
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}
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static uint32_t
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hash_alu(uint32_t hash, const nir_alu_instr *instr)
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{
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hash = HASH(hash, instr->op);
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2019-05-17 13:46:38 -07:00
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/* We explicitly don't hash instr->exact. */
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uint8_t flags = instr->no_signed_wrap |
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instr->no_unsigned_wrap << 1;
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hash = HASH(hash, flags);
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2015-09-24 01:57:04 -04:00
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hash = HASH(hash, instr->dest.dest.ssa.num_components);
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2015-08-03 15:05:38 -07:00
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hash = HASH(hash, instr->dest.dest.ssa.bit_size);
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2015-09-24 01:57:04 -04:00
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2019-05-09 15:27:14 -07:00
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if (nir_op_infos[instr->op].algebraic_properties & NIR_OP_IS_2SRC_COMMUTATIVE) {
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2019-05-09 15:33:11 -07:00
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assert(nir_op_infos[instr->op].num_inputs >= 2);
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2015-09-24 01:57:04 -04:00
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uint32_t hash0 = hash_alu_src(hash, &instr->src[0],
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nir_ssa_alu_instr_src_components(instr, 0));
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uint32_t hash1 = hash_alu_src(hash, &instr->src[1],
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nir_ssa_alu_instr_src_components(instr, 1));
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/* For commutative operations, we need some commutative way of
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* combining the hashes. One option would be to XOR them but that
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* means that anything with two identical sources will hash to 0 and
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* that's common enough we probably don't want the guaranteed
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* collision. Either addition or multiplication will also work.
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*/
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hash = hash0 * hash1;
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2019-05-09 15:33:11 -07:00
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for (unsigned i = 2; i < nir_op_infos[instr->op].num_inputs; i++) {
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hash = hash_alu_src(hash, &instr->src[i],
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nir_ssa_alu_instr_src_components(instr, i));
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}
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2015-09-24 01:57:04 -04:00
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} else {
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for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
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hash = hash_alu_src(hash, &instr->src[i],
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nir_ssa_alu_instr_src_components(instr, i));
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}
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}
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return hash;
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}
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2018-03-14 21:45:38 -07:00
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static uint32_t
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hash_deref(uint32_t hash, const nir_deref_instr *instr)
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{
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hash = HASH(hash, instr->deref_type);
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2020-10-30 12:14:05 -05:00
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hash = HASH(hash, instr->modes);
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2018-03-14 21:45:38 -07:00
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hash = HASH(hash, instr->type);
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if (instr->deref_type == nir_deref_type_var)
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return HASH(hash, instr->var);
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hash = hash_src(hash, &instr->parent);
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switch (instr->deref_type) {
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case nir_deref_type_struct:
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hash = HASH(hash, instr->strct.index);
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break;
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case nir_deref_type_array:
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2018-11-28 12:26:52 -06:00
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case nir_deref_type_ptr_as_array:
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2018-03-14 21:45:38 -07:00
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hash = hash_src(hash, &instr->arr.index);
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break;
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2018-11-28 12:26:52 -06:00
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case nir_deref_type_cast:
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hash = HASH(hash, instr->cast.ptr_stride);
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2020-08-24 09:51:04 -05:00
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hash = HASH(hash, instr->cast.align_mul);
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hash = HASH(hash, instr->cast.align_offset);
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2018-11-28 12:26:52 -06:00
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break;
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2018-03-14 21:45:38 -07:00
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case nir_deref_type_var:
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case nir_deref_type_array_wildcard:
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/* Nothing to do */
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break;
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default:
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unreachable("Invalid instruction deref type");
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}
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return hash;
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}
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2015-09-24 01:57:04 -04:00
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static uint32_t
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hash_load_const(uint32_t hash, const nir_load_const_instr *instr)
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{
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hash = HASH(hash, instr->def.num_components);
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2018-10-18 11:59:40 -05:00
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if (instr->def.bit_size == 1) {
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for (unsigned i = 0; i < instr->def.num_components; i++) {
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2019-03-27 00:59:03 +01:00
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uint8_t b = instr->value[i].b;
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2018-10-18 11:59:40 -05:00
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hash = HASH(hash, b);
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}
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} else {
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2019-03-27 00:59:03 +01:00
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unsigned size = instr->def.num_components * sizeof(*instr->value);
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2020-02-27 15:04:25 +02:00
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hash = XXH32(instr->value, size, hash);
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2018-10-18 11:59:40 -05:00
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}
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2015-09-24 01:57:04 -04:00
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return hash;
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}
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static int
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cmp_phi_src(const void *data1, const void *data2)
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{
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nir_phi_src *src1 = *(nir_phi_src **)data1;
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nir_phi_src *src2 = *(nir_phi_src **)data2;
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return src1->pred - src2->pred;
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}
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static uint32_t
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hash_phi(uint32_t hash, const nir_phi_instr *instr)
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{
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hash = HASH(hash, instr->instr.block);
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/* sort sources by predecessor, since the order shouldn't matter */
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unsigned num_preds = instr->instr.block->predecessors->entries;
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NIR_VLA(nir_phi_src *, srcs, num_preds);
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unsigned i = 0;
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2016-04-26 20:16:21 -07:00
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nir_foreach_phi_src(src, instr) {
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2015-09-24 01:57:04 -04:00
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srcs[i++] = src;
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}
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qsort(srcs, num_preds, sizeof(nir_phi_src *), cmp_phi_src);
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for (i = 0; i < num_preds; i++) {
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hash = hash_src(hash, &srcs[i]->src);
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hash = HASH(hash, srcs[i]->pred);
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}
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return hash;
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}
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static uint32_t
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hash_intrinsic(uint32_t hash, const nir_intrinsic_instr *instr)
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{
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const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
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hash = HASH(hash, instr->intrinsic);
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2015-08-03 15:05:38 -07:00
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if (info->has_dest) {
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2015-09-24 01:57:04 -04:00
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hash = HASH(hash, instr->dest.ssa.num_components);
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2015-08-03 15:05:38 -07:00
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hash = HASH(hash, instr->dest.ssa.bit_size);
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}
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2015-09-24 01:57:04 -04:00
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2020-02-27 15:04:25 +02:00
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hash = XXH32(instr->const_index, info->num_indices * sizeof(instr->const_index[0]), hash);
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2020-08-18 16:07:32 +01:00
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for (unsigned i = 0; i < nir_intrinsic_infos[instr->intrinsic].num_srcs; i++)
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hash = hash_src(hash, &instr->src[i]);
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2015-09-24 01:57:04 -04:00
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return hash;
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}
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static uint32_t
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hash_tex(uint32_t hash, const nir_tex_instr *instr)
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{
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hash = HASH(hash, instr->op);
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hash = HASH(hash, instr->num_srcs);
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for (unsigned i = 0; i < instr->num_srcs; i++) {
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hash = HASH(hash, instr->src[i].src_type);
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hash = hash_src(hash, &instr->src[i].src);
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}
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hash = HASH(hash, instr->coord_components);
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hash = HASH(hash, instr->sampler_dim);
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hash = HASH(hash, instr->is_array);
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hash = HASH(hash, instr->is_shadow);
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hash = HASH(hash, instr->is_new_style_shadow);
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unsigned component = instr->component;
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hash = HASH(hash, component);
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2019-03-18 21:23:59 +01:00
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for (unsigned i = 0; i < 4; ++i)
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for (unsigned j = 0; j < 2; ++j)
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hash = HASH(hash, instr->tg4_offsets[i][j]);
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2016-02-06 09:05:10 -08:00
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hash = HASH(hash, instr->texture_index);
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2015-11-02 17:58:29 -08:00
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hash = HASH(hash, instr->sampler_index);
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2020-01-01 14:42:58 +01:00
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hash = HASH(hash, instr->texture_non_uniform);
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hash = HASH(hash, instr->sampler_non_uniform);
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2015-09-24 01:57:04 -04:00
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return hash;
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}
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/* Computes a hash of an instruction for use in a hash table. Note that this
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* will only work for instructions where instr_can_rewrite() returns true, and
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* it should return identical hashes for two instructions that are the same
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* according nir_instrs_equal().
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*/
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static uint32_t
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hash_instr(const void *data)
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|
|
|
|
{
|
|
|
|
|
const nir_instr *instr = data;
|
2020-02-27 15:04:25 +02:00
|
|
|
uint32_t hash = 0;
|
2015-09-24 01:57:04 -04:00
|
|
|
|
|
|
|
|
switch (instr->type) {
|
|
|
|
|
case nir_instr_type_alu:
|
|
|
|
|
hash = hash_alu(hash, nir_instr_as_alu(instr));
|
|
|
|
|
break;
|
2018-03-14 21:45:38 -07:00
|
|
|
case nir_instr_type_deref:
|
|
|
|
|
hash = hash_deref(hash, nir_instr_as_deref(instr));
|
|
|
|
|
break;
|
2015-09-24 01:57:04 -04:00
|
|
|
case nir_instr_type_load_const:
|
|
|
|
|
hash = hash_load_const(hash, nir_instr_as_load_const(instr));
|
|
|
|
|
break;
|
|
|
|
|
case nir_instr_type_phi:
|
|
|
|
|
hash = hash_phi(hash, nir_instr_as_phi(instr));
|
|
|
|
|
break;
|
|
|
|
|
case nir_instr_type_intrinsic:
|
|
|
|
|
hash = hash_intrinsic(hash, nir_instr_as_intrinsic(instr));
|
|
|
|
|
break;
|
|
|
|
|
case nir_instr_type_tex:
|
|
|
|
|
hash = hash_tex(hash, nir_instr_as_tex(instr));
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
unreachable("Invalid instruction type");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return hash;
|
|
|
|
|
}
|
2015-09-24 00:54:52 -04:00
|
|
|
|
|
|
|
|
bool
|
|
|
|
|
nir_srcs_equal(nir_src src1, nir_src src2)
|
|
|
|
|
{
|
|
|
|
|
if (src1.is_ssa) {
|
|
|
|
|
if (src2.is_ssa) {
|
|
|
|
|
return src1.ssa == src2.ssa;
|
|
|
|
|
} else {
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
if (src2.is_ssa) {
|
|
|
|
|
return false;
|
|
|
|
|
} else {
|
|
|
|
|
if ((src1.reg.indirect == NULL) != (src2.reg.indirect == NULL))
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
if (src1.reg.indirect) {
|
|
|
|
|
if (!nir_srcs_equal(*src1.reg.indirect, *src2.reg.indirect))
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return src1.reg.reg == src2.reg.reg &&
|
|
|
|
|
src1.reg.base_offset == src2.reg.base_offset;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2018-05-22 18:18:07 -07:00
|
|
|
/**
|
|
|
|
|
* If the \p s is an SSA value that was generated by a negation instruction,
|
|
|
|
|
* that instruction is returned as a \c nir_alu_instr. Otherwise \c NULL is
|
|
|
|
|
* returned.
|
|
|
|
|
*/
|
2019-04-17 17:10:18 -05:00
|
|
|
static nir_alu_instr *
|
|
|
|
|
get_neg_instr(nir_src s)
|
2018-05-22 18:18:07 -07:00
|
|
|
{
|
2019-04-17 17:10:18 -05:00
|
|
|
nir_alu_instr *alu = nir_src_as_alu_instr(s);
|
2018-05-22 18:18:07 -07:00
|
|
|
|
|
|
|
|
return alu != NULL && (alu->op == nir_op_fneg || alu->op == nir_op_ineg)
|
|
|
|
|
? alu : NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2018-05-24 11:37:51 -07:00
|
|
|
bool
|
2019-06-13 14:06:55 -07:00
|
|
|
nir_const_value_negative_equal(nir_const_value c1,
|
|
|
|
|
nir_const_value c2,
|
2019-06-13 12:59:29 -07:00
|
|
|
nir_alu_type full_type)
|
2018-05-24 11:37:51 -07:00
|
|
|
{
|
2019-06-13 12:59:29 -07:00
|
|
|
assert(nir_alu_type_get_base_type(full_type) != nir_type_invalid);
|
|
|
|
|
assert(nir_alu_type_get_type_size(full_type) != 0);
|
|
|
|
|
|
|
|
|
|
switch (full_type) {
|
|
|
|
|
case nir_type_float16:
|
2019-06-13 14:06:55 -07:00
|
|
|
return _mesa_half_to_float(c1.u16) == -_mesa_half_to_float(c2.u16);
|
2018-05-24 11:37:51 -07:00
|
|
|
|
2019-06-13 12:59:29 -07:00
|
|
|
case nir_type_float32:
|
2019-06-13 14:06:55 -07:00
|
|
|
return c1.f32 == -c2.f32;
|
2018-05-24 11:37:51 -07:00
|
|
|
|
2019-06-13 12:59:29 -07:00
|
|
|
case nir_type_float64:
|
2019-06-13 14:06:55 -07:00
|
|
|
return c1.f64 == -c2.f64;
|
2018-05-24 11:37:51 -07:00
|
|
|
|
2019-06-13 12:59:29 -07:00
|
|
|
case nir_type_int8:
|
|
|
|
|
case nir_type_uint8:
|
2019-06-13 14:06:55 -07:00
|
|
|
return c1.i8 == -c2.i8;
|
2018-05-24 11:37:51 -07:00
|
|
|
|
2019-06-13 12:59:29 -07:00
|
|
|
case nir_type_int16:
|
|
|
|
|
case nir_type_uint16:
|
2019-06-13 14:06:55 -07:00
|
|
|
return c1.i16 == -c2.i16;
|
2018-05-24 11:37:51 -07:00
|
|
|
|
2019-06-13 12:59:29 -07:00
|
|
|
case nir_type_int32:
|
|
|
|
|
case nir_type_uint32:
|
2019-06-13 14:06:55 -07:00
|
|
|
return c1.i32 == -c2.i32;
|
2018-05-24 11:37:51 -07:00
|
|
|
|
2019-06-13 12:59:29 -07:00
|
|
|
case nir_type_int64:
|
|
|
|
|
case nir_type_uint64:
|
2019-06-13 14:06:55 -07:00
|
|
|
return c1.i64 == -c2.i64;
|
2018-05-24 11:37:51 -07:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2018-05-22 18:18:07 -07:00
|
|
|
/**
|
|
|
|
|
* Shallow compare of ALU srcs to determine if one is the negation of the other
|
|
|
|
|
*
|
|
|
|
|
* This function detects cases where \p alu1 is a constant and \p alu2 is a
|
|
|
|
|
* constant that is its negation. It will also detect cases where \p alu2 is
|
|
|
|
|
* an SSA value that is a \c nir_op_fneg applied to \p alu1 (and vice versa).
|
|
|
|
|
*
|
|
|
|
|
* This function does not detect the general case when \p alu1 and \p alu2 are
|
|
|
|
|
* SSA values that are the negations of each other (e.g., \p alu1 represents
|
|
|
|
|
* (a * b) and \p alu2 represents (-a * b)).
|
nir: Handle swizzle in nir_alu_srcs_negative_equal
When I added this function, I was not sure if swizzles of immediate
values were a thing that occurred in NIR. The only existing user of
these functions is the partial redundancy elimination for compares.
Since comparison instructions are inherently scalar, this does not
occur.
However, a couple later patches, "nir/algebraic: Recognize
open-coded flrp(-1, 1, a) and flrp(1, -1, a)" combined with "intel/vec4:
Try to emit a single load for multiple 3-src instruction operands",
collaborate to create a few thousand instances.
No shader-db changes on any Intel platform.
v2: Handle the swizzle in nir_alu_srcs_negative_equal and leave
nir_const_value_negative_equal unchanged. Suggested by Jason.
v3: Correctly handle write masks. Add note (and assertion) that the
caller is responsible for various compatibility checks. The single
existing caller only calls this for combinations of scalar fadd and
float comparison instructions, so all of the requirements are met. A
later patch (intel/vec4: Try to emit a single load for multiple 3-src
instruction operands) will call this for sources of the same
instruction, so all of the requirements are met.
v4: Add unit test for nir_opt_comparison_pre that is fixed by this
commit.
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-06-10 15:05:14 -07:00
|
|
|
*
|
|
|
|
|
* \warning
|
|
|
|
|
* It is the responsibility of the caller to ensure that the component counts,
|
|
|
|
|
* write masks, and base types of the sources being compared are compatible.
|
2018-05-22 18:18:07 -07:00
|
|
|
*/
|
|
|
|
|
bool
|
|
|
|
|
nir_alu_srcs_negative_equal(const nir_alu_instr *alu1,
|
|
|
|
|
const nir_alu_instr *alu2,
|
|
|
|
|
unsigned src1, unsigned src2)
|
|
|
|
|
{
|
nir: Handle swizzle in nir_alu_srcs_negative_equal
When I added this function, I was not sure if swizzles of immediate
values were a thing that occurred in NIR. The only existing user of
these functions is the partial redundancy elimination for compares.
Since comparison instructions are inherently scalar, this does not
occur.
However, a couple later patches, "nir/algebraic: Recognize
open-coded flrp(-1, 1, a) and flrp(1, -1, a)" combined with "intel/vec4:
Try to emit a single load for multiple 3-src instruction operands",
collaborate to create a few thousand instances.
No shader-db changes on any Intel platform.
v2: Handle the swizzle in nir_alu_srcs_negative_equal and leave
nir_const_value_negative_equal unchanged. Suggested by Jason.
v3: Correctly handle write masks. Add note (and assertion) that the
caller is responsible for various compatibility checks. The single
existing caller only calls this for combinations of scalar fadd and
float comparison instructions, so all of the requirements are met. A
later patch (intel/vec4: Try to emit a single load for multiple 3-src
instruction operands) will call this for sources of the same
instruction, so all of the requirements are met.
v4: Add unit test for nir_opt_comparison_pre that is fixed by this
commit.
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-06-10 15:05:14 -07:00
|
|
|
#ifndef NDEBUG
|
|
|
|
|
for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++) {
|
|
|
|
|
assert(nir_alu_instr_channel_used(alu1, src1, i) ==
|
|
|
|
|
nir_alu_instr_channel_used(alu2, src2, i));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (nir_op_infos[alu1->op].input_types[src1] == nir_type_float) {
|
|
|
|
|
assert(nir_op_infos[alu1->op].input_types[src1] ==
|
|
|
|
|
nir_op_infos[alu2->op].input_types[src2]);
|
|
|
|
|
} else {
|
|
|
|
|
assert(nir_op_infos[alu1->op].input_types[src1] == nir_type_int);
|
|
|
|
|
assert(nir_op_infos[alu2->op].input_types[src2] == nir_type_int);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2018-05-22 18:18:07 -07:00
|
|
|
if (alu1->src[src1].abs != alu2->src[src2].abs)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
bool parity = alu1->src[src1].negate != alu2->src[src2].negate;
|
|
|
|
|
|
|
|
|
|
/* Handling load_const instructions is tricky. */
|
|
|
|
|
|
|
|
|
|
const nir_const_value *const const1 =
|
|
|
|
|
nir_src_as_const_value(alu1->src[src1].src);
|
|
|
|
|
|
|
|
|
|
if (const1 != NULL) {
|
|
|
|
|
/* Assume that constant folding will eliminate source mods and unary
|
|
|
|
|
* ops.
|
|
|
|
|
*/
|
|
|
|
|
if (parity)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
const nir_const_value *const const2 =
|
|
|
|
|
nir_src_as_const_value(alu2->src[src2].src);
|
|
|
|
|
|
|
|
|
|
if (const2 == NULL)
|
|
|
|
|
return false;
|
|
|
|
|
|
2019-06-13 14:19:11 -07:00
|
|
|
if (nir_src_bit_size(alu1->src[src1].src) !=
|
|
|
|
|
nir_src_bit_size(alu2->src[src2].src))
|
|
|
|
|
return false;
|
|
|
|
|
|
2019-06-13 14:06:55 -07:00
|
|
|
const nir_alu_type full_type = nir_op_infos[alu1->op].input_types[src1] |
|
|
|
|
|
nir_src_bit_size(alu1->src[src1].src);
|
nir: Handle swizzle in nir_alu_srcs_negative_equal
When I added this function, I was not sure if swizzles of immediate
values were a thing that occurred in NIR. The only existing user of
these functions is the partial redundancy elimination for compares.
Since comparison instructions are inherently scalar, this does not
occur.
However, a couple later patches, "nir/algebraic: Recognize
open-coded flrp(-1, 1, a) and flrp(1, -1, a)" combined with "intel/vec4:
Try to emit a single load for multiple 3-src instruction operands",
collaborate to create a few thousand instances.
No shader-db changes on any Intel platform.
v2: Handle the swizzle in nir_alu_srcs_negative_equal and leave
nir_const_value_negative_equal unchanged. Suggested by Jason.
v3: Correctly handle write masks. Add note (and assertion) that the
caller is responsible for various compatibility checks. The single
existing caller only calls this for combinations of scalar fadd and
float comparison instructions, so all of the requirements are met. A
later patch (intel/vec4: Try to emit a single load for multiple 3-src
instruction operands) will call this for sources of the same
instruction, so all of the requirements are met.
v4: Add unit test for nir_opt_comparison_pre that is fixed by this
commit.
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-06-10 15:05:14 -07:00
|
|
|
for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++) {
|
|
|
|
|
if (nir_alu_instr_channel_used(alu1, src1, i) &&
|
|
|
|
|
!nir_const_value_negative_equal(const1[alu1->src[src1].swizzle[i]],
|
|
|
|
|
const2[alu2->src[src2].swizzle[i]],
|
|
|
|
|
full_type))
|
2019-06-13 14:06:55 -07:00
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
2018-05-22 18:18:07 -07:00
|
|
|
}
|
|
|
|
|
|
2020-09-08 18:36:47 -05:00
|
|
|
uint8_t alu1_swizzle[NIR_MAX_VEC_COMPONENTS] = {0};
|
2018-05-22 18:18:07 -07:00
|
|
|
nir_src alu1_actual_src;
|
2019-04-17 17:10:18 -05:00
|
|
|
nir_alu_instr *neg1 = get_neg_instr(alu1->src[src1].src);
|
2018-05-22 18:18:07 -07:00
|
|
|
|
|
|
|
|
if (neg1) {
|
|
|
|
|
parity = !parity;
|
|
|
|
|
alu1_actual_src = neg1->src[0].src;
|
|
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < nir_ssa_alu_instr_src_components(neg1, 0); i++)
|
|
|
|
|
alu1_swizzle[i] = neg1->src[0].swizzle[i];
|
|
|
|
|
} else {
|
|
|
|
|
alu1_actual_src = alu1->src[src1].src;
|
|
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < nir_ssa_alu_instr_src_components(alu1, src1); i++)
|
|
|
|
|
alu1_swizzle[i] = i;
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-08 18:36:47 -05:00
|
|
|
uint8_t alu2_swizzle[NIR_MAX_VEC_COMPONENTS] = {0};
|
2018-05-22 18:18:07 -07:00
|
|
|
nir_src alu2_actual_src;
|
2019-04-17 17:10:18 -05:00
|
|
|
nir_alu_instr *neg2 = get_neg_instr(alu2->src[src2].src);
|
2018-05-22 18:18:07 -07:00
|
|
|
|
|
|
|
|
if (neg2) {
|
|
|
|
|
parity = !parity;
|
|
|
|
|
alu2_actual_src = neg2->src[0].src;
|
|
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < nir_ssa_alu_instr_src_components(neg2, 0); i++)
|
|
|
|
|
alu2_swizzle[i] = neg2->src[0].swizzle[i];
|
|
|
|
|
} else {
|
|
|
|
|
alu2_actual_src = alu2->src[src2].src;
|
|
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < nir_ssa_alu_instr_src_components(alu2, src2); i++)
|
|
|
|
|
alu2_swizzle[i] = i;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < nir_ssa_alu_instr_src_components(alu1, src1); i++) {
|
|
|
|
|
if (alu1_swizzle[alu1->src[src1].swizzle[i]] !=
|
|
|
|
|
alu2_swizzle[alu2->src[src2].swizzle[i]])
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return parity && nir_srcs_equal(alu1_actual_src, alu2_actual_src);
|
|
|
|
|
}
|
|
|
|
|
|
2016-07-29 01:29:11 -07:00
|
|
|
bool
|
2015-09-24 01:05:15 -04:00
|
|
|
nir_alu_srcs_equal(const nir_alu_instr *alu1, const nir_alu_instr *alu2,
|
|
|
|
|
unsigned src1, unsigned src2)
|
2015-09-24 00:54:52 -04:00
|
|
|
{
|
|
|
|
|
if (alu1->src[src1].abs != alu2->src[src2].abs ||
|
|
|
|
|
alu1->src[src1].negate != alu2->src[src2].negate)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < nir_ssa_alu_instr_src_components(alu1, src1); i++) {
|
|
|
|
|
if (alu1->src[src1].swizzle[i] != alu2->src[src2].swizzle[i])
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return nir_srcs_equal(alu1->src[src1].src, alu2->src[src2].src);
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-24 01:57:04 -04:00
|
|
|
/* Returns "true" if two instructions are equal. Note that this will only
|
|
|
|
|
* work for the subset of instructions defined by instr_can_rewrite(). Also,
|
|
|
|
|
* it should only return "true" for instructions that hash_instr() will return
|
|
|
|
|
* the same hash for (ignoring collisions, of course).
|
|
|
|
|
*/
|
|
|
|
|
|
2019-06-20 13:47:30 -05:00
|
|
|
bool
|
2015-09-24 01:05:15 -04:00
|
|
|
nir_instrs_equal(const nir_instr *instr1, const nir_instr *instr2)
|
2015-09-24 00:54:52 -04:00
|
|
|
{
|
2019-06-20 13:47:30 -05:00
|
|
|
assert(instr_can_rewrite(instr1) && instr_can_rewrite(instr2));
|
|
|
|
|
|
2015-09-24 00:54:52 -04:00
|
|
|
if (instr1->type != instr2->type)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
switch (instr1->type) {
|
|
|
|
|
case nir_instr_type_alu: {
|
|
|
|
|
nir_alu_instr *alu1 = nir_instr_as_alu(instr1);
|
|
|
|
|
nir_alu_instr *alu2 = nir_instr_as_alu(instr2);
|
|
|
|
|
|
|
|
|
|
if (alu1->op != alu2->op)
|
|
|
|
|
return false;
|
|
|
|
|
|
2019-05-17 13:46:38 -07:00
|
|
|
/* We explicitly don't compare instr->exact. */
|
|
|
|
|
|
|
|
|
|
if (alu1->no_signed_wrap != alu2->no_signed_wrap)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
if (alu1->no_unsigned_wrap != alu2->no_unsigned_wrap)
|
|
|
|
|
return false;
|
|
|
|
|
|
2015-09-24 00:54:52 -04:00
|
|
|
/* TODO: We can probably acutally do something more inteligent such
|
|
|
|
|
* as allowing different numbers and taking a maximum or something
|
|
|
|
|
* here */
|
|
|
|
|
if (alu1->dest.dest.ssa.num_components != alu2->dest.dest.ssa.num_components)
|
|
|
|
|
return false;
|
|
|
|
|
|
2015-08-03 15:05:38 -07:00
|
|
|
if (alu1->dest.dest.ssa.bit_size != alu2->dest.dest.ssa.bit_size)
|
|
|
|
|
return false;
|
|
|
|
|
|
2019-05-09 15:27:14 -07:00
|
|
|
if (nir_op_infos[alu1->op].algebraic_properties & NIR_OP_IS_2SRC_COMMUTATIVE) {
|
2019-05-09 15:33:11 -07:00
|
|
|
if ((!nir_alu_srcs_equal(alu1, alu2, 0, 0) ||
|
|
|
|
|
!nir_alu_srcs_equal(alu1, alu2, 1, 1)) &&
|
|
|
|
|
(!nir_alu_srcs_equal(alu1, alu2, 0, 1) ||
|
|
|
|
|
!nir_alu_srcs_equal(alu1, alu2, 1, 0)))
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
for (unsigned i = 2; i < nir_op_infos[alu1->op].num_inputs; i++) {
|
|
|
|
|
if (!nir_alu_srcs_equal(alu1, alu2, i, i))
|
|
|
|
|
return false;
|
|
|
|
|
}
|
2015-09-24 00:54:52 -04:00
|
|
|
} else {
|
|
|
|
|
for (unsigned i = 0; i < nir_op_infos[alu1->op].num_inputs; i++) {
|
|
|
|
|
if (!nir_alu_srcs_equal(alu1, alu2, i, i))
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return true;
|
|
|
|
|
}
|
2018-03-14 21:45:38 -07:00
|
|
|
case nir_instr_type_deref: {
|
|
|
|
|
nir_deref_instr *deref1 = nir_instr_as_deref(instr1);
|
|
|
|
|
nir_deref_instr *deref2 = nir_instr_as_deref(instr2);
|
|
|
|
|
|
|
|
|
|
if (deref1->deref_type != deref2->deref_type ||
|
2020-10-30 12:14:05 -05:00
|
|
|
deref1->modes != deref2->modes ||
|
2018-03-14 21:45:38 -07:00
|
|
|
deref1->type != deref2->type)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
if (deref1->deref_type == nir_deref_type_var)
|
|
|
|
|
return deref1->var == deref2->var;
|
|
|
|
|
|
|
|
|
|
if (!nir_srcs_equal(deref1->parent, deref2->parent))
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
switch (deref1->deref_type) {
|
|
|
|
|
case nir_deref_type_struct:
|
|
|
|
|
if (deref1->strct.index != deref2->strct.index)
|
|
|
|
|
return false;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case nir_deref_type_array:
|
2018-11-28 12:26:52 -06:00
|
|
|
case nir_deref_type_ptr_as_array:
|
2018-03-14 21:45:38 -07:00
|
|
|
if (!nir_srcs_equal(deref1->arr.index, deref2->arr.index))
|
|
|
|
|
return false;
|
|
|
|
|
break;
|
|
|
|
|
|
2018-11-28 12:26:52 -06:00
|
|
|
case nir_deref_type_cast:
|
2020-08-24 09:51:04 -05:00
|
|
|
if (deref1->cast.ptr_stride != deref2->cast.ptr_stride ||
|
|
|
|
|
deref1->cast.align_mul != deref2->cast.align_mul ||
|
|
|
|
|
deref1->cast.align_offset != deref2->cast.align_offset)
|
2018-11-28 12:26:52 -06:00
|
|
|
return false;
|
|
|
|
|
break;
|
|
|
|
|
|
2018-03-14 21:45:38 -07:00
|
|
|
case nir_deref_type_var:
|
|
|
|
|
case nir_deref_type_array_wildcard:
|
|
|
|
|
/* Nothing to do */
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
unreachable("Invalid instruction deref type");
|
|
|
|
|
}
|
2018-07-25 15:07:08 -07:00
|
|
|
return true;
|
2018-03-14 21:45:38 -07:00
|
|
|
}
|
2015-09-24 00:54:52 -04:00
|
|
|
case nir_instr_type_tex: {
|
|
|
|
|
nir_tex_instr *tex1 = nir_instr_as_tex(instr1);
|
|
|
|
|
nir_tex_instr *tex2 = nir_instr_as_tex(instr2);
|
|
|
|
|
|
|
|
|
|
if (tex1->op != tex2->op)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
if (tex1->num_srcs != tex2->num_srcs)
|
|
|
|
|
return false;
|
|
|
|
|
for (unsigned i = 0; i < tex1->num_srcs; i++) {
|
|
|
|
|
if (tex1->src[i].src_type != tex2->src[i].src_type ||
|
|
|
|
|
!nir_srcs_equal(tex1->src[i].src, tex2->src[i].src)) {
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (tex1->coord_components != tex2->coord_components ||
|
|
|
|
|
tex1->sampler_dim != tex2->sampler_dim ||
|
|
|
|
|
tex1->is_array != tex2->is_array ||
|
|
|
|
|
tex1->is_shadow != tex2->is_shadow ||
|
|
|
|
|
tex1->is_new_style_shadow != tex2->is_new_style_shadow ||
|
|
|
|
|
tex1->component != tex2->component ||
|
2016-02-06 09:05:10 -08:00
|
|
|
tex1->texture_index != tex2->texture_index ||
|
2015-11-02 17:58:29 -08:00
|
|
|
tex1->sampler_index != tex2->sampler_index) {
|
2015-09-24 00:54:52 -04:00
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2019-03-18 21:23:59 +01:00
|
|
|
if (memcmp(tex1->tg4_offsets, tex2->tg4_offsets,
|
|
|
|
|
sizeof(tex1->tg4_offsets)))
|
|
|
|
|
return false;
|
|
|
|
|
|
2015-09-24 00:54:52 -04:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
case nir_instr_type_load_const: {
|
|
|
|
|
nir_load_const_instr *load1 = nir_instr_as_load_const(instr1);
|
|
|
|
|
nir_load_const_instr *load2 = nir_instr_as_load_const(instr2);
|
|
|
|
|
|
|
|
|
|
if (load1->def.num_components != load2->def.num_components)
|
|
|
|
|
return false;
|
|
|
|
|
|
2015-08-03 15:05:38 -07:00
|
|
|
if (load1->def.bit_size != load2->def.bit_size)
|
|
|
|
|
return false;
|
|
|
|
|
|
2019-04-01 21:42:37 -05:00
|
|
|
if (load1->def.bit_size == 1) {
|
|
|
|
|
for (unsigned i = 0; i < load1->def.num_components; ++i) {
|
2019-03-27 00:59:03 +01:00
|
|
|
if (load1->value[i].b != load2->value[i].b)
|
|
|
|
|
return false;
|
|
|
|
|
}
|
2019-04-01 21:42:37 -05:00
|
|
|
} else {
|
|
|
|
|
unsigned size = load1->def.num_components * sizeof(*load1->value);
|
|
|
|
|
if (memcmp(load1->value, load2->value, size) != 0)
|
|
|
|
|
return false;
|
2018-10-18 11:59:40 -05:00
|
|
|
}
|
2019-03-27 00:59:03 +01:00
|
|
|
return true;
|
2015-09-24 00:54:52 -04:00
|
|
|
}
|
|
|
|
|
case nir_instr_type_phi: {
|
|
|
|
|
nir_phi_instr *phi1 = nir_instr_as_phi(instr1);
|
|
|
|
|
nir_phi_instr *phi2 = nir_instr_as_phi(instr2);
|
|
|
|
|
|
|
|
|
|
if (phi1->instr.block != phi2->instr.block)
|
|
|
|
|
return false;
|
|
|
|
|
|
2016-04-26 20:16:21 -07:00
|
|
|
nir_foreach_phi_src(src1, phi1) {
|
|
|
|
|
nir_foreach_phi_src(src2, phi2) {
|
2015-09-24 00:54:52 -04:00
|
|
|
if (src1->pred == src2->pred) {
|
|
|
|
|
if (!nir_srcs_equal(src1->src, src2->src))
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
case nir_instr_type_intrinsic: {
|
|
|
|
|
nir_intrinsic_instr *intrinsic1 = nir_instr_as_intrinsic(instr1);
|
|
|
|
|
nir_intrinsic_instr *intrinsic2 = nir_instr_as_intrinsic(instr2);
|
|
|
|
|
const nir_intrinsic_info *info =
|
|
|
|
|
&nir_intrinsic_infos[intrinsic1->intrinsic];
|
|
|
|
|
|
|
|
|
|
if (intrinsic1->intrinsic != intrinsic2->intrinsic ||
|
|
|
|
|
intrinsic1->num_components != intrinsic2->num_components)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
if (info->has_dest && intrinsic1->dest.ssa.num_components !=
|
|
|
|
|
intrinsic2->dest.ssa.num_components)
|
|
|
|
|
return false;
|
|
|
|
|
|
2015-08-03 15:05:38 -07:00
|
|
|
if (info->has_dest && intrinsic1->dest.ssa.bit_size !=
|
|
|
|
|
intrinsic2->dest.ssa.bit_size)
|
|
|
|
|
return false;
|
|
|
|
|
|
2015-09-24 00:54:52 -04:00
|
|
|
for (unsigned i = 0; i < info->num_srcs; i++) {
|
|
|
|
|
if (!nir_srcs_equal(intrinsic1->src[i], intrinsic2->src[i]))
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < info->num_indices; i++) {
|
|
|
|
|
if (intrinsic1->const_index[i] != intrinsic2->const_index[i])
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
case nir_instr_type_call:
|
|
|
|
|
case nir_instr_type_jump:
|
|
|
|
|
case nir_instr_type_ssa_undef:
|
|
|
|
|
case nir_instr_type_parallel_copy:
|
|
|
|
|
default:
|
|
|
|
|
unreachable("Invalid instruction type");
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-25 15:07:08 -07:00
|
|
|
unreachable("All cases in the above switch should return");
|
2015-09-24 00:54:52 -04:00
|
|
|
}
|
|
|
|
|
|
2015-09-24 01:57:04 -04:00
|
|
|
static nir_ssa_def *
|
|
|
|
|
nir_instr_get_dest_ssa_def(nir_instr *instr)
|
|
|
|
|
{
|
|
|
|
|
switch (instr->type) {
|
|
|
|
|
case nir_instr_type_alu:
|
|
|
|
|
assert(nir_instr_as_alu(instr)->dest.dest.is_ssa);
|
|
|
|
|
return &nir_instr_as_alu(instr)->dest.dest.ssa;
|
2018-03-14 21:45:38 -07:00
|
|
|
case nir_instr_type_deref:
|
|
|
|
|
assert(nir_instr_as_deref(instr)->dest.is_ssa);
|
|
|
|
|
return &nir_instr_as_deref(instr)->dest.ssa;
|
2015-09-24 01:57:04 -04:00
|
|
|
case nir_instr_type_load_const:
|
|
|
|
|
return &nir_instr_as_load_const(instr)->def;
|
|
|
|
|
case nir_instr_type_phi:
|
|
|
|
|
assert(nir_instr_as_phi(instr)->dest.is_ssa);
|
|
|
|
|
return &nir_instr_as_phi(instr)->dest.ssa;
|
|
|
|
|
case nir_instr_type_intrinsic:
|
|
|
|
|
assert(nir_instr_as_intrinsic(instr)->dest.is_ssa);
|
|
|
|
|
return &nir_instr_as_intrinsic(instr)->dest.ssa;
|
|
|
|
|
case nir_instr_type_tex:
|
|
|
|
|
assert(nir_instr_as_tex(instr)->dest.is_ssa);
|
|
|
|
|
return &nir_instr_as_tex(instr)->dest.ssa;
|
|
|
|
|
default:
|
|
|
|
|
unreachable("We never ask for any of these");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static bool
|
|
|
|
|
cmp_func(const void *data1, const void *data2)
|
|
|
|
|
{
|
|
|
|
|
return nir_instrs_equal(data1, data2);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
struct set *
|
|
|
|
|
nir_instr_set_create(void *mem_ctx)
|
|
|
|
|
{
|
|
|
|
|
return _mesa_set_create(mem_ctx, hash_instr, cmp_func);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
nir_instr_set_destroy(struct set *instr_set)
|
|
|
|
|
{
|
|
|
|
|
_mesa_set_destroy(instr_set, NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool
|
|
|
|
|
nir_instr_set_add_or_rewrite(struct set *instr_set, nir_instr *instr)
|
|
|
|
|
{
|
|
|
|
|
if (!instr_can_rewrite(instr))
|
|
|
|
|
return false;
|
|
|
|
|
|
2019-03-27 12:11:36 +01:00
|
|
|
struct set_entry *e = _mesa_set_search_or_add(instr_set, instr);
|
|
|
|
|
nir_instr *match = (nir_instr *) e->key;
|
|
|
|
|
if (match != instr) {
|
2015-09-24 01:57:04 -04:00
|
|
|
nir_ssa_def *def = nir_instr_get_dest_ssa_def(instr);
|
2016-03-17 11:38:54 -07:00
|
|
|
nir_ssa_def *new_def = nir_instr_get_dest_ssa_def(match);
|
|
|
|
|
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Remove wrongly repeated words in comments
Clean up misrepetitions ('if if', 'the the' etc) found throughout the
comments. This has been done manually, after grepping
case-insensitively for duplicate if, is, the, then, do, for, an,
plus a few other typos corrected in fly-by
v2:
* proper commit message and non-joke title;
* replace two 'as is' followed by 'is' to 'as-is'.
v3:
* 'a integer' => 'an integer' and similar (originally spotted by
Jason Ekstrand, I fixed a few other similar ones while at it)
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-06-23 19:20:18 +02:00
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/* It's safe to replace an exact instruction with an inexact one as
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2016-03-17 11:38:54 -07:00
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* long as we make it exact. If we got here, the two instructions are
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* exactly identical in every other way so, once we've set the exact
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* bit, they are the same.
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*/
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if (instr->type == nir_instr_type_alu && nir_instr_as_alu(instr)->exact)
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nir_instr_as_alu(match)->exact = true;
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2015-09-24 01:57:04 -04:00
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nir_ssa_def_rewrite_uses(def, nir_src_for_ssa(new_def));
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return true;
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}
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return false;
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}
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void
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nir_instr_set_remove(struct set *instr_set, nir_instr *instr)
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{
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if (!instr_can_rewrite(instr))
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return;
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struct set_entry *entry = _mesa_set_search(instr_set, instr);
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if (entry)
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_mesa_set_remove(instr_set, entry);
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}
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