2014-05-19 10:17:51 -07:00
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_cfg.h"
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2014-06-28 20:37:56 -07:00
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#include "brw_eu.h"
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2024-01-24 22:43:58 -08:00
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#include "brw_disasm.h"
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2017-11-16 11:43:51 -08:00
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#include "brw_disasm_info.h"
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2021-04-05 10:44:41 -07:00
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#include "dev/intel_debug.h"
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2016-01-18 12:54:03 +02:00
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#include "compiler/nir/nir.h"
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2014-05-19 10:17:51 -07:00
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brw: Fix printing of blocks in disassembly when BRW is available
When disassembling and BRW IR is available (which happens in the
generator), there will be pointers to the BRW's basic block structures
that are used to print the block numbers and predecessor/successors
in the output.
There are two challenges:
- Because DO and FLOW instructions are not real instructions, they are
not emitted in the output but would still cause the output to contain
empty blocks. Previous code accounted for DO but still had problems.
- DO blocks have special physical links that don't make sense when the
DO is not emitted at the end, but they would be shown even if that
block was omitted.
These issues can be seen here (edited to remove non-essential bits)
```
START B0 (2 cycles)
mov(8) g126<1>UD 0x3f800000UD
END B0 ->B1
START B2 <-B1 <-B4 (0 cycles)
END B2 ->B3
START B3 <-B2 (260 cycles)
LABEL1:
mov(8) g1<1>D 0D
cmp.ge.f0.0(8) null<1>D g2<0,1,0>D 10D
sync nop(1) null<0,1,0>UB
send(1) g0UD g1UD nullUD
(+f0.0) break(8) JIP: LABEL0 UIP: LABEL0
END B3 ->B1 ->B5 ->B4
START B4 <-B3 (1000 cycles)
sync nop(1) null<0,1,0>UB
mov(8) g126<1>UD g0<0,1,0>UD
LABEL0:
while(8) JIP: LABEL1
END B4 ->B2
START B5 <-B1 <-B3 (20 cycles)
```
For example:
- Block 1 is missing (a skipped DO block)
- Block 2 is empty (it was a FLOW block)
- Block 3 ends with a link to Block 1 (the special links involving DO
blocks).
Two key changes were made to fix this. First, skip the DO and FLOW
blocks completely. The use_tail ensures that the instruction group is
reused to avoid empty blocks. Second, when printing, the successors and
predecessors, walk through the skipped blocks. And finally, don't print
the special blocks.
With the fix, here's the output. Note the blocks retain their original
BRW IR number.
```
START B0 (2 cycles)
mov(8) g127<1>UD 0x3f800000UD
END B0 ->B3
START B3 <-B0 <-B4 (260 cycles)
LABEL1:
mov(8) g1<1>D 0D
cmp.ge.f0.0(8) null<1>D g2<0,1,0>D 10D
sync nop(1) null<0,1,0>UB
send(1) g0UD g1UD nullUD
(+f0.0) break(8) JIP: LABEL0 UIP: LABEL0
END B3 ->B5 ->B4
START B4 <-B3 (1000 cycles)
sync nop(1) null<0,1,0>UB
mov(8) g127<1>UD g0<0,1,0>UD
LABEL0:
while(8) JIP: LABEL1
END B4 ->B3
START B5 <-B3 (20 cycles)
```
Issue was spotted by Ken.
Fixes: d2c39b17793 ("intel/brw: Always have a (non-DO) block after a DO in the CFG")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36226>
2025-07-18 09:40:23 -07:00
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static bool
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is_do_block(struct bblock_t *block)
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{
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return block->start()->opcode == BRW_OPCODE_DO;
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}
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static bool
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is_flow_block(struct bblock_t *block)
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{
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return block->start()->opcode == SHADER_OPCODE_FLOW;
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}
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static bool
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should_omit_link(struct bblock_t *block,
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struct bblock_link *link)
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{
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return link->kind == bblock_link_physical &&
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(is_do_block(block) || is_do_block(link->block));
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}
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static void
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print_successors_for_disasm(struct bblock_t *block)
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{
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brw_foreach_list_typed(struct bblock_link, succ, link,
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&block->children) {
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if (should_omit_link(block, succ))
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continue;
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if (is_do_block(succ->block) || is_flow_block(succ->block))
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print_successors_for_disasm(succ->block);
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else
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fprintf(stderr, " ->B%d", succ->block->num);
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}
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}
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static void
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print_predecessors_for_disasm(struct bblock_t *block)
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{
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brw_foreach_list_typed(struct bblock_link, pred, link,
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&block->parents) {
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if (should_omit_link(block, pred))
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continue;
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if (is_do_block(pred->block) || is_flow_block(pred->block))
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print_predecessors_for_disasm(pred->block);
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else
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fprintf(stderr, " <-B%d", pred->block->num);
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}
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}
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2014-05-19 10:17:51 -07:00
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void
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2019-06-03 14:55:23 +03:00
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dump_assembly(void *assembly, int start_offset, int end_offset,
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struct disasm_info *disasm, const unsigned *block_latency)
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2014-05-19 10:17:51 -07:00
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{
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2022-06-29 14:13:31 -07:00
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const struct brw_isa_info *isa = disasm->isa;
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2014-05-19 10:17:51 -07:00
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const char *last_annotation_string = NULL;
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2019-06-03 14:55:23 +03:00
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void *mem_ctx = ralloc_context(NULL);
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const struct brw_label *root_label =
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2022-06-29 14:13:31 -07:00
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brw_label_assembly(isa, assembly, start_offset, end_offset, mem_ctx);
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2019-06-03 14:55:23 +03:00
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2025-07-28 16:07:44 -04:00
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brw_foreach_list_typed(struct inst_group, group, link, &disasm->group_list) {
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struct brw_exec_node *next_node = brw_exec_node_get_next(&group->link);
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if (brw_exec_node_is_tail_sentinel(next_node))
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2017-11-15 17:08:42 -08:00
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break;
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2014-05-19 10:17:51 -07:00
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2017-11-15 17:08:42 -08:00
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struct inst_group *next =
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2025-07-28 16:07:44 -04:00
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brw_exec_node_data(struct inst_group, next_node, link);
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2017-11-15 17:08:42 -08:00
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int start_offset = group->offset;
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int end_offset = next->offset;
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if (group->block_start) {
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fprintf(stderr, " START B%d", group->block_start->num);
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brw: Fix printing of blocks in disassembly when BRW is available
When disassembling and BRW IR is available (which happens in the
generator), there will be pointers to the BRW's basic block structures
that are used to print the block numbers and predecessor/successors
in the output.
There are two challenges:
- Because DO and FLOW instructions are not real instructions, they are
not emitted in the output but would still cause the output to contain
empty blocks. Previous code accounted for DO but still had problems.
- DO blocks have special physical links that don't make sense when the
DO is not emitted at the end, but they would be shown even if that
block was omitted.
These issues can be seen here (edited to remove non-essential bits)
```
START B0 (2 cycles)
mov(8) g126<1>UD 0x3f800000UD
END B0 ->B1
START B2 <-B1 <-B4 (0 cycles)
END B2 ->B3
START B3 <-B2 (260 cycles)
LABEL1:
mov(8) g1<1>D 0D
cmp.ge.f0.0(8) null<1>D g2<0,1,0>D 10D
sync nop(1) null<0,1,0>UB
send(1) g0UD g1UD nullUD
(+f0.0) break(8) JIP: LABEL0 UIP: LABEL0
END B3 ->B1 ->B5 ->B4
START B4 <-B3 (1000 cycles)
sync nop(1) null<0,1,0>UB
mov(8) g126<1>UD g0<0,1,0>UD
LABEL0:
while(8) JIP: LABEL1
END B4 ->B2
START B5 <-B1 <-B3 (20 cycles)
```
For example:
- Block 1 is missing (a skipped DO block)
- Block 2 is empty (it was a FLOW block)
- Block 3 ends with a link to Block 1 (the special links involving DO
blocks).
Two key changes were made to fix this. First, skip the DO and FLOW
blocks completely. The use_tail ensures that the instruction group is
reused to avoid empty blocks. Second, when printing, the successors and
predecessors, walk through the skipped blocks. And finally, don't print
the special blocks.
With the fix, here's the output. Note the blocks retain their original
BRW IR number.
```
START B0 (2 cycles)
mov(8) g127<1>UD 0x3f800000UD
END B0 ->B3
START B3 <-B0 <-B4 (260 cycles)
LABEL1:
mov(8) g1<1>D 0D
cmp.ge.f0.0(8) null<1>D g2<0,1,0>D 10D
sync nop(1) null<0,1,0>UB
send(1) g0UD g1UD nullUD
(+f0.0) break(8) JIP: LABEL0 UIP: LABEL0
END B3 ->B5 ->B4
START B4 <-B3 (1000 cycles)
sync nop(1) null<0,1,0>UB
mov(8) g127<1>UD g0<0,1,0>UD
LABEL0:
while(8) JIP: LABEL1
END B4 ->B3
START B5 <-B3 (20 cycles)
```
Issue was spotted by Ken.
Fixes: d2c39b17793 ("intel/brw: Always have a (non-DO) block after a DO in the CFG")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36226>
2025-07-18 09:40:23 -07:00
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print_predecessors_for_disasm(group->block_start);
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2020-04-02 17:42:57 -07:00
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if (block_latency)
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fprintf(stderr, " (%u cycles)",
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block_latency[group->block_start->num]);
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fprintf(stderr, "\n");
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2014-05-19 10:17:51 -07:00
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}
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2017-11-15 17:08:42 -08:00
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if (last_annotation_string != group->annotation) {
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last_annotation_string = group->annotation;
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2014-05-19 10:17:51 -07:00
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if (last_annotation_string)
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fprintf(stderr, " %s\n", last_annotation_string);
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}
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2022-06-29 14:13:31 -07:00
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brw_disassemble(isa, assembly, start_offset, end_offset,
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2024-08-08 19:05:09 +00:00
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root_label, NULL, stderr);
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2014-05-19 10:17:51 -07:00
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2017-11-15 17:08:42 -08:00
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if (group->error) {
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fputs(group->error, stderr);
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2015-10-21 15:23:10 -07:00
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}
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2017-11-15 17:08:42 -08:00
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if (group->block_end) {
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fprintf(stderr, " END B%d", group->block_end->num);
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brw: Fix printing of blocks in disassembly when BRW is available
When disassembling and BRW IR is available (which happens in the
generator), there will be pointers to the BRW's basic block structures
that are used to print the block numbers and predecessor/successors
in the output.
There are two challenges:
- Because DO and FLOW instructions are not real instructions, they are
not emitted in the output but would still cause the output to contain
empty blocks. Previous code accounted for DO but still had problems.
- DO blocks have special physical links that don't make sense when the
DO is not emitted at the end, but they would be shown even if that
block was omitted.
These issues can be seen here (edited to remove non-essential bits)
```
START B0 (2 cycles)
mov(8) g126<1>UD 0x3f800000UD
END B0 ->B1
START B2 <-B1 <-B4 (0 cycles)
END B2 ->B3
START B3 <-B2 (260 cycles)
LABEL1:
mov(8) g1<1>D 0D
cmp.ge.f0.0(8) null<1>D g2<0,1,0>D 10D
sync nop(1) null<0,1,0>UB
send(1) g0UD g1UD nullUD
(+f0.0) break(8) JIP: LABEL0 UIP: LABEL0
END B3 ->B1 ->B5 ->B4
START B4 <-B3 (1000 cycles)
sync nop(1) null<0,1,0>UB
mov(8) g126<1>UD g0<0,1,0>UD
LABEL0:
while(8) JIP: LABEL1
END B4 ->B2
START B5 <-B1 <-B3 (20 cycles)
```
For example:
- Block 1 is missing (a skipped DO block)
- Block 2 is empty (it was a FLOW block)
- Block 3 ends with a link to Block 1 (the special links involving DO
blocks).
Two key changes were made to fix this. First, skip the DO and FLOW
blocks completely. The use_tail ensures that the instruction group is
reused to avoid empty blocks. Second, when printing, the successors and
predecessors, walk through the skipped blocks. And finally, don't print
the special blocks.
With the fix, here's the output. Note the blocks retain their original
BRW IR number.
```
START B0 (2 cycles)
mov(8) g127<1>UD 0x3f800000UD
END B0 ->B3
START B3 <-B0 <-B4 (260 cycles)
LABEL1:
mov(8) g1<1>D 0D
cmp.ge.f0.0(8) null<1>D g2<0,1,0>D 10D
sync nop(1) null<0,1,0>UB
send(1) g0UD g1UD nullUD
(+f0.0) break(8) JIP: LABEL0 UIP: LABEL0
END B3 ->B5 ->B4
START B4 <-B3 (1000 cycles)
sync nop(1) null<0,1,0>UB
mov(8) g127<1>UD g0<0,1,0>UD
LABEL0:
while(8) JIP: LABEL1
END B4 ->B3
START B5 <-B3 (20 cycles)
```
Issue was spotted by Ken.
Fixes: d2c39b17793 ("intel/brw: Always have a (non-DO) block after a DO in the CFG")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36226>
2025-07-18 09:40:23 -07:00
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print_successors_for_disasm(group->block_end);
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2014-05-19 10:17:51 -07:00
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fprintf(stderr, "\n");
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}
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}
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fprintf(stderr, "\n");
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2019-06-03 14:55:23 +03:00
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ralloc_free(mem_ctx);
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2014-05-19 10:17:51 -07:00
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}
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2014-06-29 18:11:29 -07:00
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2017-11-15 17:08:42 -08:00
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struct disasm_info *
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2022-06-29 14:13:31 -07:00
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disasm_initialize(const struct brw_isa_info *isa,
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2017-11-15 17:08:42 -08:00
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const struct cfg_t *cfg)
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2014-06-29 18:11:29 -07:00
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{
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2017-11-15 17:08:42 -08:00
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struct disasm_info *disasm = ralloc(NULL, struct disasm_info);
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2025-07-28 16:07:44 -04:00
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brw_exec_list_make_empty(&disasm->group_list);
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2022-06-29 14:13:31 -07:00
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disasm->isa = isa;
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2017-11-15 17:08:42 -08:00
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disasm->cfg = cfg;
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disasm->cur_block = 0;
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disasm->use_tail = false;
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return disasm;
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2015-10-21 15:23:10 -07:00
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}
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2017-11-15 17:08:42 -08:00
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struct inst_group *
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2024-02-29 17:53:53 -08:00
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disasm_new_inst_group(struct disasm_info *disasm, int next_inst_offset)
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2015-10-21 15:23:10 -07:00
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{
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2024-02-29 17:53:53 -08:00
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assert(next_inst_offset >= 0);
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2017-11-15 17:08:42 -08:00
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struct inst_group *tail = rzalloc(disasm, struct inst_group);
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tail->offset = next_inst_offset;
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2025-07-28 16:07:44 -04:00
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brw_exec_list_push_tail(&disasm->group_list, &tail->link);
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2017-11-15 17:08:42 -08:00
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return tail;
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}
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2015-10-21 15:23:10 -07:00
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2017-11-15 17:08:42 -08:00
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void
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disasm_annotate(struct disasm_info *disasm,
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2024-12-07 00:23:07 -08:00
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brw_inst *inst, int offset)
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2017-11-15 17:08:42 -08:00
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{
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const struct cfg_t *cfg = disasm->cfg;
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struct inst_group *group;
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if (!disasm->use_tail) {
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group = disasm_new_inst_group(disasm, offset);
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} else {
|
2018-01-31 11:09:36 -08:00
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disasm->use_tail = false;
|
2025-07-28 16:07:44 -04:00
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group = brw_exec_node_data(struct inst_group,
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brw_exec_list_get_tail_raw(&disasm->group_list), link);
|
2017-11-15 17:08:42 -08:00
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}
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2015-10-21 15:23:10 -07:00
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2024-08-23 10:46:13 -07:00
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#ifndef NDEBUG
|
2021-10-13 11:21:41 +02:00
|
|
|
if (INTEL_DEBUG(DEBUG_ANNOTATION)) {
|
2017-11-15 17:08:42 -08:00
|
|
|
group->annotation = inst->annotation;
|
2014-06-29 18:11:29 -07:00
|
|
|
}
|
2024-08-23 10:46:13 -07:00
|
|
|
#endif
|
2014-06-29 18:11:29 -07:00
|
|
|
|
brw: Fix printing of blocks in disassembly when BRW is available
When disassembling and BRW IR is available (which happens in the
generator), there will be pointers to the BRW's basic block structures
that are used to print the block numbers and predecessor/successors
in the output.
There are two challenges:
- Because DO and FLOW instructions are not real instructions, they are
not emitted in the output but would still cause the output to contain
empty blocks. Previous code accounted for DO but still had problems.
- DO blocks have special physical links that don't make sense when the
DO is not emitted at the end, but they would be shown even if that
block was omitted.
These issues can be seen here (edited to remove non-essential bits)
```
START B0 (2 cycles)
mov(8) g126<1>UD 0x3f800000UD
END B0 ->B1
START B2 <-B1 <-B4 (0 cycles)
END B2 ->B3
START B3 <-B2 (260 cycles)
LABEL1:
mov(8) g1<1>D 0D
cmp.ge.f0.0(8) null<1>D g2<0,1,0>D 10D
sync nop(1) null<0,1,0>UB
send(1) g0UD g1UD nullUD
(+f0.0) break(8) JIP: LABEL0 UIP: LABEL0
END B3 ->B1 ->B5 ->B4
START B4 <-B3 (1000 cycles)
sync nop(1) null<0,1,0>UB
mov(8) g126<1>UD g0<0,1,0>UD
LABEL0:
while(8) JIP: LABEL1
END B4 ->B2
START B5 <-B1 <-B3 (20 cycles)
```
For example:
- Block 1 is missing (a skipped DO block)
- Block 2 is empty (it was a FLOW block)
- Block 3 ends with a link to Block 1 (the special links involving DO
blocks).
Two key changes were made to fix this. First, skip the DO and FLOW
blocks completely. The use_tail ensures that the instruction group is
reused to avoid empty blocks. Second, when printing, the successors and
predecessors, walk through the skipped blocks. And finally, don't print
the special blocks.
With the fix, here's the output. Note the blocks retain their original
BRW IR number.
```
START B0 (2 cycles)
mov(8) g127<1>UD 0x3f800000UD
END B0 ->B3
START B3 <-B0 <-B4 (260 cycles)
LABEL1:
mov(8) g1<1>D 0D
cmp.ge.f0.0(8) null<1>D g2<0,1,0>D 10D
sync nop(1) null<0,1,0>UB
send(1) g0UD g1UD nullUD
(+f0.0) break(8) JIP: LABEL0 UIP: LABEL0
END B3 ->B5 ->B4
START B4 <-B3 (1000 cycles)
sync nop(1) null<0,1,0>UB
mov(8) g127<1>UD g0<0,1,0>UD
LABEL0:
while(8) JIP: LABEL1
END B4 ->B3
START B5 <-B3 (20 cycles)
```
Issue was spotted by Ken.
Fixes: d2c39b17793 ("intel/brw: Always have a (non-DO) block after a DO in the CFG")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36226>
2025-07-18 09:40:23 -07:00
|
|
|
if (inst->opcode == BRW_OPCODE_DO ||
|
|
|
|
|
inst->opcode == SHADER_OPCODE_FLOW) {
|
|
|
|
|
disasm->use_tail = true;
|
|
|
|
|
disasm->cur_block++;
|
|
|
|
|
return;
|
2014-06-29 18:11:29 -07:00
|
|
|
}
|
|
|
|
|
|
brw: Fix printing of blocks in disassembly when BRW is available
When disassembling and BRW IR is available (which happens in the
generator), there will be pointers to the BRW's basic block structures
that are used to print the block numbers and predecessor/successors
in the output.
There are two challenges:
- Because DO and FLOW instructions are not real instructions, they are
not emitted in the output but would still cause the output to contain
empty blocks. Previous code accounted for DO but still had problems.
- DO blocks have special physical links that don't make sense when the
DO is not emitted at the end, but they would be shown even if that
block was omitted.
These issues can be seen here (edited to remove non-essential bits)
```
START B0 (2 cycles)
mov(8) g126<1>UD 0x3f800000UD
END B0 ->B1
START B2 <-B1 <-B4 (0 cycles)
END B2 ->B3
START B3 <-B2 (260 cycles)
LABEL1:
mov(8) g1<1>D 0D
cmp.ge.f0.0(8) null<1>D g2<0,1,0>D 10D
sync nop(1) null<0,1,0>UB
send(1) g0UD g1UD nullUD
(+f0.0) break(8) JIP: LABEL0 UIP: LABEL0
END B3 ->B1 ->B5 ->B4
START B4 <-B3 (1000 cycles)
sync nop(1) null<0,1,0>UB
mov(8) g126<1>UD g0<0,1,0>UD
LABEL0:
while(8) JIP: LABEL1
END B4 ->B2
START B5 <-B1 <-B3 (20 cycles)
```
For example:
- Block 1 is missing (a skipped DO block)
- Block 2 is empty (it was a FLOW block)
- Block 3 ends with a link to Block 1 (the special links involving DO
blocks).
Two key changes were made to fix this. First, skip the DO and FLOW
blocks completely. The use_tail ensures that the instruction group is
reused to avoid empty blocks. Second, when printing, the successors and
predecessors, walk through the skipped blocks. And finally, don't print
the special blocks.
With the fix, here's the output. Note the blocks retain their original
BRW IR number.
```
START B0 (2 cycles)
mov(8) g127<1>UD 0x3f800000UD
END B0 ->B3
START B3 <-B0 <-B4 (260 cycles)
LABEL1:
mov(8) g1<1>D 0D
cmp.ge.f0.0(8) null<1>D g2<0,1,0>D 10D
sync nop(1) null<0,1,0>UB
send(1) g0UD g1UD nullUD
(+f0.0) break(8) JIP: LABEL0 UIP: LABEL0
END B3 ->B5 ->B4
START B4 <-B3 (1000 cycles)
sync nop(1) null<0,1,0>UB
mov(8) g127<1>UD g0<0,1,0>UD
LABEL0:
while(8) JIP: LABEL1
END B4 ->B3
START B5 <-B3 (20 cycles)
```
Issue was spotted by Ken.
Fixes: d2c39b17793 ("intel/brw: Always have a (non-DO) block after a DO in the CFG")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36226>
2025-07-18 09:40:23 -07:00
|
|
|
if (cfg->blocks[disasm->cur_block]->start() == inst) {
|
|
|
|
|
group->block_start = cfg->blocks[disasm->cur_block];
|
2014-06-29 18:11:29 -07:00
|
|
|
}
|
2015-11-19 00:45:49 -08:00
|
|
|
|
2025-03-07 19:47:01 -08:00
|
|
|
if (cfg->blocks[disasm->cur_block]->end() == inst) {
|
2017-11-15 17:08:42 -08:00
|
|
|
group->block_end = cfg->blocks[disasm->cur_block];
|
|
|
|
|
disasm->cur_block++;
|
2014-06-29 18:11:29 -07:00
|
|
|
}
|
|
|
|
|
}
|
2015-10-21 15:23:10 -07:00
|
|
|
|
|
|
|
|
void
|
2024-02-29 17:53:53 -08:00
|
|
|
disasm_insert_error(struct disasm_info *disasm, int offset,
|
|
|
|
|
int inst_size, const char *error)
|
2015-10-21 15:23:10 -07:00
|
|
|
{
|
2025-07-28 16:07:44 -04:00
|
|
|
brw_foreach_list_typed(struct inst_group, cur, link, &disasm->group_list) {
|
|
|
|
|
struct brw_exec_node *next_node = brw_exec_node_get_next(&cur->link);
|
|
|
|
|
if (brw_exec_node_is_tail_sentinel(next_node))
|
2017-11-15 17:08:42 -08:00
|
|
|
break;
|
2015-11-13 12:13:14 -08:00
|
|
|
|
2017-11-15 17:08:42 -08:00
|
|
|
struct inst_group *next =
|
2025-07-28 16:07:44 -04:00
|
|
|
brw_exec_node_data(struct inst_group, next_node, link);
|
2015-10-21 15:23:10 -07:00
|
|
|
|
|
|
|
|
if (next->offset <= offset)
|
|
|
|
|
continue;
|
|
|
|
|
|
2022-07-19 00:27:29 -07:00
|
|
|
if (offset + inst_size != next->offset) {
|
2024-02-29 17:53:53 -08:00
|
|
|
struct inst_group *new_group = ralloc(disasm, struct inst_group);
|
|
|
|
|
memcpy(new_group, cur, sizeof(struct inst_group));
|
2017-11-15 17:08:42 -08:00
|
|
|
|
2015-10-21 15:23:10 -07:00
|
|
|
cur->error = NULL;
|
|
|
|
|
cur->error_length = 0;
|
|
|
|
|
cur->block_end = NULL;
|
2017-11-15 17:08:42 -08:00
|
|
|
|
2024-02-29 17:53:53 -08:00
|
|
|
new_group->offset = offset + inst_size;
|
|
|
|
|
new_group->block_start = NULL;
|
2017-11-15 17:08:42 -08:00
|
|
|
|
2025-07-28 16:07:44 -04:00
|
|
|
brw_exec_node_insert_after(&cur->link, &new_group->link);
|
2015-10-21 15:23:10 -07:00
|
|
|
}
|
|
|
|
|
|
2017-11-16 13:42:41 -08:00
|
|
|
if (cur->error)
|
|
|
|
|
ralloc_strcat(&cur->error, error);
|
|
|
|
|
else
|
2017-11-15 17:08:42 -08:00
|
|
|
cur->error = ralloc_strdup(disasm, error);
|
2017-11-16 13:42:41 -08:00
|
|
|
return;
|
|
|
|
|
}
|
2015-10-21 15:23:10 -07:00
|
|
|
}
|